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bellardeaa728e2008-05-28 12:51:20 +00001/*
Blue Swirl10774992012-04-29 16:39:13 +00002 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
bellardeaa728e2008-05-28 12:51:20 +00004 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardeaa728e2008-05-28 12:51:20 +000019 */
Paolo Bonzini83dae092010-06-29 09:58:49 +020020
Peter Maydellb6a0aa02016-01-26 18:17:03 +000021#include "qemu/osdep.h"
Blue Swirl3e457172011-07-13 12:44:15 +000022#include "cpu.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/log.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070024#include "exec/helper-proto.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010025#include "exec/exec-all.h"
Paolo Bonzinif08b6172014-03-28 19:42:10 +010026#include "exec/cpu_ldst.h"
Paolo Bonzini508127e2016-01-07 16:55:28 +030027#include "exec/log.h"
Blue Swirl3e457172011-07-13 12:44:15 +000028
bellardeaa728e2008-05-28 12:51:20 +000029//#define DEBUG_PCALL
30
aliguorid12d51d2009-01-15 21:48:06 +000031#ifdef DEBUG_PCALL
Blue Swirl20054ef2012-04-28 15:33:48 +000032# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
Andreas Färber8995b7a2013-07-03 01:07:10 +020033# define LOG_PCALL_STATE(cpu) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP)
aliguorid12d51d2009-01-15 21:48:06 +000035#else
Blue Swirl20054ef2012-04-28 15:33:48 +000036# define LOG_PCALL(...) do { } while (0)
Andreas Färber8995b7a2013-07-03 01:07:10 +020037# define LOG_PCALL_STATE(cpu) do { } while (0)
aliguorid12d51d2009-01-15 21:48:06 +000038#endif
39
Peter Maydell9220fe52015-01-20 15:19:34 +000040#ifdef CONFIG_USER_ONLY
41#define MEMSUFFIX _kernel
42#define DATA_SIZE 1
43#include "exec/cpu_ldst_useronly_template.h"
44
45#define DATA_SIZE 2
46#include "exec/cpu_ldst_useronly_template.h"
47
48#define DATA_SIZE 4
49#include "exec/cpu_ldst_useronly_template.h"
50
51#define DATA_SIZE 8
52#include "exec/cpu_ldst_useronly_template.h"
53#undef MEMSUFFIX
54#else
Paolo Bonzini8a201bd2014-03-28 11:43:45 +010055#define CPU_MMU_INDEX (cpu_mmu_index_kernel(env))
56#define MEMSUFFIX _kernel
57#define DATA_SIZE 1
58#include "exec/cpu_ldst_template.h"
59
60#define DATA_SIZE 2
61#include "exec/cpu_ldst_template.h"
62
63#define DATA_SIZE 4
64#include "exec/cpu_ldst_template.h"
65
66#define DATA_SIZE 8
67#include "exec/cpu_ldst_template.h"
68#undef CPU_MMU_INDEX
69#undef MEMSUFFIX
70#endif
71
bellardeaa728e2008-05-28 12:51:20 +000072/* return non zero if error */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030073static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
74 uint32_t *e2_ptr, int selector,
75 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +000076{
77 SegmentCache *dt;
78 int index;
79 target_ulong ptr;
80
Blue Swirl20054ef2012-04-28 15:33:48 +000081 if (selector & 0x4) {
bellardeaa728e2008-05-28 12:51:20 +000082 dt = &env->ldt;
Blue Swirl20054ef2012-04-28 15:33:48 +000083 } else {
bellardeaa728e2008-05-28 12:51:20 +000084 dt = &env->gdt;
Blue Swirl20054ef2012-04-28 15:33:48 +000085 }
bellardeaa728e2008-05-28 12:51:20 +000086 index = selector & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +000087 if ((index + 7) > dt->limit) {
bellardeaa728e2008-05-28 12:51:20 +000088 return -1;
Blue Swirl20054ef2012-04-28 15:33:48 +000089 }
bellardeaa728e2008-05-28 12:51:20 +000090 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030091 *e1_ptr = cpu_ldl_kernel_ra(env, ptr, retaddr);
92 *e2_ptr = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +000093 return 0;
94}
95
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +030096static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
97 uint32_t *e2_ptr, int selector)
98{
99 return load_segment_ra(env, e1_ptr, e2_ptr, selector, 0);
100}
101
bellardeaa728e2008-05-28 12:51:20 +0000102static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
103{
104 unsigned int limit;
Blue Swirl20054ef2012-04-28 15:33:48 +0000105
bellardeaa728e2008-05-28 12:51:20 +0000106 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
Blue Swirl20054ef2012-04-28 15:33:48 +0000107 if (e2 & DESC_G_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000108 limit = (limit << 12) | 0xfff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000109 }
bellardeaa728e2008-05-28 12:51:20 +0000110 return limit;
111}
112
113static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
114{
Blue Swirl20054ef2012-04-28 15:33:48 +0000115 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
bellardeaa728e2008-05-28 12:51:20 +0000116}
117
Blue Swirl20054ef2012-04-28 15:33:48 +0000118static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
119 uint32_t e2)
bellardeaa728e2008-05-28 12:51:20 +0000120{
121 sc->base = get_seg_base(e1, e2);
122 sc->limit = get_seg_limit(e1, e2);
123 sc->flags = e2;
124}
125
126/* init the segment cache in vm86 mode. */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000127static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
bellardeaa728e2008-05-28 12:51:20 +0000128{
129 selector &= 0xffff;
Paolo Bonzinib98dbc92014-05-15 16:07:04 +0200130
131 cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff,
132 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
133 DESC_A_MASK | (3 << DESC_DPL_SHIFT));
bellardeaa728e2008-05-28 12:51:20 +0000134}
135
Blue Swirl2999a0b2012-04-29 19:47:06 +0000136static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300137 uint32_t *esp_ptr, int dpl,
138 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000139{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200140 X86CPU *cpu = x86_env_get_cpu(env);
bellardeaa728e2008-05-28 12:51:20 +0000141 int type, index, shift;
142
143#if 0
144 {
145 int i;
146 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
Blue Swirl20054ef2012-04-28 15:33:48 +0000147 for (i = 0; i < env->tr.limit; i++) {
bellardeaa728e2008-05-28 12:51:20 +0000148 printf("%02x ", env->tr.base[i]);
Blue Swirl20054ef2012-04-28 15:33:48 +0000149 if ((i & 7) == 7) {
150 printf("\n");
151 }
bellardeaa728e2008-05-28 12:51:20 +0000152 }
153 printf("\n");
154 }
155#endif
156
Blue Swirl20054ef2012-04-28 15:33:48 +0000157 if (!(env->tr.flags & DESC_P_MASK)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200158 cpu_abort(CPU(cpu), "invalid tss");
Blue Swirl20054ef2012-04-28 15:33:48 +0000159 }
bellardeaa728e2008-05-28 12:51:20 +0000160 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000161 if ((type & 7) != 1) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200162 cpu_abort(CPU(cpu), "invalid tss type");
Blue Swirl20054ef2012-04-28 15:33:48 +0000163 }
bellardeaa728e2008-05-28 12:51:20 +0000164 shift = type >> 3;
165 index = (dpl * 4 + 2) << shift;
Blue Swirl20054ef2012-04-28 15:33:48 +0000166 if (index + (4 << shift) - 1 > env->tr.limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300167 raise_exception_err_ra(env, EXCP0A_TSS, env->tr.selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000168 }
bellardeaa728e2008-05-28 12:51:20 +0000169 if (shift == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300170 *esp_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index, retaddr);
171 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000172 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300173 *esp_ptr = cpu_ldl_kernel_ra(env, env->tr.base + index, retaddr);
174 *ss_ptr = cpu_lduw_kernel_ra(env, env->tr.base + index + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000175 }
176}
177
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300178static void tss_load_seg(CPUX86State *env, int seg_reg, int selector, int cpl,
179 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000180{
181 uint32_t e1, e2;
Paolo Bonzinid3b54912014-05-15 18:19:17 +0200182 int rpl, dpl;
bellardeaa728e2008-05-28 12:51:20 +0000183
184 if ((selector & 0xfffc) != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300185 if (load_segment_ra(env, &e1, &e2, selector, retaddr) != 0) {
186 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000187 }
188 if (!(e2 & DESC_S_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300189 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000190 }
bellardeaa728e2008-05-28 12:51:20 +0000191 rpl = selector & 3;
192 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
bellardeaa728e2008-05-28 12:51:20 +0000193 if (seg_reg == R_CS) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000194 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300195 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000196 }
Blue Swirl20054ef2012-04-28 15:33:48 +0000197 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300198 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000199 }
bellardeaa728e2008-05-28 12:51:20 +0000200 } else if (seg_reg == R_SS) {
201 /* SS must be writable data */
Blue Swirl20054ef2012-04-28 15:33:48 +0000202 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300203 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000204 }
205 if (dpl != cpl || dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300206 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000207 }
bellardeaa728e2008-05-28 12:51:20 +0000208 } else {
209 /* not readable code */
Blue Swirl20054ef2012-04-28 15:33:48 +0000210 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300211 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000212 }
bellardeaa728e2008-05-28 12:51:20 +0000213 /* if data or non conforming code, checks the rights */
214 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000215 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300216 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000217 }
bellardeaa728e2008-05-28 12:51:20 +0000218 }
219 }
Blue Swirl20054ef2012-04-28 15:33:48 +0000220 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300221 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000222 }
bellardeaa728e2008-05-28 12:51:20 +0000223 cpu_x86_load_seg_cache(env, seg_reg, selector,
Blue Swirl20054ef2012-04-28 15:33:48 +0000224 get_seg_base(e1, e2),
225 get_seg_limit(e1, e2),
226 e2);
bellardeaa728e2008-05-28 12:51:20 +0000227 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +0000228 if (seg_reg == R_SS || seg_reg == R_CS) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300229 raise_exception_err_ra(env, EXCP0A_TSS, selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000230 }
bellardeaa728e2008-05-28 12:51:20 +0000231 }
232}
233
234#define SWITCH_TSS_JMP 0
235#define SWITCH_TSS_IRET 1
236#define SWITCH_TSS_CALL 2
237
238/* XXX: restore CPU state in registers (PowerPC case) */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300239static void switch_tss_ra(CPUX86State *env, int tss_selector,
240 uint32_t e1, uint32_t e2, int source,
241 uint32_t next_eip, uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +0000242{
243 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
244 target_ulong tss_base;
245 uint32_t new_regs[8], new_segs[6];
246 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
247 uint32_t old_eflags, eflags_mask;
248 SegmentCache *dt;
249 int index;
250 target_ulong ptr;
251
252 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000253 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
254 source);
bellardeaa728e2008-05-28 12:51:20 +0000255
256 /* if task gate, we read the TSS segment and we load it */
257 if (type == 5) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000258 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300259 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000260 }
bellardeaa728e2008-05-28 12:51:20 +0000261 tss_selector = e1 >> 16;
Blue Swirl20054ef2012-04-28 15:33:48 +0000262 if (tss_selector & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300263 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000264 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300265 if (load_segment_ra(env, &e1, &e2, tss_selector, retaddr) != 0) {
266 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000267 }
268 if (e2 & DESC_S_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300269 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000270 }
bellardeaa728e2008-05-28 12:51:20 +0000271 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000272 if ((type & 7) != 1) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300273 raise_exception_err_ra(env, EXCP0D_GPF, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000274 }
bellardeaa728e2008-05-28 12:51:20 +0000275 }
276
Blue Swirl20054ef2012-04-28 15:33:48 +0000277 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300278 raise_exception_err_ra(env, EXCP0B_NOSEG, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000279 }
bellardeaa728e2008-05-28 12:51:20 +0000280
Blue Swirl20054ef2012-04-28 15:33:48 +0000281 if (type & 8) {
bellardeaa728e2008-05-28 12:51:20 +0000282 tss_limit_max = 103;
Blue Swirl20054ef2012-04-28 15:33:48 +0000283 } else {
bellardeaa728e2008-05-28 12:51:20 +0000284 tss_limit_max = 43;
Blue Swirl20054ef2012-04-28 15:33:48 +0000285 }
bellardeaa728e2008-05-28 12:51:20 +0000286 tss_limit = get_seg_limit(e1, e2);
287 tss_base = get_seg_base(e1, e2);
288 if ((tss_selector & 4) != 0 ||
Blue Swirl20054ef2012-04-28 15:33:48 +0000289 tss_limit < tss_limit_max) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300290 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000291 }
bellardeaa728e2008-05-28 12:51:20 +0000292 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +0000293 if (old_type & 8) {
bellardeaa728e2008-05-28 12:51:20 +0000294 old_tss_limit_max = 103;
Blue Swirl20054ef2012-04-28 15:33:48 +0000295 } else {
bellardeaa728e2008-05-28 12:51:20 +0000296 old_tss_limit_max = 43;
Blue Swirl20054ef2012-04-28 15:33:48 +0000297 }
bellardeaa728e2008-05-28 12:51:20 +0000298
299 /* read all the registers from the new TSS */
300 if (type & 8) {
301 /* 32 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300302 new_cr3 = cpu_ldl_kernel_ra(env, tss_base + 0x1c, retaddr);
303 new_eip = cpu_ldl_kernel_ra(env, tss_base + 0x20, retaddr);
304 new_eflags = cpu_ldl_kernel_ra(env, tss_base + 0x24, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000305 for (i = 0; i < 8; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300306 new_regs[i] = cpu_ldl_kernel_ra(env, tss_base + (0x28 + i * 4),
307 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000308 }
309 for (i = 0; i < 6; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300310 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x48 + i * 4),
311 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000312 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300313 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x60, retaddr);
314 new_trap = cpu_ldl_kernel_ra(env, tss_base + 0x64, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000315 } else {
316 /* 16 bit */
317 new_cr3 = 0;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300318 new_eip = cpu_lduw_kernel_ra(env, tss_base + 0x0e, retaddr);
319 new_eflags = cpu_lduw_kernel_ra(env, tss_base + 0x10, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000320 for (i = 0; i < 8; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300321 new_regs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x12 + i * 2),
322 retaddr) | 0xffff0000;
Blue Swirl20054ef2012-04-28 15:33:48 +0000323 }
324 for (i = 0; i < 4; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300325 new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 4),
326 retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000327 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300328 new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000329 new_segs[R_FS] = 0;
330 new_segs[R_GS] = 0;
331 new_trap = 0;
332 }
Blue Swirl4581cbc2010-10-13 18:38:08 +0000333 /* XXX: avoid a compiler warning, see
334 http://support.amd.com/us/Processor_TechDocs/24593.pdf
335 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
336 (void)new_trap;
bellardeaa728e2008-05-28 12:51:20 +0000337
338 /* NOTE: we must avoid memory exceptions during the task switch,
339 so we make dummy accesses before */
340 /* XXX: it can still fail in some cases, so a bigger hack is
341 necessary to valid the TLB after having done the accesses */
342
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300343 v1 = cpu_ldub_kernel_ra(env, env->tr.base, retaddr);
344 v2 = cpu_ldub_kernel_ra(env, env->tr.base + old_tss_limit_max, retaddr);
345 cpu_stb_kernel_ra(env, env->tr.base, v1, retaddr);
346 cpu_stb_kernel_ra(env, env->tr.base + old_tss_limit_max, v2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000347
348 /* clear busy bit (it is restartable) */
349 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
350 target_ulong ptr;
351 uint32_t e2;
Blue Swirl20054ef2012-04-28 15:33:48 +0000352
bellardeaa728e2008-05-28 12:51:20 +0000353 ptr = env->gdt.base + (env->tr.selector & ~7);
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300354 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000355 e2 &= ~DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300356 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000357 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000358 old_eflags = cpu_compute_eflags(env);
Blue Swirl20054ef2012-04-28 15:33:48 +0000359 if (source == SWITCH_TSS_IRET) {
bellardeaa728e2008-05-28 12:51:20 +0000360 old_eflags &= ~NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +0000361 }
bellardeaa728e2008-05-28 12:51:20 +0000362
363 /* save the current state in the old TSS */
364 if (type & 8) {
365 /* 32 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300366 cpu_stl_kernel_ra(env, env->tr.base + 0x20, next_eip, retaddr);
367 cpu_stl_kernel_ra(env, env->tr.base + 0x24, old_eflags, retaddr);
368 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX], retaddr);
369 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX], retaddr);
370 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX], retaddr);
371 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX], retaddr);
372 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP], retaddr);
373 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP], retaddr);
374 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI], retaddr);
375 cpu_stl_kernel_ra(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI], retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000376 for (i = 0; i < 6; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300377 cpu_stw_kernel_ra(env, env->tr.base + (0x48 + i * 4),
378 env->segs[i].selector, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000379 }
bellardeaa728e2008-05-28 12:51:20 +0000380 } else {
381 /* 16 bit */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300382 cpu_stw_kernel_ra(env, env->tr.base + 0x0e, next_eip, retaddr);
383 cpu_stw_kernel_ra(env, env->tr.base + 0x10, old_eflags, retaddr);
384 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX], retaddr);
385 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX], retaddr);
386 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX], retaddr);
387 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX], retaddr);
388 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP], retaddr);
389 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP], retaddr);
390 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr);
391 cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000392 for (i = 0; i < 4; i++) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300393 cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 4),
394 env->segs[i].selector, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000395 }
bellardeaa728e2008-05-28 12:51:20 +0000396 }
397
398 /* now if an exception occurs, it will occurs in the next task
399 context */
400
401 if (source == SWITCH_TSS_CALL) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300402 cpu_stw_kernel_ra(env, tss_base, env->tr.selector, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000403 new_eflags |= NT_MASK;
404 }
405
406 /* set busy bit */
407 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
408 target_ulong ptr;
409 uint32_t e2;
Blue Swirl20054ef2012-04-28 15:33:48 +0000410
bellardeaa728e2008-05-28 12:51:20 +0000411 ptr = env->gdt.base + (tss_selector & ~7);
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300412 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000413 e2 |= DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300414 cpu_stl_kernel_ra(env, ptr + 4, e2, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000415 }
416
417 /* set the new CPU state */
418 /* from this point, any exception which occurs can give problems */
419 env->cr[0] |= CR0_TS_MASK;
420 env->hflags |= HF_TS_MASK;
421 env->tr.selector = tss_selector;
422 env->tr.base = tss_base;
423 env->tr.limit = tss_limit;
424 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
425
426 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
427 cpu_x86_update_cr3(env, new_cr3);
428 }
429
430 /* load all registers without an exception, then reload them with
431 possible exception */
432 env->eip = new_eip;
433 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
434 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +0000435 if (!(type & 8)) {
bellardeaa728e2008-05-28 12:51:20 +0000436 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000437 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000438 cpu_load_eflags(env, new_eflags, eflags_mask);
Blue Swirl20054ef2012-04-28 15:33:48 +0000439 /* XXX: what to do in 16 bit case? */
liguang4b34e3a2013-05-28 16:20:59 +0800440 env->regs[R_EAX] = new_regs[0];
liguanga4165612013-05-28 16:21:01 +0800441 env->regs[R_ECX] = new_regs[1];
liguang00f5e6f2013-05-28 16:21:02 +0800442 env->regs[R_EDX] = new_regs[2];
liguang70b51362013-05-28 16:21:00 +0800443 env->regs[R_EBX] = new_regs[3];
liguang08b3ded2013-05-28 16:21:04 +0800444 env->regs[R_ESP] = new_regs[4];
liguangc12dddd2013-05-28 16:21:03 +0800445 env->regs[R_EBP] = new_regs[5];
liguang78c3c6d2013-05-28 16:21:05 +0800446 env->regs[R_ESI] = new_regs[6];
liguangcf75c592013-05-28 16:21:06 +0800447 env->regs[R_EDI] = new_regs[7];
bellardeaa728e2008-05-28 12:51:20 +0000448 if (new_eflags & VM_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000449 for (i = 0; i < 6; i++) {
Blue Swirl2999a0b2012-04-29 19:47:06 +0000450 load_seg_vm(env, i, new_segs[i]);
Blue Swirl20054ef2012-04-28 15:33:48 +0000451 }
bellardeaa728e2008-05-28 12:51:20 +0000452 } else {
bellardeaa728e2008-05-28 12:51:20 +0000453 /* first just selectors as the rest may trigger exceptions */
Blue Swirl20054ef2012-04-28 15:33:48 +0000454 for (i = 0; i < 6; i++) {
bellardeaa728e2008-05-28 12:51:20 +0000455 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000456 }
bellardeaa728e2008-05-28 12:51:20 +0000457 }
458
459 env->ldt.selector = new_ldt & ~4;
460 env->ldt.base = 0;
461 env->ldt.limit = 0;
462 env->ldt.flags = 0;
463
464 /* load the LDT */
Blue Swirl20054ef2012-04-28 15:33:48 +0000465 if (new_ldt & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300466 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000467 }
bellardeaa728e2008-05-28 12:51:20 +0000468
469 if ((new_ldt & 0xfffc) != 0) {
470 dt = &env->gdt;
471 index = new_ldt & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +0000472 if ((index + 7) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300473 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000474 }
bellardeaa728e2008-05-28 12:51:20 +0000475 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300476 e1 = cpu_ldl_kernel_ra(env, ptr, retaddr);
477 e2 = cpu_ldl_kernel_ra(env, ptr + 4, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000478 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300479 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000480 }
481 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300482 raise_exception_err_ra(env, EXCP0A_TSS, new_ldt & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +0000483 }
bellardeaa728e2008-05-28 12:51:20 +0000484 load_seg_cache_raw_dt(&env->ldt, e1, e2);
485 }
486
487 /* load the segments */
488 if (!(new_eflags & VM_MASK)) {
Paolo Bonzinid3b54912014-05-15 18:19:17 +0200489 int cpl = new_segs[R_CS] & 3;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300490 tss_load_seg(env, R_CS, new_segs[R_CS], cpl, retaddr);
491 tss_load_seg(env, R_SS, new_segs[R_SS], cpl, retaddr);
492 tss_load_seg(env, R_ES, new_segs[R_ES], cpl, retaddr);
493 tss_load_seg(env, R_DS, new_segs[R_DS], cpl, retaddr);
494 tss_load_seg(env, R_FS, new_segs[R_FS], cpl, retaddr);
495 tss_load_seg(env, R_GS, new_segs[R_GS], cpl, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000496 }
497
liguanga78d0ea2013-05-28 16:21:07 +0800498 /* check that env->eip is in the CS segment limits */
bellardeaa728e2008-05-28 12:51:20 +0000499 if (new_eip > env->segs[R_CS].limit) {
Blue Swirl20054ef2012-04-28 15:33:48 +0000500 /* XXX: different exception if CALL? */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300501 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
bellardeaa728e2008-05-28 12:51:20 +0000502 }
aliguori01df0402008-11-18 21:08:15 +0000503
504#ifndef CONFIG_USER_ONLY
505 /* reset local breakpoints */
liguang428065c2013-01-15 13:39:55 +0800506 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
Richard Henderson93d00d02015-09-15 11:45:08 -0700507 cpu_x86_update_dr7(env, env->dr[7] & ~DR7_LOCAL_BP_MASK);
aliguori01df0402008-11-18 21:08:15 +0000508 }
509#endif
bellardeaa728e2008-05-28 12:51:20 +0000510}
511
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300512static void switch_tss(CPUX86State *env, int tss_selector,
513 uint32_t e1, uint32_t e2, int source,
514 uint32_t next_eip)
515{
516 switch_tss_ra(env, tss_selector, e1, e2, source, next_eip, 0);
517}
518
bellardeaa728e2008-05-28 12:51:20 +0000519static inline unsigned int get_sp_mask(unsigned int e2)
520{
Blue Swirl20054ef2012-04-28 15:33:48 +0000521 if (e2 & DESC_B_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000522 return 0xffffffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000523 } else {
bellardeaa728e2008-05-28 12:51:20 +0000524 return 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000525 }
bellardeaa728e2008-05-28 12:51:20 +0000526}
527
Blue Swirl20054ef2012-04-28 15:33:48 +0000528static int exception_has_error_code(int intno)
aliguori2ed51f52009-04-22 20:20:07 +0000529{
Blue Swirl20054ef2012-04-28 15:33:48 +0000530 switch (intno) {
531 case 8:
532 case 10:
533 case 11:
534 case 12:
535 case 13:
536 case 14:
537 case 17:
538 return 1;
539 }
540 return 0;
aliguori2ed51f52009-04-22 20:20:07 +0000541}
542
bellardeaa728e2008-05-28 12:51:20 +0000543#ifdef TARGET_X86_64
liguang08b3ded2013-05-28 16:21:04 +0800544#define SET_ESP(val, sp_mask) \
545 do { \
546 if ((sp_mask) == 0xffff) { \
547 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
548 ((val) & 0xffff); \
549 } else if ((sp_mask) == 0xffffffffLL) { \
550 env->regs[R_ESP] = (uint32_t)(val); \
551 } else { \
552 env->regs[R_ESP] = (val); \
553 } \
Blue Swirl20054ef2012-04-28 15:33:48 +0000554 } while (0)
bellardeaa728e2008-05-28 12:51:20 +0000555#else
liguang08b3ded2013-05-28 16:21:04 +0800556#define SET_ESP(val, sp_mask) \
557 do { \
558 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
559 ((val) & (sp_mask)); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000560 } while (0)
bellardeaa728e2008-05-28 12:51:20 +0000561#endif
562
aliguoric0a04f02008-09-09 14:49:02 +0000563/* in 64-bit machines, this can overflow. So this segment addition macro
564 * can be used to trim the value to 32-bit whenever needed */
565#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
566
bellardeaa728e2008-05-28 12:51:20 +0000567/* XXX: add a is_user flag to have proper security support */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300568#define PUSHW_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000569 { \
570 sp -= 2; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300571 cpu_stw_kernel_ra(env, (ssp) + (sp & (sp_mask)), (val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000572 }
bellardeaa728e2008-05-28 12:51:20 +0000573
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300574#define PUSHL_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000575 { \
576 sp -= 4; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300577 cpu_stl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000578 }
bellardeaa728e2008-05-28 12:51:20 +0000579
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300580#define POPW_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000581 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300582 val = cpu_lduw_kernel_ra(env, (ssp) + (sp & (sp_mask)), ra); \
Blue Swirl329e6072012-04-29 19:11:01 +0000583 sp += 2; \
Blue Swirl20054ef2012-04-28 15:33:48 +0000584 }
bellardeaa728e2008-05-28 12:51:20 +0000585
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300586#define POPL_RA(ssp, sp, sp_mask, val, ra) \
Blue Swirl329e6072012-04-29 19:11:01 +0000587 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300588 val = (uint32_t)cpu_ldl_kernel_ra(env, SEG_ADDL(ssp, sp, sp_mask), ra); \
Blue Swirl329e6072012-04-29 19:11:01 +0000589 sp += 4; \
Blue Swirl20054ef2012-04-28 15:33:48 +0000590 }
bellardeaa728e2008-05-28 12:51:20 +0000591
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300592#define PUSHW(ssp, sp, sp_mask, val) PUSHW_RA(ssp, sp, sp_mask, val, 0)
593#define PUSHL(ssp, sp, sp_mask, val) PUSHL_RA(ssp, sp, sp_mask, val, 0)
594#define POPW(ssp, sp, sp_mask, val) POPW_RA(ssp, sp, sp_mask, val, 0)
595#define POPL(ssp, sp, sp_mask, val) POPL_RA(ssp, sp, sp_mask, val, 0)
596
bellardeaa728e2008-05-28 12:51:20 +0000597/* protected mode interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000598static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
599 int error_code, unsigned int next_eip,
600 int is_hw)
bellardeaa728e2008-05-28 12:51:20 +0000601{
602 SegmentCache *dt;
603 target_ulong ptr, ssp;
604 int type, dpl, selector, ss_dpl, cpl;
605 int has_error_code, new_stack, shift;
blueswir11c918eb2009-01-14 19:27:02 +0000606 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
bellardeaa728e2008-05-28 12:51:20 +0000607 uint32_t old_eip, sp_mask;
Kevin O'Connor87446322014-05-20 17:10:24 -0400608 int vm86 = env->eflags & VM_MASK;
bellardeaa728e2008-05-28 12:51:20 +0000609
bellardeaa728e2008-05-28 12:51:20 +0000610 has_error_code = 0;
Blue Swirl20054ef2012-04-28 15:33:48 +0000611 if (!is_int && !is_hw) {
612 has_error_code = exception_has_error_code(intno);
613 }
614 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +0000615 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000616 } else {
bellardeaa728e2008-05-28 12:51:20 +0000617 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000618 }
bellardeaa728e2008-05-28 12:51:20 +0000619
620 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +0000621 if (intno * 8 + 7 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000622 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000623 }
bellardeaa728e2008-05-28 12:51:20 +0000624 ptr = dt->base + intno * 8;
Blue Swirl329e6072012-04-29 19:11:01 +0000625 e1 = cpu_ldl_kernel(env, ptr);
626 e2 = cpu_ldl_kernel(env, ptr + 4);
bellardeaa728e2008-05-28 12:51:20 +0000627 /* check gate type */
628 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +0000629 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +0000630 case 5: /* task gate */
631 /* must do that check here to return the correct error code */
Blue Swirl20054ef2012-04-28 15:33:48 +0000632 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000633 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000634 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000635 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
bellardeaa728e2008-05-28 12:51:20 +0000636 if (has_error_code) {
637 int type;
638 uint32_t mask;
Blue Swirl20054ef2012-04-28 15:33:48 +0000639
bellardeaa728e2008-05-28 12:51:20 +0000640 /* push the error code */
641 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
642 shift = type >> 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000643 if (env->segs[R_SS].flags & DESC_B_MASK) {
bellardeaa728e2008-05-28 12:51:20 +0000644 mask = 0xffffffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000645 } else {
bellardeaa728e2008-05-28 12:51:20 +0000646 mask = 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +0000647 }
liguang08b3ded2013-05-28 16:21:04 +0800648 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
bellardeaa728e2008-05-28 12:51:20 +0000649 ssp = env->segs[R_SS].base + esp;
Blue Swirl20054ef2012-04-28 15:33:48 +0000650 if (shift) {
Blue Swirl329e6072012-04-29 19:11:01 +0000651 cpu_stl_kernel(env, ssp, error_code);
Blue Swirl20054ef2012-04-28 15:33:48 +0000652 } else {
Blue Swirl329e6072012-04-29 19:11:01 +0000653 cpu_stw_kernel(env, ssp, error_code);
Blue Swirl20054ef2012-04-28 15:33:48 +0000654 }
bellardeaa728e2008-05-28 12:51:20 +0000655 SET_ESP(esp, mask);
656 }
657 return;
658 case 6: /* 286 interrupt gate */
659 case 7: /* 286 trap gate */
660 case 14: /* 386 interrupt gate */
661 case 15: /* 386 trap gate */
662 break;
663 default:
Blue Swirl77b2bc22012-04-28 19:35:10 +0000664 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
bellardeaa728e2008-05-28 12:51:20 +0000665 break;
666 }
667 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
668 cpl = env->hflags & HF_CPL_MASK;
ths1235fc02008-06-03 19:51:57 +0000669 /* check privilege if software int */
Blue Swirl20054ef2012-04-28 15:33:48 +0000670 if (is_int && dpl < cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000671 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000672 }
bellardeaa728e2008-05-28 12:51:20 +0000673 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +0000674 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000675 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000676 }
bellardeaa728e2008-05-28 12:51:20 +0000677 selector = e1 >> 16;
678 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
Blue Swirl20054ef2012-04-28 15:33:48 +0000679 if ((selector & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000680 raise_exception_err(env, EXCP0D_GPF, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000681 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000682 if (load_segment(env, &e1, &e2, selector) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000683 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000684 }
685 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000686 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000687 }
bellardeaa728e2008-05-28 12:51:20 +0000688 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000689 if (dpl > cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000690 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000691 }
692 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000693 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000694 }
bellardeaa728e2008-05-28 12:51:20 +0000695 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
696 /* to inner privilege */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300697 get_ss_esp_from_tss(env, &ss, &esp, dpl, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000698 if ((ss & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000699 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000700 }
701 if ((ss & 3) != dpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000702 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000703 }
Blue Swirl2999a0b2012-04-29 19:47:06 +0000704 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000705 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000706 }
bellardeaa728e2008-05-28 12:51:20 +0000707 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000708 if (ss_dpl != dpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000709 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000710 }
bellardeaa728e2008-05-28 12:51:20 +0000711 if (!(ss_e2 & DESC_S_MASK) ||
712 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +0000713 !(ss_e2 & DESC_W_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000714 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000715 }
716 if (!(ss_e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000717 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000718 }
bellardeaa728e2008-05-28 12:51:20 +0000719 new_stack = 1;
720 sp_mask = get_sp_mask(ss_e2);
721 ssp = get_seg_base(ss_e1, ss_e2);
722 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
723 /* to same privilege */
Kevin O'Connor87446322014-05-20 17:10:24 -0400724 if (vm86) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000725 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000726 }
bellardeaa728e2008-05-28 12:51:20 +0000727 new_stack = 0;
728 sp_mask = get_sp_mask(env->segs[R_SS].flags);
729 ssp = env->segs[R_SS].base;
liguang08b3ded2013-05-28 16:21:04 +0800730 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +0000731 dpl = cpl;
732 } else {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000733 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
bellardeaa728e2008-05-28 12:51:20 +0000734 new_stack = 0; /* avoid warning */
735 sp_mask = 0; /* avoid warning */
736 ssp = 0; /* avoid warning */
737 esp = 0; /* avoid warning */
738 }
739
740 shift = type >> 3;
741
742#if 0
743 /* XXX: check that enough room is available */
744 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
Kevin O'Connor87446322014-05-20 17:10:24 -0400745 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000746 push_size += 8;
Blue Swirl20054ef2012-04-28 15:33:48 +0000747 }
bellardeaa728e2008-05-28 12:51:20 +0000748 push_size <<= shift;
749#endif
750 if (shift == 1) {
751 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400752 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000753 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
754 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
755 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
756 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
757 }
758 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800759 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +0000760 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000761 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000762 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
763 PUSHL(ssp, esp, sp_mask, old_eip);
764 if (has_error_code) {
765 PUSHL(ssp, esp, sp_mask, error_code);
766 }
767 } else {
768 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400769 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000770 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
771 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
772 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
773 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
774 }
775 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800776 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +0000777 }
Blue Swirl997ff0d2012-04-29 15:01:21 +0000778 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000779 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
780 PUSHW(ssp, esp, sp_mask, old_eip);
781 if (has_error_code) {
782 PUSHW(ssp, esp, sp_mask, error_code);
783 }
784 }
785
Kevin O'Connorfd460602014-04-29 16:38:31 -0400786 /* interrupt gate clear IF mask */
787 if ((type & 1) == 0) {
788 env->eflags &= ~IF_MASK;
789 }
790 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
791
bellardeaa728e2008-05-28 12:51:20 +0000792 if (new_stack) {
Kevin O'Connor87446322014-05-20 17:10:24 -0400793 if (vm86) {
bellardeaa728e2008-05-28 12:51:20 +0000794 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
795 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
796 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
797 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
798 }
799 ss = (ss & ~3) | dpl;
800 cpu_x86_load_seg_cache(env, R_SS, ss,
801 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
802 }
803 SET_ESP(esp, sp_mask);
804
805 selector = (selector & ~3) | dpl;
806 cpu_x86_load_seg_cache(env, R_CS, selector,
807 get_seg_base(e1, e2),
808 get_seg_limit(e1, e2),
809 e2);
bellardeaa728e2008-05-28 12:51:20 +0000810 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +0000811}
812
813#ifdef TARGET_X86_64
814
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300815#define PUSHQ_RA(sp, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000816 { \
817 sp -= 8; \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300818 cpu_stq_kernel_ra(env, sp, (val), ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000819 }
bellardeaa728e2008-05-28 12:51:20 +0000820
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300821#define POPQ_RA(sp, val, ra) \
Blue Swirl20054ef2012-04-28 15:33:48 +0000822 { \
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300823 val = cpu_ldq_kernel_ra(env, sp, ra); \
Blue Swirl20054ef2012-04-28 15:33:48 +0000824 sp += 8; \
825 }
bellardeaa728e2008-05-28 12:51:20 +0000826
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300827#define PUSHQ(sp, val) PUSHQ_RA(sp, val, 0)
828#define POPQ(sp, val) POPQ_RA(sp, val, 0)
829
Blue Swirl2999a0b2012-04-29 19:47:06 +0000830static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
bellardeaa728e2008-05-28 12:51:20 +0000831{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200832 X86CPU *cpu = x86_env_get_cpu(env);
bellardeaa728e2008-05-28 12:51:20 +0000833 int index;
834
835#if 0
836 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
837 env->tr.base, env->tr.limit);
838#endif
839
Blue Swirl20054ef2012-04-28 15:33:48 +0000840 if (!(env->tr.flags & DESC_P_MASK)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200841 cpu_abort(CPU(cpu), "invalid tss");
Blue Swirl20054ef2012-04-28 15:33:48 +0000842 }
bellardeaa728e2008-05-28 12:51:20 +0000843 index = 8 * level + 4;
Blue Swirl20054ef2012-04-28 15:33:48 +0000844 if ((index + 7) > env->tr.limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000845 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000846 }
Blue Swirl329e6072012-04-29 19:11:01 +0000847 return cpu_ldq_kernel(env, env->tr.base + index);
bellardeaa728e2008-05-28 12:51:20 +0000848}
849
850/* 64 bit interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +0000851static void do_interrupt64(CPUX86State *env, int intno, int is_int,
852 int error_code, target_ulong next_eip, int is_hw)
bellardeaa728e2008-05-28 12:51:20 +0000853{
854 SegmentCache *dt;
855 target_ulong ptr;
856 int type, dpl, selector, cpl, ist;
857 int has_error_code, new_stack;
858 uint32_t e1, e2, e3, ss;
859 target_ulong old_eip, esp, offset;
bellardeaa728e2008-05-28 12:51:20 +0000860
bellardeaa728e2008-05-28 12:51:20 +0000861 has_error_code = 0;
Blue Swirl20054ef2012-04-28 15:33:48 +0000862 if (!is_int && !is_hw) {
863 has_error_code = exception_has_error_code(intno);
864 }
865 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +0000866 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000867 } else {
bellardeaa728e2008-05-28 12:51:20 +0000868 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +0000869 }
bellardeaa728e2008-05-28 12:51:20 +0000870
871 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +0000872 if (intno * 16 + 15 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000873 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000874 }
bellardeaa728e2008-05-28 12:51:20 +0000875 ptr = dt->base + intno * 16;
Blue Swirl329e6072012-04-29 19:11:01 +0000876 e1 = cpu_ldl_kernel(env, ptr);
877 e2 = cpu_ldl_kernel(env, ptr + 4);
878 e3 = cpu_ldl_kernel(env, ptr + 8);
bellardeaa728e2008-05-28 12:51:20 +0000879 /* check gate type */
880 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +0000881 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +0000882 case 14: /* 386 interrupt gate */
883 case 15: /* 386 trap gate */
884 break;
885 default:
Blue Swirl77b2bc22012-04-28 19:35:10 +0000886 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
bellardeaa728e2008-05-28 12:51:20 +0000887 break;
888 }
889 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
890 cpl = env->hflags & HF_CPL_MASK;
ths1235fc02008-06-03 19:51:57 +0000891 /* check privilege if software int */
Blue Swirl20054ef2012-04-28 15:33:48 +0000892 if (is_int && dpl < cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000893 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000894 }
bellardeaa728e2008-05-28 12:51:20 +0000895 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +0000896 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000897 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +0000898 }
bellardeaa728e2008-05-28 12:51:20 +0000899 selector = e1 >> 16;
900 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
901 ist = e2 & 7;
Blue Swirl20054ef2012-04-28 15:33:48 +0000902 if ((selector & 0xfffc) == 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000903 raise_exception_err(env, EXCP0D_GPF, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +0000904 }
bellardeaa728e2008-05-28 12:51:20 +0000905
Blue Swirl2999a0b2012-04-29 19:47:06 +0000906 if (load_segment(env, &e1, &e2, selector) != 0) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000907 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000908 }
909 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000910 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000911 }
bellardeaa728e2008-05-28 12:51:20 +0000912 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +0000913 if (dpl > cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000914 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000915 }
916 if (!(e2 & DESC_P_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000917 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000918 }
919 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000920 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000921 }
bellardeaa728e2008-05-28 12:51:20 +0000922 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
923 /* to inner privilege */
bellardeaa728e2008-05-28 12:51:20 +0000924 new_stack = 1;
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100925 esp = get_rsp_from_tss(env, ist != 0 ? ist + 3 : dpl);
926 ss = 0;
bellardeaa728e2008-05-28 12:51:20 +0000927 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
928 /* to same privilege */
Blue Swirl20054ef2012-04-28 15:33:48 +0000929 if (env->eflags & VM_MASK) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000930 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
Blue Swirl20054ef2012-04-28 15:33:48 +0000931 }
bellardeaa728e2008-05-28 12:51:20 +0000932 new_stack = 0;
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100933 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +0000934 dpl = cpl;
935 } else {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000936 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
bellardeaa728e2008-05-28 12:51:20 +0000937 new_stack = 0; /* avoid warning */
938 esp = 0; /* avoid warning */
939 }
Paolo Bonziniae67dc72014-11-12 12:04:56 +0100940 esp &= ~0xfLL; /* align stack */
bellardeaa728e2008-05-28 12:51:20 +0000941
942 PUSHQ(esp, env->segs[R_SS].selector);
liguang08b3ded2013-05-28 16:21:04 +0800943 PUSHQ(esp, env->regs[R_ESP]);
Blue Swirl997ff0d2012-04-29 15:01:21 +0000944 PUSHQ(esp, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +0000945 PUSHQ(esp, env->segs[R_CS].selector);
946 PUSHQ(esp, old_eip);
947 if (has_error_code) {
948 PUSHQ(esp, error_code);
949 }
950
Kevin O'Connorfd460602014-04-29 16:38:31 -0400951 /* interrupt gate clear IF mask */
952 if ((type & 1) == 0) {
953 env->eflags &= ~IF_MASK;
954 }
955 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
956
bellardeaa728e2008-05-28 12:51:20 +0000957 if (new_stack) {
958 ss = 0 | dpl;
959 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
960 }
liguang08b3ded2013-05-28 16:21:04 +0800961 env->regs[R_ESP] = esp;
bellardeaa728e2008-05-28 12:51:20 +0000962
963 selector = (selector & ~3) | dpl;
964 cpu_x86_load_seg_cache(env, R_CS, selector,
965 get_seg_base(e1, e2),
966 get_seg_limit(e1, e2),
967 e2);
bellardeaa728e2008-05-28 12:51:20 +0000968 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +0000969}
970#endif
971
blueswir1d9957a82008-12-13 11:49:17 +0000972#ifdef TARGET_X86_64
bellardeaa728e2008-05-28 12:51:20 +0000973#if defined(CONFIG_USER_ONLY)
Blue Swirl2999a0b2012-04-29 19:47:06 +0000974void helper_syscall(CPUX86State *env, int next_eip_addend)
bellardeaa728e2008-05-28 12:51:20 +0000975{
Andreas Färber27103422013-08-26 08:31:06 +0200976 CPUState *cs = CPU(x86_env_get_cpu(env));
977
978 cs->exception_index = EXCP_SYSCALL;
bellardeaa728e2008-05-28 12:51:20 +0000979 env->exception_next_eip = env->eip + next_eip_addend;
Andreas Färber5638d182013-08-27 17:52:12 +0200980 cpu_loop_exit(cs);
bellardeaa728e2008-05-28 12:51:20 +0000981}
982#else
Blue Swirl2999a0b2012-04-29 19:47:06 +0000983void helper_syscall(CPUX86State *env, int next_eip_addend)
bellardeaa728e2008-05-28 12:51:20 +0000984{
985 int selector;
986
987 if (!(env->efer & MSR_EFER_SCE)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +0300988 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +0000989 }
990 selector = (env->star >> 32) & 0xffff;
bellardeaa728e2008-05-28 12:51:20 +0000991 if (env->hflags & HF_LMA_MASK) {
992 int code64;
993
liguanga4165612013-05-28 16:21:01 +0800994 env->regs[R_ECX] = env->eip + next_eip_addend;
Blue Swirl997ff0d2012-04-29 15:01:21 +0000995 env->regs[11] = cpu_compute_eflags(env);
bellardeaa728e2008-05-28 12:51:20 +0000996
997 code64 = env->hflags & HF_CS64_MASK;
998
Kevin O'Connorfd460602014-04-29 16:38:31 -0400999 env->eflags &= ~env->fmask;
1000 cpu_load_eflags(env, env->eflags, 0);
bellardeaa728e2008-05-28 12:51:20 +00001001 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1002 0, 0xffffffff,
1003 DESC_G_MASK | DESC_P_MASK |
1004 DESC_S_MASK |
Blue Swirl20054ef2012-04-28 15:33:48 +00001005 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1006 DESC_L_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001007 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1008 0, 0xffffffff,
1009 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1010 DESC_S_MASK |
1011 DESC_W_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00001012 if (code64) {
bellardeaa728e2008-05-28 12:51:20 +00001013 env->eip = env->lstar;
Blue Swirl20054ef2012-04-28 15:33:48 +00001014 } else {
bellardeaa728e2008-05-28 12:51:20 +00001015 env->eip = env->cstar;
Blue Swirl20054ef2012-04-28 15:33:48 +00001016 }
blueswir1d9957a82008-12-13 11:49:17 +00001017 } else {
liguanga4165612013-05-28 16:21:01 +08001018 env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
bellardeaa728e2008-05-28 12:51:20 +00001019
Kevin O'Connorfd460602014-04-29 16:38:31 -04001020 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001021 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1022 0, 0xffffffff,
1023 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1024 DESC_S_MASK |
1025 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1026 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1027 0, 0xffffffff,
1028 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1029 DESC_S_MASK |
1030 DESC_W_MASK | DESC_A_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001031 env->eip = (uint32_t)env->star;
1032 }
1033}
1034#endif
blueswir1d9957a82008-12-13 11:49:17 +00001035#endif
bellardeaa728e2008-05-28 12:51:20 +00001036
blueswir1d9957a82008-12-13 11:49:17 +00001037#ifdef TARGET_X86_64
Blue Swirl2999a0b2012-04-29 19:47:06 +00001038void helper_sysret(CPUX86State *env, int dflag)
bellardeaa728e2008-05-28 12:51:20 +00001039{
1040 int cpl, selector;
1041
1042 if (!(env->efer & MSR_EFER_SCE)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001043 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001044 }
1045 cpl = env->hflags & HF_CPL_MASK;
1046 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001047 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001048 }
1049 selector = (env->star >> 48) & 0xffff;
bellardeaa728e2008-05-28 12:51:20 +00001050 if (env->hflags & HF_LMA_MASK) {
Kevin O'Connorfd460602014-04-29 16:38:31 -04001051 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1052 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1053 NT_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001054 if (dflag == 2) {
1055 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1056 0, 0xffffffff,
1057 DESC_G_MASK | DESC_P_MASK |
1058 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1059 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1060 DESC_L_MASK);
liguanga4165612013-05-28 16:21:01 +08001061 env->eip = env->regs[R_ECX];
bellardeaa728e2008-05-28 12:51:20 +00001062 } else {
1063 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1064 0, 0xffffffff,
1065 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1066 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1067 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
liguanga4165612013-05-28 16:21:01 +08001068 env->eip = (uint32_t)env->regs[R_ECX];
bellardeaa728e2008-05-28 12:51:20 +00001069 }
Bill Paulac576222015-03-09 15:48:01 -07001070 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
bellardeaa728e2008-05-28 12:51:20 +00001071 0, 0xffffffff,
1072 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1073 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1074 DESC_W_MASK | DESC_A_MASK);
blueswir1d9957a82008-12-13 11:49:17 +00001075 } else {
Kevin O'Connorfd460602014-04-29 16:38:31 -04001076 env->eflags |= IF_MASK;
bellardeaa728e2008-05-28 12:51:20 +00001077 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1078 0, 0xffffffff,
1079 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1080 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1081 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
liguanga4165612013-05-28 16:21:01 +08001082 env->eip = (uint32_t)env->regs[R_ECX];
Bill Paulac576222015-03-09 15:48:01 -07001083 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) | 3,
bellardeaa728e2008-05-28 12:51:20 +00001084 0, 0xffffffff,
1085 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1086 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1087 DESC_W_MASK | DESC_A_MASK);
bellardeaa728e2008-05-28 12:51:20 +00001088 }
bellardeaa728e2008-05-28 12:51:20 +00001089}
blueswir1d9957a82008-12-13 11:49:17 +00001090#endif
bellardeaa728e2008-05-28 12:51:20 +00001091
1092/* real mode interrupt */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001093static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1094 int error_code, unsigned int next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001095{
1096 SegmentCache *dt;
1097 target_ulong ptr, ssp;
1098 int selector;
1099 uint32_t offset, esp;
1100 uint32_t old_cs, old_eip;
bellardeaa728e2008-05-28 12:51:20 +00001101
Blue Swirl20054ef2012-04-28 15:33:48 +00001102 /* real mode (simpler!) */
bellardeaa728e2008-05-28 12:51:20 +00001103 dt = &env->idt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001104 if (intno * 4 + 3 > dt->limit) {
Blue Swirl77b2bc22012-04-28 19:35:10 +00001105 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001106 }
bellardeaa728e2008-05-28 12:51:20 +00001107 ptr = dt->base + intno * 4;
Blue Swirl329e6072012-04-29 19:11:01 +00001108 offset = cpu_lduw_kernel(env, ptr);
1109 selector = cpu_lduw_kernel(env, ptr + 2);
liguang08b3ded2013-05-28 16:21:04 +08001110 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001111 ssp = env->segs[R_SS].base;
Blue Swirl20054ef2012-04-28 15:33:48 +00001112 if (is_int) {
bellardeaa728e2008-05-28 12:51:20 +00001113 old_eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001114 } else {
bellardeaa728e2008-05-28 12:51:20 +00001115 old_eip = env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001116 }
bellardeaa728e2008-05-28 12:51:20 +00001117 old_cs = env->segs[R_CS].selector;
Blue Swirl20054ef2012-04-28 15:33:48 +00001118 /* XXX: use SS segment size? */
Blue Swirl997ff0d2012-04-29 15:01:21 +00001119 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
bellardeaa728e2008-05-28 12:51:20 +00001120 PUSHW(ssp, esp, 0xffff, old_cs);
1121 PUSHW(ssp, esp, 0xffff, old_eip);
1122
1123 /* update processor state */
liguang08b3ded2013-05-28 16:21:04 +08001124 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
bellardeaa728e2008-05-28 12:51:20 +00001125 env->eip = offset;
1126 env->segs[R_CS].selector = selector;
1127 env->segs[R_CS].base = (selector << 4);
1128 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1129}
1130
Blue Swirle694d4e2011-05-16 19:38:48 +00001131#if defined(CONFIG_USER_ONLY)
Peter Maydell33271822016-05-17 15:18:06 +01001132/* fake user mode interrupt. is_int is TRUE if coming from the int
1133 * instruction. next_eip is the env->eip value AFTER the interrupt
1134 * instruction. It is only relevant if is_int is TRUE or if intno
1135 * is EXCP_SYSCALL.
1136 */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001137static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1138 int error_code, target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001139{
1140 SegmentCache *dt;
1141 target_ulong ptr;
1142 int dpl, cpl, shift;
1143 uint32_t e2;
1144
1145 dt = &env->idt;
1146 if (env->hflags & HF_LMA_MASK) {
1147 shift = 4;
1148 } else {
1149 shift = 3;
1150 }
1151 ptr = dt->base + (intno << shift);
Blue Swirl329e6072012-04-29 19:11:01 +00001152 e2 = cpu_ldl_kernel(env, ptr + 4);
bellardeaa728e2008-05-28 12:51:20 +00001153
1154 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1155 cpl = env->hflags & HF_CPL_MASK;
ths1235fc02008-06-03 19:51:57 +00001156 /* check privilege if software int */
Blue Swirl20054ef2012-04-28 15:33:48 +00001157 if (is_int && dpl < cpl) {
Blue Swirl77b2bc22012-04-28 19:35:10 +00001158 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001159 }
bellardeaa728e2008-05-28 12:51:20 +00001160
1161 /* Since we emulate only user space, we cannot do more than
1162 exiting the emulation with the suitable exception and error
Jincheng Miao47575992014-08-08 11:56:54 +08001163 code. So update EIP for INT 0x80 and EXCP_SYSCALL. */
1164 if (is_int || intno == EXCP_SYSCALL) {
liguanga78d0ea2013-05-28 16:21:07 +08001165 env->eip = next_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001166 }
bellardeaa728e2008-05-28 12:51:20 +00001167}
1168
Blue Swirle694d4e2011-05-16 19:38:48 +00001169#else
1170
Blue Swirl2999a0b2012-04-29 19:47:06 +00001171static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1172 int error_code, int is_hw, int rm)
aliguori2ed51f52009-04-22 20:20:07 +00001173{
Andreas Färber19d6ca12014-03-09 19:15:27 +01001174 CPUState *cs = CPU(x86_env_get_cpu(env));
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001175 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
Blue Swirl20054ef2012-04-28 15:33:48 +00001176 control.event_inj));
1177
aliguori2ed51f52009-04-22 20:20:07 +00001178 if (!(event_inj & SVM_EVTINJ_VALID)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001179 int type;
1180
1181 if (is_int) {
1182 type = SVM_EVTINJ_TYPE_SOFT;
1183 } else {
1184 type = SVM_EVTINJ_TYPE_EXEPT;
1185 }
1186 event_inj = intno | type | SVM_EVTINJ_VALID;
1187 if (!rm && exception_has_error_code(intno)) {
1188 event_inj |= SVM_EVTINJ_VALID_ERR;
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001189 x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
Blue Swirl20054ef2012-04-28 15:33:48 +00001190 control.event_inj_err),
1191 error_code);
1192 }
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001193 x86_stl_phys(cs,
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +10001194 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
Blue Swirl20054ef2012-04-28 15:33:48 +00001195 event_inj);
aliguori2ed51f52009-04-22 20:20:07 +00001196 }
1197}
aliguori00ea18d2009-04-23 13:16:56 +00001198#endif
aliguori2ed51f52009-04-22 20:20:07 +00001199
bellardeaa728e2008-05-28 12:51:20 +00001200/*
1201 * Begin execution of an interruption. is_int is TRUE if coming from
liguanga78d0ea2013-05-28 16:21:07 +08001202 * the int instruction. next_eip is the env->eip value AFTER the interrupt
bellardeaa728e2008-05-28 12:51:20 +00001203 * instruction. It is only relevant if is_int is TRUE.
1204 */
Andreas Färberca4c8102013-07-03 02:00:09 +02001205static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
Blue Swirl2999a0b2012-04-29 19:47:06 +00001206 int error_code, target_ulong next_eip, int is_hw)
bellardeaa728e2008-05-28 12:51:20 +00001207{
Andreas Färberca4c8102013-07-03 02:00:09 +02001208 CPUX86State *env = &cpu->env;
1209
aliguori8fec2b82009-01-15 22:36:53 +00001210 if (qemu_loglevel_mask(CPU_LOG_INT)) {
bellardeaa728e2008-05-28 12:51:20 +00001211 if ((env->cr[0] & CR0_PE_MASK)) {
1212 static int count;
Blue Swirl20054ef2012-04-28 15:33:48 +00001213
1214 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1215 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1216 count, intno, error_code, is_int,
1217 env->hflags & HF_CPL_MASK,
liguanga78d0ea2013-05-28 16:21:07 +08001218 env->segs[R_CS].selector, env->eip,
1219 (int)env->segs[R_CS].base + env->eip,
liguang08b3ded2013-05-28 16:21:04 +08001220 env->segs[R_SS].selector, env->regs[R_ESP]);
bellardeaa728e2008-05-28 12:51:20 +00001221 if (intno == 0x0e) {
aliguori93fcfe32009-01-15 22:34:14 +00001222 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
bellardeaa728e2008-05-28 12:51:20 +00001223 } else {
liguang4b34e3a2013-05-28 16:20:59 +08001224 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
bellardeaa728e2008-05-28 12:51:20 +00001225 }
aliguori93fcfe32009-01-15 22:34:14 +00001226 qemu_log("\n");
Andreas Färbera0762852013-06-16 07:28:50 +02001227 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP);
bellardeaa728e2008-05-28 12:51:20 +00001228#if 0
1229 {
1230 int i;
Adam Lackorzynski9bd54942010-04-01 23:46:20 +02001231 target_ulong ptr;
Blue Swirl20054ef2012-04-28 15:33:48 +00001232
aliguori93fcfe32009-01-15 22:34:14 +00001233 qemu_log(" code=");
bellardeaa728e2008-05-28 12:51:20 +00001234 ptr = env->segs[R_CS].base + env->eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001235 for (i = 0; i < 16; i++) {
aliguori93fcfe32009-01-15 22:34:14 +00001236 qemu_log(" %02x", ldub(ptr + i));
bellardeaa728e2008-05-28 12:51:20 +00001237 }
aliguori93fcfe32009-01-15 22:34:14 +00001238 qemu_log("\n");
bellardeaa728e2008-05-28 12:51:20 +00001239 }
1240#endif
1241 count++;
1242 }
1243 }
1244 if (env->cr[0] & CR0_PE_MASK) {
aliguori00ea18d2009-04-23 13:16:56 +00001245#if !defined(CONFIG_USER_ONLY)
Blue Swirl20054ef2012-04-28 15:33:48 +00001246 if (env->hflags & HF_SVMI_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001247 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
Blue Swirl20054ef2012-04-28 15:33:48 +00001248 }
aliguori00ea18d2009-04-23 13:16:56 +00001249#endif
blueswir1eb38c522008-09-06 17:47:39 +00001250#ifdef TARGET_X86_64
bellardeaa728e2008-05-28 12:51:20 +00001251 if (env->hflags & HF_LMA_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001252 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
bellardeaa728e2008-05-28 12:51:20 +00001253 } else
1254#endif
1255 {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001256 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1257 is_hw);
bellardeaa728e2008-05-28 12:51:20 +00001258 }
1259 } else {
aliguori00ea18d2009-04-23 13:16:56 +00001260#if !defined(CONFIG_USER_ONLY)
Blue Swirl20054ef2012-04-28 15:33:48 +00001261 if (env->hflags & HF_SVMI_MASK) {
Blue Swirl2999a0b2012-04-29 19:47:06 +00001262 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
Blue Swirl20054ef2012-04-28 15:33:48 +00001263 }
aliguori00ea18d2009-04-23 13:16:56 +00001264#endif
Blue Swirl2999a0b2012-04-29 19:47:06 +00001265 do_interrupt_real(env, intno, is_int, error_code, next_eip);
bellardeaa728e2008-05-28 12:51:20 +00001266 }
aliguori2ed51f52009-04-22 20:20:07 +00001267
aliguori00ea18d2009-04-23 13:16:56 +00001268#if !defined(CONFIG_USER_ONLY)
aliguori2ed51f52009-04-22 20:20:07 +00001269 if (env->hflags & HF_SVMI_MASK) {
Edgar E. Iglesiasfdfba1a2013-11-15 14:46:38 +01001270 CPUState *cs = CPU(cpu);
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001271 uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb +
Blue Swirl20054ef2012-04-28 15:33:48 +00001272 offsetof(struct vmcb,
1273 control.event_inj));
1274
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001275 x86_stl_phys(cs,
Edgar E. Iglesiasab1da852013-12-17 15:07:29 +10001276 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
Blue Swirl20054ef2012-04-28 15:33:48 +00001277 event_inj & ~SVM_EVTINJ_VALID);
aliguori2ed51f52009-04-22 20:20:07 +00001278 }
aliguori00ea18d2009-04-23 13:16:56 +00001279#endif
bellardeaa728e2008-05-28 12:51:20 +00001280}
1281
Andreas Färber97a8ea52013-02-02 10:57:51 +01001282void x86_cpu_do_interrupt(CPUState *cs)
Blue Swirle694d4e2011-05-16 19:38:48 +00001283{
Andreas Färber97a8ea52013-02-02 10:57:51 +01001284 X86CPU *cpu = X86_CPU(cs);
1285 CPUX86State *env = &cpu->env;
1286
Blue Swirle694d4e2011-05-16 19:38:48 +00001287#if defined(CONFIG_USER_ONLY)
1288 /* if user mode only, we simulate a fake exception
1289 which will be handled outside the cpu execution
1290 loop */
Andreas Färber27103422013-08-26 08:31:06 +02001291 do_interrupt_user(env, cs->exception_index,
Blue Swirle694d4e2011-05-16 19:38:48 +00001292 env->exception_is_int,
1293 env->error_code,
1294 env->exception_next_eip);
1295 /* successfully delivered */
1296 env->old_exception = -1;
1297#else
1298 /* simulate a real cpu exception. On i386, it can
1299 trigger new exceptions, but we do not handle
1300 double or triple faults yet. */
Andreas Färber27103422013-08-26 08:31:06 +02001301 do_interrupt_all(cpu, cs->exception_index,
Blue Swirle694d4e2011-05-16 19:38:48 +00001302 env->exception_is_int,
1303 env->error_code,
1304 env->exception_next_eip, 0);
1305 /* successfully delivered */
1306 env->old_exception = -1;
1307#endif
Blue Swirle694d4e2011-05-16 19:38:48 +00001308}
1309
Blue Swirl2999a0b2012-04-29 19:47:06 +00001310void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
Blue Swirle694d4e2011-05-16 19:38:48 +00001311{
Andreas Färberca4c8102013-07-03 02:00:09 +02001312 do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
Blue Swirle694d4e2011-05-16 19:38:48 +00001313}
1314
Richard Henderson42f53fe2014-09-13 09:45:33 -07001315bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
1316{
1317 X86CPU *cpu = X86_CPU(cs);
1318 CPUX86State *env = &cpu->env;
1319 bool ret = false;
1320
1321#if !defined(CONFIG_USER_ONLY)
1322 if (interrupt_request & CPU_INTERRUPT_POLL) {
1323 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
1324 apic_poll_irq(cpu->apic_state);
Pavel Dovgalyuka4fc3212015-09-17 19:24:11 +03001325 /* Don't process multiple interrupt requests in a single call.
1326 This is required to make icount-driven execution deterministic. */
1327 return true;
Richard Henderson42f53fe2014-09-13 09:45:33 -07001328 }
1329#endif
1330 if (interrupt_request & CPU_INTERRUPT_SIPI) {
1331 do_cpu_sipi(cpu);
1332 } else if (env->hflags2 & HF2_GIF_MASK) {
1333 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
1334 !(env->hflags & HF_SMM_MASK)) {
1335 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0);
1336 cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
1337 do_smm_enter(cpu);
1338 ret = true;
1339 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
1340 !(env->hflags2 & HF2_NMI_MASK)) {
1341 cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
1342 env->hflags2 |= HF2_NMI_MASK;
1343 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
1344 ret = true;
1345 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
1346 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1347 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
1348 ret = true;
1349 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
1350 (((env->hflags2 & HF2_VINTR_MASK) &&
1351 (env->hflags2 & HF2_HIF_MASK)) ||
1352 (!(env->hflags2 & HF2_VINTR_MASK) &&
1353 (env->eflags & IF_MASK &&
1354 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
1355 int intno;
1356 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0);
1357 cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
1358 CPU_INTERRUPT_VIRQ);
1359 intno = cpu_get_pic_interrupt(env);
1360 qemu_log_mask(CPU_LOG_TB_IN_ASM,
1361 "Servicing hardware INT=0x%02x\n", intno);
1362 do_interrupt_x86_hardirq(env, intno, 1);
1363 /* ensure that no TB jump will be modified as
1364 the program flow was changed */
1365 ret = true;
1366#if !defined(CONFIG_USER_ONLY)
1367 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
1368 (env->eflags & IF_MASK) &&
1369 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
1370 int intno;
1371 /* FIXME: this should respect TPR */
1372 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0);
Paolo Bonzinib216aa62015-04-08 13:39:37 +02001373 intno = x86_ldl_phys(cs, env->vm_vmcb
Richard Henderson42f53fe2014-09-13 09:45:33 -07001374 + offsetof(struct vmcb, control.int_vector));
1375 qemu_log_mask(CPU_LOG_TB_IN_ASM,
1376 "Servicing virtual hardware INT=0x%02x\n", intno);
1377 do_interrupt_x86_hardirq(env, intno, 1);
1378 cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
1379 ret = true;
1380#endif
1381 }
1382 }
1383
1384 return ret;
1385}
1386
Blue Swirl2999a0b2012-04-29 19:47:06 +00001387void helper_lldt(CPUX86State *env, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001388{
1389 SegmentCache *dt;
1390 uint32_t e1, e2;
1391 int index, entry_limit;
1392 target_ulong ptr;
1393
1394 selector &= 0xffff;
1395 if ((selector & 0xfffc) == 0) {
1396 /* XXX: NULL selector case: invalid LDT */
1397 env->ldt.base = 0;
1398 env->ldt.limit = 0;
1399 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00001400 if (selector & 0x4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001401 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001402 }
bellardeaa728e2008-05-28 12:51:20 +00001403 dt = &env->gdt;
1404 index = selector & ~7;
1405#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00001406 if (env->hflags & HF_LMA_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00001407 entry_limit = 15;
Blue Swirl20054ef2012-04-28 15:33:48 +00001408 } else
bellardeaa728e2008-05-28 12:51:20 +00001409#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001410 {
bellardeaa728e2008-05-28 12:51:20 +00001411 entry_limit = 7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001412 }
1413 if ((index + entry_limit) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001414 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001415 }
bellardeaa728e2008-05-28 12:51:20 +00001416 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001417 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1418 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001419 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001420 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001421 }
1422 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001423 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001424 }
bellardeaa728e2008-05-28 12:51:20 +00001425#ifdef TARGET_X86_64
1426 if (env->hflags & HF_LMA_MASK) {
1427 uint32_t e3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001428
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001429 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001430 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1431 env->ldt.base |= (target_ulong)e3 << 32;
1432 } else
1433#endif
1434 {
1435 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1436 }
1437 }
1438 env->ldt.selector = selector;
1439}
1440
Blue Swirl2999a0b2012-04-29 19:47:06 +00001441void helper_ltr(CPUX86State *env, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001442{
1443 SegmentCache *dt;
1444 uint32_t e1, e2;
1445 int index, type, entry_limit;
1446 target_ulong ptr;
1447
1448 selector &= 0xffff;
1449 if ((selector & 0xfffc) == 0) {
1450 /* NULL selector case: invalid TR */
1451 env->tr.base = 0;
1452 env->tr.limit = 0;
1453 env->tr.flags = 0;
1454 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00001455 if (selector & 0x4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001456 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001457 }
bellardeaa728e2008-05-28 12:51:20 +00001458 dt = &env->gdt;
1459 index = selector & ~7;
1460#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00001461 if (env->hflags & HF_LMA_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00001462 entry_limit = 15;
Blue Swirl20054ef2012-04-28 15:33:48 +00001463 } else
bellardeaa728e2008-05-28 12:51:20 +00001464#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001465 {
bellardeaa728e2008-05-28 12:51:20 +00001466 entry_limit = 7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001467 }
1468 if ((index + entry_limit) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001469 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001470 }
bellardeaa728e2008-05-28 12:51:20 +00001471 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001472 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1473 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001474 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1475 if ((e2 & DESC_S_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001476 (type != 1 && type != 9)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001477 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001478 }
1479 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001480 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001481 }
bellardeaa728e2008-05-28 12:51:20 +00001482#ifdef TARGET_X86_64
1483 if (env->hflags & HF_LMA_MASK) {
1484 uint32_t e3, e4;
Blue Swirl20054ef2012-04-28 15:33:48 +00001485
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001486 e3 = cpu_ldl_kernel_ra(env, ptr + 8, GETPC());
1487 e4 = cpu_ldl_kernel_ra(env, ptr + 12, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001488 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001489 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001490 }
bellardeaa728e2008-05-28 12:51:20 +00001491 load_seg_cache_raw_dt(&env->tr, e1, e2);
1492 env->tr.base |= (target_ulong)e3 << 32;
1493 } else
1494#endif
1495 {
1496 load_seg_cache_raw_dt(&env->tr, e1, e2);
1497 }
1498 e2 |= DESC_TSS_BUSY_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001499 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001500 }
1501 env->tr.selector = selector;
1502}
1503
1504/* only works if protected mode and not VM86. seg_reg must be != R_CS */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001505void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
bellardeaa728e2008-05-28 12:51:20 +00001506{
1507 uint32_t e1, e2;
1508 int cpl, dpl, rpl;
1509 SegmentCache *dt;
1510 int index;
1511 target_ulong ptr;
1512
1513 selector &= 0xffff;
1514 cpl = env->hflags & HF_CPL_MASK;
1515 if ((selector & 0xfffc) == 0) {
1516 /* null selector case */
1517 if (seg_reg == R_SS
1518#ifdef TARGET_X86_64
1519 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1520#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00001521 ) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001522 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001523 }
bellardeaa728e2008-05-28 12:51:20 +00001524 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1525 } else {
1526
Blue Swirl20054ef2012-04-28 15:33:48 +00001527 if (selector & 0x4) {
bellardeaa728e2008-05-28 12:51:20 +00001528 dt = &env->ldt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001529 } else {
bellardeaa728e2008-05-28 12:51:20 +00001530 dt = &env->gdt;
Blue Swirl20054ef2012-04-28 15:33:48 +00001531 }
bellardeaa728e2008-05-28 12:51:20 +00001532 index = selector & ~7;
Blue Swirl20054ef2012-04-28 15:33:48 +00001533 if ((index + 7) > dt->limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001534 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001535 }
bellardeaa728e2008-05-28 12:51:20 +00001536 ptr = dt->base + index;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001537 e1 = cpu_ldl_kernel_ra(env, ptr, GETPC());
1538 e2 = cpu_ldl_kernel_ra(env, ptr + 4, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001539
Blue Swirl20054ef2012-04-28 15:33:48 +00001540 if (!(e2 & DESC_S_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001541 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001542 }
bellardeaa728e2008-05-28 12:51:20 +00001543 rpl = selector & 3;
1544 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1545 if (seg_reg == R_SS) {
1546 /* must be writable segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001547 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001548 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001549 }
1550 if (rpl != cpl || dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001551 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001552 }
bellardeaa728e2008-05-28 12:51:20 +00001553 } else {
1554 /* must be readable segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001555 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001556 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001557 }
bellardeaa728e2008-05-28 12:51:20 +00001558
1559 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1560 /* if not conforming code, test rights */
Blue Swirl20054ef2012-04-28 15:33:48 +00001561 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001562 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001563 }
bellardeaa728e2008-05-28 12:51:20 +00001564 }
1565 }
1566
1567 if (!(e2 & DESC_P_MASK)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001568 if (seg_reg == R_SS) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001569 raise_exception_err_ra(env, EXCP0C_STACK, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001570 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001571 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001572 }
bellardeaa728e2008-05-28 12:51:20 +00001573 }
1574
1575 /* set the access bit if not already set */
1576 if (!(e2 & DESC_A_MASK)) {
1577 e2 |= DESC_A_MASK;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001578 cpu_stl_kernel_ra(env, ptr + 4, e2, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001579 }
1580
1581 cpu_x86_load_seg_cache(env, seg_reg, selector,
1582 get_seg_base(e1, e2),
1583 get_seg_limit(e1, e2),
1584 e2);
1585#if 0
aliguori93fcfe32009-01-15 22:34:14 +00001586 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
bellardeaa728e2008-05-28 12:51:20 +00001587 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1588#endif
1589 }
1590}
1591
1592/* protected mode jump */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001593void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001594 target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001595{
1596 int gate_cs, type;
1597 uint32_t e1, e2, cpl, dpl, rpl, limit;
bellardeaa728e2008-05-28 12:51:20 +00001598
Blue Swirl20054ef2012-04-28 15:33:48 +00001599 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001600 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001601 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001602 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1603 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001604 }
bellardeaa728e2008-05-28 12:51:20 +00001605 cpl = env->hflags & HF_CPL_MASK;
1606 if (e2 & DESC_S_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001607 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001608 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001609 }
bellardeaa728e2008-05-28 12:51:20 +00001610 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1611 if (e2 & DESC_C_MASK) {
1612 /* conforming code segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001613 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001614 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001615 }
bellardeaa728e2008-05-28 12:51:20 +00001616 } else {
1617 /* non conforming code segment */
1618 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001619 if (rpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001620 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001621 }
1622 if (dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001623 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001624 }
bellardeaa728e2008-05-28 12:51:20 +00001625 }
Blue Swirl20054ef2012-04-28 15:33:48 +00001626 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001627 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001628 }
bellardeaa728e2008-05-28 12:51:20 +00001629 limit = get_seg_limit(e1, e2);
1630 if (new_eip > limit &&
Blue Swirl20054ef2012-04-28 15:33:48 +00001631 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001632 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001633 }
bellardeaa728e2008-05-28 12:51:20 +00001634 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1635 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001636 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001637 } else {
1638 /* jump to call or task gate */
1639 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1640 rpl = new_cs & 3;
1641 cpl = env->hflags & HF_CPL_MASK;
1642 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00001643 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00001644 case 1: /* 286 TSS */
1645 case 9: /* 386 TSS */
1646 case 5: /* task gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001647 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001648 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001649 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001650 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001651 break;
1652 case 4: /* 286 call gate */
1653 case 12: /* 386 call gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001654 if ((dpl < cpl) || (dpl < rpl)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001655 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001656 }
1657 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001658 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001659 }
bellardeaa728e2008-05-28 12:51:20 +00001660 gate_cs = e1 >> 16;
1661 new_eip = (e1 & 0xffff);
Blue Swirl20054ef2012-04-28 15:33:48 +00001662 if (type == 12) {
bellardeaa728e2008-05-28 12:51:20 +00001663 new_eip |= (e2 & 0xffff0000);
Blue Swirl20054ef2012-04-28 15:33:48 +00001664 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001665 if (load_segment_ra(env, &e1, &e2, gate_cs, GETPC()) != 0) {
1666 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001667 }
bellardeaa728e2008-05-28 12:51:20 +00001668 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1669 /* must be code segment */
1670 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
Blue Swirl20054ef2012-04-28 15:33:48 +00001671 (DESC_S_MASK | DESC_CS_MASK))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001672 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001673 }
bellardeaa728e2008-05-28 12:51:20 +00001674 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001675 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001676 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001677 }
1678 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001679 raise_exception_err_ra(env, EXCP0D_GPF, gate_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001680 }
bellardeaa728e2008-05-28 12:51:20 +00001681 limit = get_seg_limit(e1, e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001682 if (new_eip > limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001683 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001684 }
bellardeaa728e2008-05-28 12:51:20 +00001685 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1686 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001687 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001688 break;
1689 default:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001690 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001691 break;
1692 }
1693 }
1694}
1695
1696/* real mode call */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001697void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
bellardeaa728e2008-05-28 12:51:20 +00001698 int shift, int next_eip)
1699{
1700 int new_eip;
1701 uint32_t esp, esp_mask;
1702 target_ulong ssp;
1703
1704 new_eip = new_eip1;
liguang08b3ded2013-05-28 16:21:04 +08001705 esp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001706 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1707 ssp = env->segs[R_SS].base;
1708 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001709 PUSHL_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1710 PUSHL_RA(ssp, esp, esp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001711 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001712 PUSHW_RA(ssp, esp, esp_mask, env->segs[R_CS].selector, GETPC());
1713 PUSHW_RA(ssp, esp, esp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001714 }
1715
1716 SET_ESP(esp, esp_mask);
1717 env->eip = new_eip;
1718 env->segs[R_CS].selector = new_cs;
1719 env->segs[R_CS].base = (new_cs << 4);
1720}
1721
1722/* protected mode call */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001723void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001724 int shift, target_ulong next_eip)
bellardeaa728e2008-05-28 12:51:20 +00001725{
1726 int new_stack, i;
1727 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
blueswir11c918eb2009-01-14 19:27:02 +00001728 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
bellardeaa728e2008-05-28 12:51:20 +00001729 uint32_t val, limit, old_sp_mask;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001730 target_ulong ssp, old_ssp;
bellardeaa728e2008-05-28 12:51:20 +00001731
aliguorid12d51d2009-01-15 21:48:06 +00001732 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
Andreas Färber8995b7a2013-07-03 01:07:10 +02001733 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
Blue Swirl20054ef2012-04-28 15:33:48 +00001734 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001735 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001736 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001737 if (load_segment_ra(env, &e1, &e2, new_cs, GETPC()) != 0) {
1738 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001739 }
bellardeaa728e2008-05-28 12:51:20 +00001740 cpl = env->hflags & HF_CPL_MASK;
aliguorid12d51d2009-01-15 21:48:06 +00001741 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
bellardeaa728e2008-05-28 12:51:20 +00001742 if (e2 & DESC_S_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00001743 if (!(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001744 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001745 }
bellardeaa728e2008-05-28 12:51:20 +00001746 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1747 if (e2 & DESC_C_MASK) {
1748 /* conforming code segment */
Blue Swirl20054ef2012-04-28 15:33:48 +00001749 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001750 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001751 }
bellardeaa728e2008-05-28 12:51:20 +00001752 } else {
1753 /* non conforming code segment */
1754 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001755 if (rpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001756 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001757 }
1758 if (dpl != cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001759 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001760 }
bellardeaa728e2008-05-28 12:51:20 +00001761 }
Blue Swirl20054ef2012-04-28 15:33:48 +00001762 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001763 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001764 }
bellardeaa728e2008-05-28 12:51:20 +00001765
1766#ifdef TARGET_X86_64
1767 /* XXX: check 16/32 bit cases in long mode */
1768 if (shift == 2) {
1769 target_ulong rsp;
Blue Swirl20054ef2012-04-28 15:33:48 +00001770
bellardeaa728e2008-05-28 12:51:20 +00001771 /* 64 bit case */
liguang08b3ded2013-05-28 16:21:04 +08001772 rsp = env->regs[R_ESP];
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001773 PUSHQ_RA(rsp, env->segs[R_CS].selector, GETPC());
1774 PUSHQ_RA(rsp, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001775 /* from this point, not restartable */
liguang08b3ded2013-05-28 16:21:04 +08001776 env->regs[R_ESP] = rsp;
bellardeaa728e2008-05-28 12:51:20 +00001777 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1778 get_seg_base(e1, e2),
1779 get_seg_limit(e1, e2), e2);
liguanga78d0ea2013-05-28 16:21:07 +08001780 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001781 } else
1782#endif
1783 {
liguang08b3ded2013-05-28 16:21:04 +08001784 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001785 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1786 ssp = env->segs[R_SS].base;
1787 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001788 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1789 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001790 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001791 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1792 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001793 }
1794
1795 limit = get_seg_limit(e1, e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00001796 if (new_eip > limit) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001797 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001798 }
bellardeaa728e2008-05-28 12:51:20 +00001799 /* from this point, not restartable */
1800 SET_ESP(sp, sp_mask);
1801 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1802 get_seg_base(e1, e2), limit, e2);
liguanga78d0ea2013-05-28 16:21:07 +08001803 env->eip = new_eip;
bellardeaa728e2008-05-28 12:51:20 +00001804 }
1805 } else {
1806 /* check gate type */
1807 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1808 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1809 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001810 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00001811 case 1: /* available 286 TSS */
1812 case 9: /* available 386 TSS */
1813 case 5: /* task gate */
Blue Swirl20054ef2012-04-28 15:33:48 +00001814 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001815 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001816 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001817 switch_tss_ra(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001818 return;
1819 case 4: /* 286 call gate */
1820 case 12: /* 386 call gate */
1821 break;
1822 default:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001823 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001824 break;
1825 }
1826 shift = type >> 3;
1827
Blue Swirl20054ef2012-04-28 15:33:48 +00001828 if (dpl < cpl || dpl < rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001829 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001830 }
bellardeaa728e2008-05-28 12:51:20 +00001831 /* check valid bit */
Blue Swirl20054ef2012-04-28 15:33:48 +00001832 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001833 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001834 }
bellardeaa728e2008-05-28 12:51:20 +00001835 selector = e1 >> 16;
1836 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1837 param_count = e2 & 0x1f;
Blue Swirl20054ef2012-04-28 15:33:48 +00001838 if ((selector & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001839 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001840 }
bellardeaa728e2008-05-28 12:51:20 +00001841
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001842 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
1843 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001844 }
1845 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001846 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001847 }
bellardeaa728e2008-05-28 12:51:20 +00001848 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001849 if (dpl > cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001850 raise_exception_err_ra(env, EXCP0D_GPF, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001851 }
1852 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001853 raise_exception_err_ra(env, EXCP0B_NOSEG, selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001854 }
bellardeaa728e2008-05-28 12:51:20 +00001855
1856 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1857 /* to inner privilege */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001858 get_ss_esp_from_tss(env, &ss, &sp, dpl, GETPC());
liguang90a25412013-05-28 16:21:10 +08001859 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1860 TARGET_FMT_lx "\n", ss, sp, param_count,
1861 env->regs[R_ESP]);
Blue Swirl20054ef2012-04-28 15:33:48 +00001862 if ((ss & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001863 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001864 }
1865 if ((ss & 3) != dpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001866 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001867 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001868 if (load_segment_ra(env, &ss_e1, &ss_e2, ss, GETPC()) != 0) {
1869 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001870 }
bellardeaa728e2008-05-28 12:51:20 +00001871 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00001872 if (ss_dpl != dpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001873 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001874 }
bellardeaa728e2008-05-28 12:51:20 +00001875 if (!(ss_e2 & DESC_S_MASK) ||
1876 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00001877 !(ss_e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001878 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001879 }
1880 if (!(ss_e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001881 raise_exception_err_ra(env, EXCP0A_TSS, ss & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001882 }
bellardeaa728e2008-05-28 12:51:20 +00001883
Blue Swirl20054ef2012-04-28 15:33:48 +00001884 /* push_size = ((param_count * 2) + 8) << shift; */
bellardeaa728e2008-05-28 12:51:20 +00001885
1886 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1887 old_ssp = env->segs[R_SS].base;
1888
1889 sp_mask = get_sp_mask(ss_e2);
1890 ssp = get_seg_base(ss_e1, ss_e2);
1891 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001892 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1893 PUSHL_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001894 for (i = param_count - 1; i >= 0; i--) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001895 val = cpu_ldl_kernel_ra(env, old_ssp +
1896 ((env->regs[R_ESP] + i * 4) &
1897 old_sp_mask), GETPC());
1898 PUSHL_RA(ssp, sp, sp_mask, val, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001899 }
1900 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001901 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_SS].selector, GETPC());
1902 PUSHW_RA(ssp, sp, sp_mask, env->regs[R_ESP], GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00001903 for (i = param_count - 1; i >= 0; i--) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001904 val = cpu_lduw_kernel_ra(env, old_ssp +
1905 ((env->regs[R_ESP] + i * 2) &
1906 old_sp_mask), GETPC());
1907 PUSHW_RA(ssp, sp, sp_mask, val, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001908 }
1909 }
1910 new_stack = 1;
1911 } else {
1912 /* to same privilege */
liguang08b3ded2013-05-28 16:21:04 +08001913 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001914 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1915 ssp = env->segs[R_SS].base;
Blue Swirl20054ef2012-04-28 15:33:48 +00001916 /* push_size = (4 << shift); */
bellardeaa728e2008-05-28 12:51:20 +00001917 new_stack = 0;
1918 }
1919
1920 if (shift) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001921 PUSHL_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1922 PUSHL_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001923 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001924 PUSHW_RA(ssp, sp, sp_mask, env->segs[R_CS].selector, GETPC());
1925 PUSHW_RA(ssp, sp, sp_mask, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001926 }
1927
1928 /* from this point, not restartable */
1929
1930 if (new_stack) {
1931 ss = (ss & ~3) | dpl;
1932 cpu_x86_load_seg_cache(env, R_SS, ss,
1933 ssp,
1934 get_seg_limit(ss_e1, ss_e2),
1935 ss_e2);
1936 }
1937
1938 selector = (selector & ~3) | dpl;
1939 cpu_x86_load_seg_cache(env, R_CS, selector,
1940 get_seg_base(e1, e2),
1941 get_seg_limit(e1, e2),
1942 e2);
bellardeaa728e2008-05-28 12:51:20 +00001943 SET_ESP(sp, sp_mask);
liguanga78d0ea2013-05-28 16:21:07 +08001944 env->eip = offset;
bellardeaa728e2008-05-28 12:51:20 +00001945 }
bellardeaa728e2008-05-28 12:51:20 +00001946}
1947
1948/* real and vm86 mode iret */
Blue Swirl2999a0b2012-04-29 19:47:06 +00001949void helper_iret_real(CPUX86State *env, int shift)
bellardeaa728e2008-05-28 12:51:20 +00001950{
1951 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1952 target_ulong ssp;
1953 int eflags_mask;
1954
Blue Swirl20054ef2012-04-28 15:33:48 +00001955 sp_mask = 0xffff; /* XXXX: use SS segment size? */
liguang08b3ded2013-05-28 16:21:04 +08001956 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00001957 ssp = env->segs[R_SS].base;
1958 if (shift == 1) {
1959 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001960 POPL_RA(ssp, sp, sp_mask, new_eip, GETPC());
1961 POPL_RA(ssp, sp, sp_mask, new_cs, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001962 new_cs &= 0xffff;
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001963 POPL_RA(ssp, sp, sp_mask, new_eflags, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001964 } else {
1965 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03001966 POPW_RA(ssp, sp, sp_mask, new_eip, GETPC());
1967 POPW_RA(ssp, sp, sp_mask, new_cs, GETPC());
1968 POPW_RA(ssp, sp, sp_mask, new_eflags, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00001969 }
liguang08b3ded2013-05-28 16:21:04 +08001970 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
malcbdadc0b2008-10-02 20:02:27 +00001971 env->segs[R_CS].selector = new_cs;
1972 env->segs[R_CS].base = (new_cs << 4);
bellardeaa728e2008-05-28 12:51:20 +00001973 env->eip = new_eip;
Blue Swirl20054ef2012-04-28 15:33:48 +00001974 if (env->eflags & VM_MASK) {
1975 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1976 NT_MASK;
1977 } else {
1978 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1979 RF_MASK | NT_MASK;
1980 }
1981 if (shift == 0) {
bellardeaa728e2008-05-28 12:51:20 +00001982 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +00001983 }
Blue Swirl997ff0d2012-04-29 15:01:21 +00001984 cpu_load_eflags(env, new_eflags, eflags_mask);
bellarddb620f42008-06-04 17:02:19 +00001985 env->hflags2 &= ~HF2_NMI_MASK;
bellardeaa728e2008-05-28 12:51:20 +00001986}
1987
Blue Swirl2999a0b2012-04-29 19:47:06 +00001988static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
bellardeaa728e2008-05-28 12:51:20 +00001989{
1990 int dpl;
1991 uint32_t e2;
1992
1993 /* XXX: on x86_64, we do not want to nullify FS and GS because
1994 they may still contain a valid base. I would be interested to
1995 know how a real x86_64 CPU behaves */
1996 if ((seg_reg == R_FS || seg_reg == R_GS) &&
Blue Swirl20054ef2012-04-28 15:33:48 +00001997 (env->segs[seg_reg].selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00001998 return;
Blue Swirl20054ef2012-04-28 15:33:48 +00001999 }
bellardeaa728e2008-05-28 12:51:20 +00002000
2001 e2 = env->segs[seg_reg].flags;
2002 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2003 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2004 /* data or non conforming code segment */
2005 if (dpl < cpl) {
2006 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2007 }
2008 }
2009}
2010
2011/* protected mode iret */
Blue Swirl2999a0b2012-04-29 19:47:06 +00002012static inline void helper_ret_protected(CPUX86State *env, int shift,
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002013 int is_iret, int addend,
2014 uintptr_t retaddr)
bellardeaa728e2008-05-28 12:51:20 +00002015{
2016 uint32_t new_cs, new_eflags, new_ss;
2017 uint32_t new_es, new_ds, new_fs, new_gs;
2018 uint32_t e1, e2, ss_e1, ss_e2;
2019 int cpl, dpl, rpl, eflags_mask, iopl;
2020 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2021
2022#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002023 if (shift == 2) {
bellardeaa728e2008-05-28 12:51:20 +00002024 sp_mask = -1;
Blue Swirl20054ef2012-04-28 15:33:48 +00002025 } else
bellardeaa728e2008-05-28 12:51:20 +00002026#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002027 {
bellardeaa728e2008-05-28 12:51:20 +00002028 sp_mask = get_sp_mask(env->segs[R_SS].flags);
Blue Swirl20054ef2012-04-28 15:33:48 +00002029 }
liguang08b3ded2013-05-28 16:21:04 +08002030 sp = env->regs[R_ESP];
bellardeaa728e2008-05-28 12:51:20 +00002031 ssp = env->segs[R_SS].base;
2032 new_eflags = 0; /* avoid warning */
2033#ifdef TARGET_X86_64
2034 if (shift == 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002035 POPQ_RA(sp, new_eip, retaddr);
2036 POPQ_RA(sp, new_cs, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002037 new_cs &= 0xffff;
2038 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002039 POPQ_RA(sp, new_eflags, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002040 }
2041 } else
2042#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002043 {
2044 if (shift == 1) {
2045 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002046 POPL_RA(ssp, sp, sp_mask, new_eip, retaddr);
2047 POPL_RA(ssp, sp, sp_mask, new_cs, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002048 new_cs &= 0xffff;
2049 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002050 POPL_RA(ssp, sp, sp_mask, new_eflags, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002051 if (new_eflags & VM_MASK) {
2052 goto return_to_vm86;
2053 }
2054 }
2055 } else {
2056 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002057 POPW_RA(ssp, sp, sp_mask, new_eip, retaddr);
2058 POPW_RA(ssp, sp, sp_mask, new_cs, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002059 if (is_iret) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002060 POPW_RA(ssp, sp, sp_mask, new_eflags, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002061 }
bellardeaa728e2008-05-28 12:51:20 +00002062 }
bellardeaa728e2008-05-28 12:51:20 +00002063 }
aliguorid12d51d2009-01-15 21:48:06 +00002064 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2065 new_cs, new_eip, shift, addend);
Andreas Färber8995b7a2013-07-03 01:07:10 +02002066 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
Blue Swirl20054ef2012-04-28 15:33:48 +00002067 if ((new_cs & 0xfffc) == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002068 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002069 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002070 if (load_segment_ra(env, &e1, &e2, new_cs, retaddr) != 0) {
2071 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002072 }
bellardeaa728e2008-05-28 12:51:20 +00002073 if (!(e2 & DESC_S_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00002074 !(e2 & DESC_CS_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002075 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002076 }
bellardeaa728e2008-05-28 12:51:20 +00002077 cpl = env->hflags & HF_CPL_MASK;
2078 rpl = new_cs & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002079 if (rpl < cpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002080 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002081 }
bellardeaa728e2008-05-28 12:51:20 +00002082 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2083 if (e2 & DESC_C_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002084 if (dpl > rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002085 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002086 }
bellardeaa728e2008-05-28 12:51:20 +00002087 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002088 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002089 raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002090 }
bellardeaa728e2008-05-28 12:51:20 +00002091 }
Blue Swirl20054ef2012-04-28 15:33:48 +00002092 if (!(e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002093 raise_exception_err_ra(env, EXCP0B_NOSEG, new_cs & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002094 }
bellardeaa728e2008-05-28 12:51:20 +00002095
2096 sp += addend;
2097 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2098 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
ths1235fc02008-06-03 19:51:57 +00002099 /* return to same privilege level */
bellardeaa728e2008-05-28 12:51:20 +00002100 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2101 get_seg_base(e1, e2),
2102 get_seg_limit(e1, e2),
2103 e2);
2104 } else {
2105 /* return to different privilege level */
2106#ifdef TARGET_X86_64
2107 if (shift == 2) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002108 POPQ_RA(sp, new_esp, retaddr);
2109 POPQ_RA(sp, new_ss, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002110 new_ss &= 0xffff;
2111 } else
2112#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002113 {
2114 if (shift == 1) {
2115 /* 32 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002116 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2117 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002118 new_ss &= 0xffff;
2119 } else {
2120 /* 16 bits */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002121 POPW_RA(ssp, sp, sp_mask, new_esp, retaddr);
2122 POPW_RA(ssp, sp, sp_mask, new_ss, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002123 }
bellardeaa728e2008-05-28 12:51:20 +00002124 }
aliguorid12d51d2009-01-15 21:48:06 +00002125 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
Blue Swirl20054ef2012-04-28 15:33:48 +00002126 new_ss, new_esp);
bellardeaa728e2008-05-28 12:51:20 +00002127 if ((new_ss & 0xfffc) == 0) {
2128#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002129 /* NULL ss is allowed in long mode if cpl != 3 */
2130 /* XXX: test CS64? */
bellardeaa728e2008-05-28 12:51:20 +00002131 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2132 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2133 0, 0xffffffff,
2134 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2135 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2136 DESC_W_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00002137 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
bellardeaa728e2008-05-28 12:51:20 +00002138 } else
2139#endif
2140 {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002141 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002142 }
2143 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002144 if ((new_ss & 3) != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002145 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002146 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002147 if (load_segment_ra(env, &ss_e1, &ss_e2, new_ss, retaddr) != 0) {
2148 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002149 }
bellardeaa728e2008-05-28 12:51:20 +00002150 if (!(ss_e2 & DESC_S_MASK) ||
2151 (ss_e2 & DESC_CS_MASK) ||
Blue Swirl20054ef2012-04-28 15:33:48 +00002152 !(ss_e2 & DESC_W_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002153 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002154 }
bellardeaa728e2008-05-28 12:51:20 +00002155 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002156 if (dpl != rpl) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002157 raise_exception_err_ra(env, EXCP0D_GPF, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002158 }
2159 if (!(ss_e2 & DESC_P_MASK)) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002160 raise_exception_err_ra(env, EXCP0B_NOSEG, new_ss & 0xfffc, retaddr);
Blue Swirl20054ef2012-04-28 15:33:48 +00002161 }
bellardeaa728e2008-05-28 12:51:20 +00002162 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2163 get_seg_base(ss_e1, ss_e2),
2164 get_seg_limit(ss_e1, ss_e2),
2165 ss_e2);
2166 }
2167
2168 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2169 get_seg_base(e1, e2),
2170 get_seg_limit(e1, e2),
2171 e2);
bellardeaa728e2008-05-28 12:51:20 +00002172 sp = new_esp;
2173#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002174 if (env->hflags & HF_CS64_MASK) {
bellardeaa728e2008-05-28 12:51:20 +00002175 sp_mask = -1;
Blue Swirl20054ef2012-04-28 15:33:48 +00002176 } else
bellardeaa728e2008-05-28 12:51:20 +00002177#endif
Blue Swirl20054ef2012-04-28 15:33:48 +00002178 {
bellardeaa728e2008-05-28 12:51:20 +00002179 sp_mask = get_sp_mask(ss_e2);
Blue Swirl20054ef2012-04-28 15:33:48 +00002180 }
bellardeaa728e2008-05-28 12:51:20 +00002181
2182 /* validate data segments */
Blue Swirl2999a0b2012-04-29 19:47:06 +00002183 validate_seg(env, R_ES, rpl);
2184 validate_seg(env, R_DS, rpl);
2185 validate_seg(env, R_FS, rpl);
2186 validate_seg(env, R_GS, rpl);
bellardeaa728e2008-05-28 12:51:20 +00002187
2188 sp += addend;
2189 }
2190 SET_ESP(sp, sp_mask);
2191 env->eip = new_eip;
2192 if (is_iret) {
2193 /* NOTE: 'cpl' is the _old_ CPL */
2194 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002195 if (cpl == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002196 eflags_mask |= IOPL_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002197 }
bellardeaa728e2008-05-28 12:51:20 +00002198 iopl = (env->eflags >> IOPL_SHIFT) & 3;
Blue Swirl20054ef2012-04-28 15:33:48 +00002199 if (cpl <= iopl) {
bellardeaa728e2008-05-28 12:51:20 +00002200 eflags_mask |= IF_MASK;
Blue Swirl20054ef2012-04-28 15:33:48 +00002201 }
2202 if (shift == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002203 eflags_mask &= 0xffff;
Blue Swirl20054ef2012-04-28 15:33:48 +00002204 }
Blue Swirl997ff0d2012-04-29 15:01:21 +00002205 cpu_load_eflags(env, new_eflags, eflags_mask);
bellardeaa728e2008-05-28 12:51:20 +00002206 }
2207 return;
2208
2209 return_to_vm86:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002210 POPL_RA(ssp, sp, sp_mask, new_esp, retaddr);
2211 POPL_RA(ssp, sp, sp_mask, new_ss, retaddr);
2212 POPL_RA(ssp, sp, sp_mask, new_es, retaddr);
2213 POPL_RA(ssp, sp, sp_mask, new_ds, retaddr);
2214 POPL_RA(ssp, sp, sp_mask, new_fs, retaddr);
2215 POPL_RA(ssp, sp, sp_mask, new_gs, retaddr);
bellardeaa728e2008-05-28 12:51:20 +00002216
2217 /* modify processor state */
Blue Swirl997ff0d2012-04-29 15:01:21 +00002218 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2219 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2220 VIP_MASK);
Blue Swirl2999a0b2012-04-29 19:47:06 +00002221 load_seg_vm(env, R_CS, new_cs & 0xffff);
Blue Swirl2999a0b2012-04-29 19:47:06 +00002222 load_seg_vm(env, R_SS, new_ss & 0xffff);
2223 load_seg_vm(env, R_ES, new_es & 0xffff);
2224 load_seg_vm(env, R_DS, new_ds & 0xffff);
2225 load_seg_vm(env, R_FS, new_fs & 0xffff);
2226 load_seg_vm(env, R_GS, new_gs & 0xffff);
bellardeaa728e2008-05-28 12:51:20 +00002227
2228 env->eip = new_eip & 0xffff;
liguang08b3ded2013-05-28 16:21:04 +08002229 env->regs[R_ESP] = new_esp;
bellardeaa728e2008-05-28 12:51:20 +00002230}
2231
Blue Swirl2999a0b2012-04-29 19:47:06 +00002232void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
bellardeaa728e2008-05-28 12:51:20 +00002233{
2234 int tss_selector, type;
2235 uint32_t e1, e2;
2236
2237 /* specific case for TSS */
2238 if (env->eflags & NT_MASK) {
2239#ifdef TARGET_X86_64
Blue Swirl20054ef2012-04-28 15:33:48 +00002240 if (env->hflags & HF_LMA_MASK) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002241 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002242 }
bellardeaa728e2008-05-28 12:51:20 +00002243#endif
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002244 tss_selector = cpu_lduw_kernel_ra(env, env->tr.base + 0, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002245 if (tss_selector & 4) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002246 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002247 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002248 if (load_segment_ra(env, &e1, &e2, tss_selector, GETPC()) != 0) {
2249 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002250 }
bellardeaa728e2008-05-28 12:51:20 +00002251 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2252 /* NOTE: we check both segment and busy TSS */
Blue Swirl20054ef2012-04-28 15:33:48 +00002253 if (type != 3) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002254 raise_exception_err_ra(env, EXCP0A_TSS, tss_selector & 0xfffc, GETPC());
Blue Swirl20054ef2012-04-28 15:33:48 +00002255 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002256 switch_tss_ra(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002257 } else {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002258 helper_ret_protected(env, shift, 1, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002259 }
bellarddb620f42008-06-04 17:02:19 +00002260 env->hflags2 &= ~HF2_NMI_MASK;
bellardeaa728e2008-05-28 12:51:20 +00002261}
2262
Blue Swirl2999a0b2012-04-29 19:47:06 +00002263void helper_lret_protected(CPUX86State *env, int shift, int addend)
bellardeaa728e2008-05-28 12:51:20 +00002264{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002265 helper_ret_protected(env, shift, 0, addend, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002266}
2267
Blue Swirl2999a0b2012-04-29 19:47:06 +00002268void helper_sysenter(CPUX86State *env)
bellardeaa728e2008-05-28 12:51:20 +00002269{
2270 if (env->sysenter_cs == 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002271 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002272 }
2273 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
balrog2436b612008-09-25 18:16:18 +00002274
2275#ifdef TARGET_X86_64
2276 if (env->hflags & HF_LMA_MASK) {
2277 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2278 0, 0xffffffff,
2279 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2280 DESC_S_MASK |
Blue Swirl20054ef2012-04-28 15:33:48 +00002281 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2282 DESC_L_MASK);
balrog2436b612008-09-25 18:16:18 +00002283 } else
2284#endif
2285 {
2286 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2287 0, 0xffffffff,
2288 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2289 DESC_S_MASK |
2290 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2291 }
bellardeaa728e2008-05-28 12:51:20 +00002292 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2293 0, 0xffffffff,
2294 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2295 DESC_S_MASK |
2296 DESC_W_MASK | DESC_A_MASK);
liguang08b3ded2013-05-28 16:21:04 +08002297 env->regs[R_ESP] = env->sysenter_esp;
liguanga78d0ea2013-05-28 16:21:07 +08002298 env->eip = env->sysenter_eip;
bellardeaa728e2008-05-28 12:51:20 +00002299}
2300
Blue Swirl2999a0b2012-04-29 19:47:06 +00002301void helper_sysexit(CPUX86State *env, int dflag)
bellardeaa728e2008-05-28 12:51:20 +00002302{
2303 int cpl;
2304
2305 cpl = env->hflags & HF_CPL_MASK;
2306 if (env->sysenter_cs == 0 || cpl != 0) {
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002307 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
bellardeaa728e2008-05-28 12:51:20 +00002308 }
balrog2436b612008-09-25 18:16:18 +00002309#ifdef TARGET_X86_64
2310 if (dflag == 2) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002311 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2312 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002313 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2314 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
Blue Swirl20054ef2012-04-28 15:33:48 +00002315 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2316 DESC_L_MASK);
2317 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2318 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002319 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2320 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2321 DESC_W_MASK | DESC_A_MASK);
2322 } else
2323#endif
2324 {
Blue Swirl20054ef2012-04-28 15:33:48 +00002325 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2326 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002327 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2328 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2329 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
Blue Swirl20054ef2012-04-28 15:33:48 +00002330 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2331 3, 0, 0xffffffff,
balrog2436b612008-09-25 18:16:18 +00002332 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2333 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2334 DESC_W_MASK | DESC_A_MASK);
2335 }
liguang08b3ded2013-05-28 16:21:04 +08002336 env->regs[R_ESP] = env->regs[R_ECX];
liguanga78d0ea2013-05-28 16:21:07 +08002337 env->eip = env->regs[R_EDX];
bellardeaa728e2008-05-28 12:51:20 +00002338}
2339
Blue Swirl2999a0b2012-04-29 19:47:06 +00002340target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002341{
2342 unsigned int limit;
2343 uint32_t e1, e2, eflags, selector;
2344 int rpl, dpl, cpl, type;
2345
2346 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002347 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002348 if ((selector & 0xfffc) == 0) {
aliguoridc1ded52009-03-20 16:13:41 +00002349 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002350 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002351 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002352 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002353 }
bellardeaa728e2008-05-28 12:51:20 +00002354 rpl = selector & 3;
2355 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2356 cpl = env->hflags & HF_CPL_MASK;
2357 if (e2 & DESC_S_MASK) {
2358 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2359 /* conforming */
2360 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002361 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002362 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002363 }
bellardeaa728e2008-05-28 12:51:20 +00002364 }
2365 } else {
2366 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00002367 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00002368 case 1:
2369 case 2:
2370 case 3:
2371 case 9:
2372 case 11:
2373 break;
2374 default:
2375 goto fail;
2376 }
2377 if (dpl < cpl || dpl < rpl) {
2378 fail:
2379 CC_SRC = eflags & ~CC_Z;
2380 return 0;
2381 }
2382 }
2383 limit = get_seg_limit(e1, e2);
2384 CC_SRC = eflags | CC_Z;
2385 return limit;
2386}
2387
Blue Swirl2999a0b2012-04-29 19:47:06 +00002388target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002389{
2390 uint32_t e1, e2, eflags, selector;
2391 int rpl, dpl, cpl, type;
2392
2393 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002394 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002395 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002396 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002397 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002398 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002399 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002400 }
bellardeaa728e2008-05-28 12:51:20 +00002401 rpl = selector & 3;
2402 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2403 cpl = env->hflags & HF_CPL_MASK;
2404 if (e2 & DESC_S_MASK) {
2405 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2406 /* conforming */
2407 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002408 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002409 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002410 }
bellardeaa728e2008-05-28 12:51:20 +00002411 }
2412 } else {
2413 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
Blue Swirl20054ef2012-04-28 15:33:48 +00002414 switch (type) {
bellardeaa728e2008-05-28 12:51:20 +00002415 case 1:
2416 case 2:
2417 case 3:
2418 case 4:
2419 case 5:
2420 case 9:
2421 case 11:
2422 case 12:
2423 break;
2424 default:
2425 goto fail;
2426 }
2427 if (dpl < cpl || dpl < rpl) {
2428 fail:
2429 CC_SRC = eflags & ~CC_Z;
2430 return 0;
2431 }
2432 }
2433 CC_SRC = eflags | CC_Z;
2434 return e2 & 0x00f0ff00;
2435}
2436
Blue Swirl2999a0b2012-04-29 19:47:06 +00002437void helper_verr(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002438{
2439 uint32_t e1, e2, eflags, selector;
2440 int rpl, dpl, cpl;
2441
2442 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002443 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002444 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002445 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002446 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002447 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002448 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002449 }
2450 if (!(e2 & DESC_S_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002451 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002452 }
bellardeaa728e2008-05-28 12:51:20 +00002453 rpl = selector & 3;
2454 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2455 cpl = env->hflags & HF_CPL_MASK;
2456 if (e2 & DESC_CS_MASK) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002457 if (!(e2 & DESC_R_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002458 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002459 }
bellardeaa728e2008-05-28 12:51:20 +00002460 if (!(e2 & DESC_C_MASK)) {
Blue Swirl20054ef2012-04-28 15:33:48 +00002461 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002462 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002463 }
bellardeaa728e2008-05-28 12:51:20 +00002464 }
2465 } else {
2466 if (dpl < cpl || dpl < rpl) {
2467 fail:
2468 CC_SRC = eflags & ~CC_Z;
2469 return;
2470 }
2471 }
2472 CC_SRC = eflags | CC_Z;
2473}
2474
Blue Swirl2999a0b2012-04-29 19:47:06 +00002475void helper_verw(CPUX86State *env, target_ulong selector1)
bellardeaa728e2008-05-28 12:51:20 +00002476{
2477 uint32_t e1, e2, eflags, selector;
2478 int rpl, dpl, cpl;
2479
2480 selector = selector1 & 0xffff;
Blue Swirlf0967a12012-04-29 12:45:34 +00002481 eflags = cpu_cc_compute_all(env, CC_OP);
Blue Swirl20054ef2012-04-28 15:33:48 +00002482 if ((selector & 0xfffc) == 0) {
bellardeaa728e2008-05-28 12:51:20 +00002483 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002484 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002485 if (load_segment_ra(env, &e1, &e2, selector, GETPC()) != 0) {
bellardeaa728e2008-05-28 12:51:20 +00002486 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002487 }
2488 if (!(e2 & DESC_S_MASK)) {
bellardeaa728e2008-05-28 12:51:20 +00002489 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002490 }
bellardeaa728e2008-05-28 12:51:20 +00002491 rpl = selector & 3;
2492 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2493 cpl = env->hflags & HF_CPL_MASK;
2494 if (e2 & DESC_CS_MASK) {
2495 goto fail;
2496 } else {
Blue Swirl20054ef2012-04-28 15:33:48 +00002497 if (dpl < cpl || dpl < rpl) {
bellardeaa728e2008-05-28 12:51:20 +00002498 goto fail;
Blue Swirl20054ef2012-04-28 15:33:48 +00002499 }
bellardeaa728e2008-05-28 12:51:20 +00002500 if (!(e2 & DESC_W_MASK)) {
2501 fail:
2502 CC_SRC = eflags & ~CC_Z;
2503 return;
2504 }
2505 }
2506 CC_SRC = eflags | CC_Z;
2507}
2508
Blue Swirl3e457172011-07-13 12:44:15 +00002509#if defined(CONFIG_USER_ONLY)
Blue Swirl2999a0b2012-04-29 19:47:06 +00002510void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
Blue Swirl3e457172011-07-13 12:44:15 +00002511{
Blue Swirl3e457172011-07-13 12:44:15 +00002512 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
Paolo Bonzinib98dbc92014-05-15 16:07:04 +02002513 int dpl = (env->eflags & VM_MASK) ? 3 : 0;
Blue Swirl3e457172011-07-13 12:44:15 +00002514 selector &= 0xffff;
2515 cpu_x86_load_seg_cache(env, seg_reg, selector,
Paolo Bonzinib98dbc92014-05-15 16:07:04 +02002516 (selector << 4), 0xffff,
2517 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2518 DESC_A_MASK | (dpl << DESC_DPL_SHIFT));
Blue Swirl3e457172011-07-13 12:44:15 +00002519 } else {
Blue Swirl2999a0b2012-04-29 19:47:06 +00002520 helper_load_seg(env, seg_reg, selector);
Blue Swirl3e457172011-07-13 12:44:15 +00002521 }
Blue Swirl3e457172011-07-13 12:44:15 +00002522}
Blue Swirl3e457172011-07-13 12:44:15 +00002523#endif
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002524
2525/* check if Port I/O is allowed in TSS */
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002526static inline void check_io(CPUX86State *env, int addr, int size,
2527 uintptr_t retaddr)
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002528{
2529 int io_offset, val, mask;
2530
2531 /* TSS must be a valid 32 bit one */
2532 if (!(env->tr.flags & DESC_P_MASK) ||
2533 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
2534 env->tr.limit < 103) {
2535 goto fail;
2536 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002537 io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002538 io_offset += (addr >> 3);
2539 /* Note: the check needs two bytes */
2540 if ((io_offset + 1) > env->tr.limit) {
2541 goto fail;
2542 }
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002543 val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002544 val >>= (addr & 7);
2545 mask = (1 << size) - 1;
2546 /* all bits must be zero to allow the I/O */
2547 if ((val & mask) != 0) {
2548 fail:
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002549 raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002550 }
2551}
2552
2553void helper_check_iob(CPUX86State *env, uint32_t t0)
2554{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002555 check_io(env, t0, 1, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002556}
2557
2558void helper_check_iow(CPUX86State *env, uint32_t t0)
2559{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002560 check_io(env, t0, 2, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002561}
2562
2563void helper_check_iol(CPUX86State *env, uint32_t t0)
2564{
Pavel Dovgalyuk100ec092015-07-10 12:57:36 +03002565 check_io(env, t0, 4, GETPC());
Paolo Bonzini81cf8d82014-03-28 18:47:57 +01002566}