bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | #include "tcg.h" |
| 25 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 26 | int gen_new_label(void); |
| 27 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 28 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 29 | { |
| 30 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 31 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 32 | } |
| 33 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 34 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 35 | { |
| 36 | *gen_opc_ptr++ = opc; |
| 37 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 38 | } |
| 39 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 40 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 41 | { |
| 42 | *gen_opc_ptr++ = opc; |
| 43 | *gen_opparam_ptr++ = arg1; |
| 44 | } |
| 45 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 46 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 47 | { |
| 48 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 49 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 50 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 51 | } |
| 52 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 53 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 54 | { |
| 55 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 56 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 57 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 58 | } |
| 59 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 60 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 61 | { |
| 62 | *gen_opc_ptr++ = opc; |
| 63 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 64 | *gen_opparam_ptr++ = arg2; |
| 65 | } |
| 66 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 67 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 68 | { |
| 69 | *gen_opc_ptr++ = opc; |
| 70 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 71 | *gen_opparam_ptr++ = arg2; |
| 72 | } |
| 73 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 74 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2) |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 75 | { |
| 76 | *gen_opc_ptr++ = opc; |
| 77 | *gen_opparam_ptr++ = arg1; |
| 78 | *gen_opparam_ptr++ = arg2; |
| 79 | } |
| 80 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 81 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 82 | TCGv_i32 arg3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 83 | { |
| 84 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 85 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 86 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 87 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 90 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 91 | TCGv_i64 arg3) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 92 | { |
| 93 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 94 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 95 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 96 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 97 | } |
| 98 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 99 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 100 | TCGv_i32 arg2, TCGArg arg3) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 101 | { |
| 102 | *gen_opc_ptr++ = opc; |
| 103 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 104 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 105 | *gen_opparam_ptr++ = arg3; |
| 106 | } |
| 107 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 108 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 109 | TCGv_i64 arg2, TCGArg arg3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 110 | { |
| 111 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 112 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 113 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 114 | *gen_opparam_ptr++ = arg3; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 115 | } |
| 116 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 117 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
| 118 | TCGv_ptr base, TCGArg offset) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 119 | { |
| 120 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 121 | *gen_opparam_ptr++ = GET_TCGV_I32(val); |
| 122 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
| 123 | *gen_opparam_ptr++ = offset; |
| 124 | } |
| 125 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 126 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
| 127 | TCGv_ptr base, TCGArg offset) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 128 | { |
| 129 | *gen_opc_ptr++ = opc; |
blueswir1 | a810a2d | 2008-12-07 17:16:42 +0000 | [diff] [blame] | 130 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 131 | *gen_opparam_ptr++ = GET_TCGV_PTR(base); |
| 132 | *gen_opparam_ptr++ = offset; |
| 133 | } |
| 134 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 135 | static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, |
| 136 | TCGv_i32 addr, TCGArg mem_index) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 137 | { |
| 138 | *gen_opc_ptr++ = opc; |
| 139 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
| 140 | *gen_opparam_ptr++ = GET_TCGV_I32(addr); |
| 141 | *gen_opparam_ptr++ = mem_index; |
| 142 | } |
| 143 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 144 | static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, |
| 145 | TCGv_i64 addr, TCGArg mem_index) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 146 | { |
| 147 | *gen_opc_ptr++ = opc; |
| 148 | *gen_opparam_ptr++ = GET_TCGV_I64(val); |
| 149 | *gen_opparam_ptr++ = GET_TCGV_I64(addr); |
| 150 | *gen_opparam_ptr++ = mem_index; |
| 151 | } |
| 152 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 153 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 154 | TCGv_i32 arg3, TCGv_i32 arg4) |
| 155 | { |
| 156 | *gen_opc_ptr++ = opc; |
| 157 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 158 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 159 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 160 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 161 | } |
| 162 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 163 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
blueswir1 | a810a2d | 2008-12-07 17:16:42 +0000 | [diff] [blame] | 164 | TCGv_i64 arg3, TCGv_i64 arg4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 165 | { |
| 166 | *gen_opc_ptr++ = opc; |
| 167 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 168 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 169 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 170 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 171 | } |
| 172 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 173 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 174 | TCGv_i32 arg3, TCGArg arg4) |
| 175 | { |
| 176 | *gen_opc_ptr++ = opc; |
| 177 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 178 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 179 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 180 | *gen_opparam_ptr++ = arg4; |
| 181 | } |
| 182 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 183 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 184 | TCGv_i64 arg3, TCGArg arg4) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 185 | { |
| 186 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 187 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 188 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 189 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 190 | *gen_opparam_ptr++ = arg4; |
| 191 | } |
| 192 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 193 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 194 | TCGArg arg3, TCGArg arg4) |
| 195 | { |
| 196 | *gen_opc_ptr++ = opc; |
| 197 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 198 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 199 | *gen_opparam_ptr++ = arg3; |
| 200 | *gen_opparam_ptr++ = arg4; |
| 201 | } |
| 202 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 203 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 204 | TCGArg arg3, TCGArg arg4) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 205 | { |
| 206 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 207 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 208 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 209 | *gen_opparam_ptr++ = arg3; |
| 210 | *gen_opparam_ptr++ = arg4; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 211 | } |
| 212 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 213 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 214 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 215 | { |
| 216 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 217 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 218 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 219 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 220 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 221 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 222 | } |
| 223 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 224 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 225 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5) |
| 226 | { |
| 227 | *gen_opc_ptr++ = opc; |
| 228 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 229 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 230 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 231 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 232 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 233 | } |
| 234 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 235 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 236 | TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5) |
| 237 | { |
| 238 | *gen_opc_ptr++ = opc; |
| 239 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 240 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 241 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 242 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 243 | *gen_opparam_ptr++ = arg5; |
| 244 | } |
| 245 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 246 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 247 | TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 248 | { |
| 249 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 250 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 251 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 252 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 253 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 254 | *gen_opparam_ptr++ = arg5; |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 255 | } |
| 256 | |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 257 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 258 | TCGv_i32 arg2, TCGv_i32 arg3, |
| 259 | TCGArg arg4, TCGArg arg5) |
| 260 | { |
| 261 | *gen_opc_ptr++ = opc; |
| 262 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 263 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 264 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 265 | *gen_opparam_ptr++ = arg4; |
| 266 | *gen_opparam_ptr++ = arg5; |
| 267 | } |
| 268 | |
| 269 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 270 | TCGv_i64 arg2, TCGv_i64 arg3, |
| 271 | TCGArg arg4, TCGArg arg5) |
| 272 | { |
| 273 | *gen_opc_ptr++ = opc; |
| 274 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 275 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 276 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 277 | *gen_opparam_ptr++ = arg4; |
| 278 | *gen_opparam_ptr++ = arg5; |
| 279 | } |
| 280 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 281 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 282 | TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5, |
| 283 | TCGv_i32 arg6) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 284 | { |
| 285 | *gen_opc_ptr++ = opc; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 286 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 287 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 288 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 289 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 290 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 291 | *gen_opparam_ptr++ = GET_TCGV_I32(arg6); |
| 292 | } |
| 293 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 294 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 295 | TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5, |
| 296 | TCGv_i64 arg6) |
| 297 | { |
| 298 | *gen_opc_ptr++ = opc; |
| 299 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 300 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 301 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 302 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 303 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 304 | *gen_opparam_ptr++ = GET_TCGV_I64(arg6); |
| 305 | } |
| 306 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 307 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 308 | TCGv_i32 arg3, TCGv_i32 arg4, |
| 309 | TCGv_i32 arg5, TCGArg arg6) |
| 310 | { |
| 311 | *gen_opc_ptr++ = opc; |
| 312 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 313 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 314 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 315 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 316 | *gen_opparam_ptr++ = GET_TCGV_I32(arg5); |
| 317 | *gen_opparam_ptr++ = arg6; |
| 318 | } |
| 319 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 320 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2, |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 321 | TCGv_i64 arg3, TCGv_i64 arg4, |
| 322 | TCGv_i64 arg5, TCGArg arg6) |
| 323 | { |
| 324 | *gen_opc_ptr++ = opc; |
| 325 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 326 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 327 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 328 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
| 329 | *gen_opparam_ptr++ = GET_TCGV_I64(arg5); |
| 330 | *gen_opparam_ptr++ = arg6; |
| 331 | } |
| 332 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 333 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1, |
| 334 | TCGv_i32 arg2, TCGv_i32 arg3, |
| 335 | TCGv_i32 arg4, TCGArg arg5, TCGArg arg6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 336 | { |
| 337 | *gen_opc_ptr++ = opc; |
| 338 | *gen_opparam_ptr++ = GET_TCGV_I32(arg1); |
| 339 | *gen_opparam_ptr++ = GET_TCGV_I32(arg2); |
| 340 | *gen_opparam_ptr++ = GET_TCGV_I32(arg3); |
| 341 | *gen_opparam_ptr++ = GET_TCGV_I32(arg4); |
| 342 | *gen_opparam_ptr++ = arg5; |
| 343 | *gen_opparam_ptr++ = arg6; |
| 344 | } |
| 345 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 346 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1, |
| 347 | TCGv_i64 arg2, TCGv_i64 arg3, |
| 348 | TCGv_i64 arg4, TCGArg arg5, TCGArg arg6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 349 | { |
| 350 | *gen_opc_ptr++ = opc; |
| 351 | *gen_opparam_ptr++ = GET_TCGV_I64(arg1); |
| 352 | *gen_opparam_ptr++ = GET_TCGV_I64(arg2); |
| 353 | *gen_opparam_ptr++ = GET_TCGV_I64(arg3); |
| 354 | *gen_opparam_ptr++ = GET_TCGV_I64(arg4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 355 | *gen_opparam_ptr++ = arg5; |
| 356 | *gen_opparam_ptr++ = arg6; |
| 357 | } |
| 358 | |
| 359 | static inline void gen_set_label(int n) |
| 360 | { |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 361 | tcg_gen_op1i(INDEX_op_set_label, n); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 362 | } |
| 363 | |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 364 | static inline void tcg_gen_br(int label) |
| 365 | { |
| 366 | tcg_gen_op1i(INDEX_op_br, label); |
| 367 | } |
| 368 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 369 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 370 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 371 | if (!TCGV_EQUAL_I32(ret, arg)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 372 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 373 | } |
| 374 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 375 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 376 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 377 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 378 | } |
| 379 | |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 380 | /* A version of dh_sizemask from def-helper.h that doesn't rely on |
| 381 | preprocessor magic. */ |
| 382 | static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed) |
| 383 | { |
| 384 | return (is_64bit << n*2) | (is_signed << (n*2 + 1)); |
| 385 | } |
| 386 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 387 | /* helper calls */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 388 | static inline void tcg_gen_helperN(void *func, int flags, int sizemask, |
| 389 | TCGArg ret, int nargs, TCGArg *args) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 390 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 391 | TCGv_ptr fn; |
| 392 | fn = tcg_const_ptr((tcg_target_long)func); |
| 393 | tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret, |
| 394 | nargs, args); |
| 395 | tcg_temp_free_ptr(fn); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 396 | } |
| 397 | |
Aurelien Jarno | dbfff4d | 2010-03-14 23:01:01 +0100 | [diff] [blame] | 398 | /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently |
| 399 | reserved for helpers in tcg-runtime.c. These helpers are all const |
| 400 | and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST | |
| 401 | TCG_CALL_PURE. This may need to be adjusted if these functions |
| 402 | start to be used with other helpers. */ |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 403 | static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret, |
Aurelien Jarno | 31d6655 | 2010-03-02 23:16:36 +0100 | [diff] [blame] | 404 | TCGv_i32 a, TCGv_i32 b) |
| 405 | { |
| 406 | TCGv_ptr fn; |
| 407 | TCGArg args[2]; |
| 408 | fn = tcg_const_ptr((tcg_target_long)func); |
| 409 | args[0] = GET_TCGV_I32(a); |
| 410 | args[1] = GET_TCGV_I32(b); |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 411 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
| 412 | GET_TCGV_I32(ret), 2, args); |
Aurelien Jarno | 31d6655 | 2010-03-02 23:16:36 +0100 | [diff] [blame] | 413 | tcg_temp_free_ptr(fn); |
| 414 | } |
| 415 | |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 416 | static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret, |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 417 | TCGv_i64 a, TCGv_i64 b) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 418 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 419 | TCGv_ptr fn; |
| 420 | TCGArg args[2]; |
| 421 | fn = tcg_const_ptr((tcg_target_long)func); |
| 422 | args[0] = GET_TCGV_I64(a); |
| 423 | args[1] = GET_TCGV_I64(b); |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 424 | tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask, |
| 425 | GET_TCGV_I64(ret), 2, args); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 426 | tcg_temp_free_ptr(fn); |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 427 | } |
| 428 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 429 | /* 32 bit ops */ |
| 430 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 431 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 432 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 433 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 434 | } |
| 435 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 436 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 437 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 438 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 439 | } |
| 440 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 441 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 442 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 443 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 444 | } |
| 445 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 446 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 447 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 448 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 449 | } |
| 450 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 451 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 452 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 453 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 454 | } |
| 455 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 456 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 457 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 458 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 459 | } |
| 460 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 461 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 462 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 463 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 464 | } |
| 465 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 466 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 467 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 468 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 469 | } |
| 470 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 471 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 472 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 473 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 474 | } |
| 475 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 476 | static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 477 | { |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 478 | /* some cases can be optimized here */ |
| 479 | if (arg2 == 0) { |
| 480 | tcg_gen_mov_i32(ret, arg1); |
| 481 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 482 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 483 | tcg_gen_add_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 484 | tcg_temp_free_i32(t0); |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 485 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 486 | } |
| 487 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 488 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 489 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 490 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 491 | } |
| 492 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 493 | static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 494 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 495 | TCGv_i32 t0 = tcg_const_i32(arg1); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 496 | tcg_gen_sub_i32(ret, t0, arg2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 497 | tcg_temp_free_i32(t0); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 498 | } |
| 499 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 500 | static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 501 | { |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 502 | /* some cases can be optimized here */ |
| 503 | if (arg2 == 0) { |
| 504 | tcg_gen_mov_i32(ret, arg1); |
| 505 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 506 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 507 | tcg_gen_sub_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 508 | tcg_temp_free_i32(t0); |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 509 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 510 | } |
| 511 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 512 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 513 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 514 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 515 | tcg_gen_mov_i32(ret, arg1); |
| 516 | } else { |
| 517 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
| 518 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 519 | } |
| 520 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 521 | static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 522 | { |
| 523 | /* some cases can be optimized here */ |
| 524 | if (arg2 == 0) { |
| 525 | tcg_gen_movi_i32(ret, 0); |
| 526 | } else if (arg2 == 0xffffffff) { |
| 527 | tcg_gen_mov_i32(ret, arg1); |
| 528 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 529 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 530 | tcg_gen_and_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 531 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 532 | } |
| 533 | } |
| 534 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 535 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 536 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 537 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 538 | tcg_gen_mov_i32(ret, arg1); |
| 539 | } else { |
| 540 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
| 541 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 542 | } |
| 543 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 544 | static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 545 | { |
| 546 | /* some cases can be optimized here */ |
| 547 | if (arg2 == 0xffffffff) { |
blueswir1 | 7089442 | 2008-02-20 18:01:23 +0000 | [diff] [blame] | 548 | tcg_gen_movi_i32(ret, 0xffffffff); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 549 | } else if (arg2 == 0) { |
| 550 | tcg_gen_mov_i32(ret, arg1); |
| 551 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 552 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 553 | tcg_gen_or_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 554 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 555 | } |
| 556 | } |
| 557 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 558 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 559 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 560 | if (TCGV_EQUAL_I32(arg1, arg2)) { |
| 561 | tcg_gen_movi_i32(ret, 0); |
| 562 | } else { |
| 563 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
| 564 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 565 | } |
| 566 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 567 | static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 568 | { |
| 569 | /* some cases can be optimized here */ |
| 570 | if (arg2 == 0) { |
| 571 | tcg_gen_mov_i32(ret, arg1); |
| 572 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 573 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 574 | tcg_gen_xor_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 575 | tcg_temp_free_i32(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 576 | } |
| 577 | } |
| 578 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 579 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 580 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 581 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 582 | } |
| 583 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 584 | static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 585 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 586 | if (arg2 == 0) { |
| 587 | tcg_gen_mov_i32(ret, arg1); |
| 588 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 589 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 590 | tcg_gen_shl_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 591 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 592 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 593 | } |
| 594 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 595 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 596 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 597 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 598 | } |
| 599 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 600 | static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 601 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 602 | if (arg2 == 0) { |
| 603 | tcg_gen_mov_i32(ret, arg1); |
| 604 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 605 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 606 | tcg_gen_shr_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 607 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 608 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 609 | } |
| 610 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 611 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 612 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 613 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 614 | } |
| 615 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 616 | static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 617 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 618 | if (arg2 == 0) { |
| 619 | tcg_gen_mov_i32(ret, arg1); |
| 620 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 621 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 622 | tcg_gen_sar_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 623 | tcg_temp_free_i32(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 624 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 625 | } |
| 626 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 627 | static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, |
| 628 | TCGv_i32 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 629 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 630 | tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 631 | } |
| 632 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 633 | static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, |
| 634 | int32_t arg2, int label_index) |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 635 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 636 | TCGv_i32 t0 = tcg_const_i32(arg2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 637 | tcg_gen_brcond_i32(cond, arg1, t0, label_index); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 638 | tcg_temp_free_i32(t0); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 639 | } |
| 640 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 641 | static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 642 | TCGv_i32 arg1, TCGv_i32 arg2) |
| 643 | { |
| 644 | tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); |
| 645 | } |
| 646 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 647 | static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
| 648 | TCGv_i32 arg1, int32_t arg2) |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 649 | { |
| 650 | TCGv_i32 t0 = tcg_const_i32(arg2); |
| 651 | tcg_gen_setcond_i32(cond, ret, arg1, t0); |
| 652 | tcg_temp_free_i32(t0); |
| 653 | } |
| 654 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 655 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 656 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 657 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 658 | } |
| 659 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 660 | static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 661 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 662 | TCGv_i32 t0 = tcg_const_i32(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 663 | tcg_gen_mul_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 664 | tcg_temp_free_i32(t0); |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 665 | } |
| 666 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 667 | static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 668 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 669 | if (TCG_TARGET_HAS_div_i32) { |
| 670 | tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2); |
| 671 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 672 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 673 | tcg_gen_sari_i32(t0, arg1, 31); |
| 674 | tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
| 675 | tcg_temp_free_i32(t0); |
| 676 | } else { |
| 677 | int sizemask = 0; |
| 678 | /* Return value and both arguments are 32-bit and signed. */ |
| 679 | sizemask |= tcg_gen_sizemask(0, 0, 1); |
| 680 | sizemask |= tcg_gen_sizemask(1, 0, 1); |
| 681 | sizemask |= tcg_gen_sizemask(2, 0, 1); |
| 682 | tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2); |
| 683 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 684 | } |
| 685 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 686 | static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 687 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 688 | if (TCG_TARGET_HAS_div_i32) { |
| 689 | tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); |
| 690 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 691 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 692 | tcg_gen_sari_i32(t0, arg1, 31); |
| 693 | tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
| 694 | tcg_temp_free_i32(t0); |
| 695 | } else { |
| 696 | int sizemask = 0; |
| 697 | /* Return value and both arguments are 32-bit and signed. */ |
| 698 | sizemask |= tcg_gen_sizemask(0, 0, 1); |
| 699 | sizemask |= tcg_gen_sizemask(1, 0, 1); |
| 700 | sizemask |= tcg_gen_sizemask(2, 0, 1); |
| 701 | tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2); |
| 702 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 703 | } |
| 704 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 705 | static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 706 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 707 | if (TCG_TARGET_HAS_div_i32) { |
| 708 | tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); |
| 709 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 710 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 711 | tcg_gen_movi_i32(t0, 0); |
| 712 | tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
| 713 | tcg_temp_free_i32(t0); |
| 714 | } else { |
| 715 | int sizemask = 0; |
| 716 | /* Return value and both arguments are 32-bit and unsigned. */ |
| 717 | sizemask |= tcg_gen_sizemask(0, 0, 0); |
| 718 | sizemask |= tcg_gen_sizemask(1, 0, 0); |
| 719 | sizemask |= tcg_gen_sizemask(2, 0, 0); |
| 720 | tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2); |
| 721 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 722 | } |
| 723 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 724 | static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 725 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 726 | if (TCG_TARGET_HAS_div_i32) { |
| 727 | tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); |
| 728 | } else if (TCG_TARGET_HAS_div2_i32) { |
| 729 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 730 | tcg_gen_movi_i32(t0, 0); |
| 731 | tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
| 732 | tcg_temp_free_i32(t0); |
| 733 | } else { |
| 734 | int sizemask = 0; |
| 735 | /* Return value and both arguments are 32-bit and unsigned. */ |
| 736 | sizemask |= tcg_gen_sizemask(0, 0, 0); |
| 737 | sizemask |= tcg_gen_sizemask(1, 0, 0); |
| 738 | sizemask |= tcg_gen_sizemask(2, 0, 0); |
| 739 | tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2); |
| 740 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 741 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 742 | |
| 743 | #if TCG_TARGET_REG_BITS == 32 |
| 744 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 745 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 746 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 747 | if (!TCGV_EQUAL_I64(ret, arg)) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 748 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
blueswir1 | 4d07272 | 2008-05-03 20:52:26 +0000 | [diff] [blame] | 749 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 750 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 751 | } |
| 752 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 753 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 754 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 755 | tcg_gen_movi_i32(TCGV_LOW(ret), arg); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 756 | tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 757 | } |
| 758 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 759 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 760 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 761 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 762 | tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 763 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 764 | } |
| 765 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 766 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 767 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 768 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 769 | tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); |
| 770 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 771 | } |
| 772 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 773 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 774 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 775 | { |
aurel32 | a747723 | 2009-02-09 20:43:53 +0000 | [diff] [blame] | 776 | tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 777 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 778 | } |
| 779 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 780 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 781 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 782 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 783 | tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); |
| 784 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 785 | } |
| 786 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 787 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 788 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 789 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 790 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 791 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 792 | } |
| 793 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 794 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 795 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 796 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 797 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
| 798 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 799 | } |
| 800 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 801 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 802 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 803 | { |
| 804 | /* since arg2 and ret have different types, they cannot be the |
| 805 | same temporary */ |
| 806 | #ifdef TCG_TARGET_WORDS_BIGENDIAN |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 807 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 808 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 809 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 810 | tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 811 | tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 812 | #endif |
| 813 | } |
| 814 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 815 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 816 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 817 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 818 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 819 | } |
| 820 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 821 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 822 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 823 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 824 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 825 | } |
| 826 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 827 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 828 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 829 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 830 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 831 | } |
| 832 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 833 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 834 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 835 | { |
| 836 | #ifdef TCG_TARGET_WORDS_BIGENDIAN |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 837 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 838 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 839 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 840 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 841 | tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 842 | #endif |
| 843 | } |
| 844 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 845 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 846 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 847 | tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 848 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 849 | TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 850 | } |
| 851 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 852 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 853 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 854 | tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 855 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 856 | TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 857 | } |
| 858 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 859 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 860 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 861 | tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 862 | tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 863 | } |
| 864 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 865 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 866 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 867 | tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
| 868 | tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 869 | } |
| 870 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 871 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 872 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 873 | tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 874 | tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 875 | } |
| 876 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 877 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 878 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 879 | tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 880 | tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 881 | } |
| 882 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 883 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 884 | { |
aurel32 | e510508 | 2009-03-11 02:57:30 +0000 | [diff] [blame] | 885 | tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 886 | tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 887 | } |
| 888 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 889 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 890 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 891 | tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 892 | tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 893 | } |
| 894 | |
| 895 | /* XXX: use generic code when basic block handling is OK or CPU |
| 896 | specific code (x86) */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 897 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 898 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 899 | int sizemask = 0; |
| 900 | /* Return value and both arguments are 64-bit and signed. */ |
| 901 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 902 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 903 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 904 | |
| 905 | tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 906 | } |
| 907 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 908 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 909 | { |
| 910 | tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
| 911 | } |
| 912 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 913 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 914 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 915 | int sizemask = 0; |
| 916 | /* Return value and both arguments are 64-bit and signed. */ |
| 917 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 918 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 919 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 920 | |
| 921 | tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 922 | } |
| 923 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 924 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 925 | { |
| 926 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
| 927 | } |
| 928 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 929 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 930 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 931 | int sizemask = 0; |
| 932 | /* Return value and both arguments are 64-bit and signed. */ |
| 933 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 934 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 935 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 936 | |
| 937 | tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 938 | } |
| 939 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 940 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 941 | { |
| 942 | tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
| 943 | } |
| 944 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 945 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
| 946 | TCGv_i64 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 947 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 948 | tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, |
| 949 | TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), |
| 950 | TCGV_HIGH(arg2), cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 951 | } |
| 952 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 953 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 954 | TCGv_i64 arg1, TCGv_i64 arg2) |
| 955 | { |
| 956 | tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), |
| 957 | TCGV_LOW(arg1), TCGV_HIGH(arg1), |
| 958 | TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); |
| 959 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 960 | } |
| 961 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 962 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 963 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 964 | TCGv_i64 t0; |
| 965 | TCGv_i32 t1; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 966 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 967 | t0 = tcg_temp_new_i64(); |
| 968 | t1 = tcg_temp_new_i32(); |
| 969 | |
| 970 | tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0), |
| 971 | TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 972 | |
| 973 | tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 974 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 975 | tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 976 | tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 977 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 978 | tcg_gen_mov_i64(ret, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 979 | tcg_temp_free_i64(t0); |
| 980 | tcg_temp_free_i32(t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 981 | } |
| 982 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 983 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 984 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 985 | int sizemask = 0; |
| 986 | /* Return value and both arguments are 64-bit and signed. */ |
| 987 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 988 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 989 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 990 | |
| 991 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 992 | } |
| 993 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 994 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 995 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 996 | int sizemask = 0; |
| 997 | /* Return value and both arguments are 64-bit and signed. */ |
| 998 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 999 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1000 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1001 | |
| 1002 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1003 | } |
| 1004 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1005 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1006 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1007 | int sizemask = 0; |
| 1008 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1009 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1010 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1011 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1012 | |
| 1013 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1014 | } |
| 1015 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1016 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1017 | { |
Richard Henderson | 2bece2c | 2010-06-14 17:35:27 -0700 | [diff] [blame] | 1018 | int sizemask = 0; |
| 1019 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1020 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1021 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1022 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1023 | |
| 1024 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | #else |
| 1028 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1029 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1030 | { |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 1031 | if (!TCGV_EQUAL_I64(ret, arg)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1032 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1033 | } |
| 1034 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1035 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1036 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1037 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1038 | } |
| 1039 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1040 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1041 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1042 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1043 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1044 | } |
| 1045 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1046 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1047 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1048 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1049 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1050 | } |
| 1051 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1052 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1053 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1054 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1055 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1058 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1059 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1060 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1061 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1062 | } |
| 1063 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1064 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1065 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1066 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1067 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1068 | } |
| 1069 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1070 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1071 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1072 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1073 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1074 | } |
| 1075 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1076 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1077 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1078 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1079 | } |
| 1080 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1081 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1082 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1083 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1084 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1085 | } |
| 1086 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1087 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1088 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1089 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1090 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1091 | } |
| 1092 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1093 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1094 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1095 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1096 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1097 | } |
| 1098 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 1099 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1100 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1101 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1102 | } |
| 1103 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1104 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1105 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1106 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1107 | } |
| 1108 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1109 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1110 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1111 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1112 | } |
| 1113 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1114 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1115 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1116 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1117 | tcg_gen_mov_i64(ret, arg1); |
| 1118 | } else { |
| 1119 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
| 1120 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1121 | } |
| 1122 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1123 | static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1124 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1125 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1126 | tcg_gen_and_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1127 | tcg_temp_free_i64(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1128 | } |
| 1129 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1130 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1131 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1132 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1133 | tcg_gen_mov_i64(ret, arg1); |
| 1134 | } else { |
| 1135 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
| 1136 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1137 | } |
| 1138 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1139 | static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1140 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1141 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1142 | tcg_gen_or_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1143 | tcg_temp_free_i64(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1144 | } |
| 1145 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1146 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1147 | { |
aurel32 | 7fc8105 | 2009-03-10 19:37:39 +0000 | [diff] [blame] | 1148 | if (TCGV_EQUAL_I64(arg1, arg2)) { |
| 1149 | tcg_gen_movi_i64(ret, 0); |
| 1150 | } else { |
| 1151 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
| 1152 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1153 | } |
| 1154 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1155 | static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1156 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1157 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1158 | tcg_gen_xor_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1159 | tcg_temp_free_i64(t0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1160 | } |
| 1161 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1162 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1163 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1164 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1165 | } |
| 1166 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1167 | static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1168 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1169 | if (arg2 == 0) { |
| 1170 | tcg_gen_mov_i64(ret, arg1); |
| 1171 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1172 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1173 | tcg_gen_shl_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1174 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1175 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1176 | } |
| 1177 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1178 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1179 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1180 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1183 | static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1184 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1185 | if (arg2 == 0) { |
| 1186 | tcg_gen_mov_i64(ret, arg1); |
| 1187 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1188 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1189 | tcg_gen_shr_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1190 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1191 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1192 | } |
| 1193 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1194 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1195 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1196 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1197 | } |
| 1198 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1199 | static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1200 | { |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1201 | if (arg2 == 0) { |
| 1202 | tcg_gen_mov_i64(ret, arg1); |
| 1203 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1204 | TCGv_i64 t0 = tcg_const_i64(arg2); |
bellard | e8996ee | 2008-05-23 17:33:39 +0000 | [diff] [blame] | 1205 | tcg_gen_sar_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1206 | tcg_temp_free_i64(t0); |
bellard | 34151a2 | 2008-05-22 13:25:14 +0000 | [diff] [blame] | 1207 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1208 | } |
| 1209 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1210 | static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, |
| 1211 | TCGv_i64 arg2, int label_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1212 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1213 | tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1214 | } |
| 1215 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1216 | static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 1217 | TCGv_i64 arg1, TCGv_i64 arg2) |
| 1218 | { |
| 1219 | tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); |
| 1220 | } |
| 1221 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1222 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1223 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1224 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1225 | } |
| 1226 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1227 | static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1228 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1229 | if (TCG_TARGET_HAS_div_i64) { |
| 1230 | tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2); |
| 1231 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1232 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1233 | tcg_gen_sari_i64(t0, arg1, 63); |
| 1234 | tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
| 1235 | tcg_temp_free_i64(t0); |
| 1236 | } else { |
| 1237 | int sizemask = 0; |
| 1238 | /* Return value and both arguments are 64-bit and signed. */ |
| 1239 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1240 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1241 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1242 | tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2); |
| 1243 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1244 | } |
| 1245 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1246 | static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1247 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1248 | if (TCG_TARGET_HAS_div_i64) { |
| 1249 | tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); |
| 1250 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1251 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1252 | tcg_gen_sari_i64(t0, arg1, 63); |
| 1253 | tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
| 1254 | tcg_temp_free_i64(t0); |
| 1255 | } else { |
| 1256 | int sizemask = 0; |
| 1257 | /* Return value and both arguments are 64-bit and signed. */ |
| 1258 | sizemask |= tcg_gen_sizemask(0, 1, 1); |
| 1259 | sizemask |= tcg_gen_sizemask(1, 1, 1); |
| 1260 | sizemask |= tcg_gen_sizemask(2, 1, 1); |
| 1261 | tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2); |
| 1262 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1263 | } |
| 1264 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1265 | static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1266 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1267 | if (TCG_TARGET_HAS_div_i64) { |
| 1268 | tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); |
| 1269 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1270 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1271 | tcg_gen_movi_i64(t0, 0); |
| 1272 | tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
| 1273 | tcg_temp_free_i64(t0); |
| 1274 | } else { |
| 1275 | int sizemask = 0; |
| 1276 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1277 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1278 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1279 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1280 | tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2); |
| 1281 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1282 | } |
| 1283 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1284 | static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1285 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1286 | if (TCG_TARGET_HAS_div_i64) { |
| 1287 | tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); |
| 1288 | } else if (TCG_TARGET_HAS_div2_i64) { |
| 1289 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1290 | tcg_gen_movi_i64(t0, 0); |
| 1291 | tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
| 1292 | tcg_temp_free_i64(t0); |
| 1293 | } else { |
| 1294 | int sizemask = 0; |
| 1295 | /* Return value and both arguments are 64-bit and unsigned. */ |
| 1296 | sizemask |= tcg_gen_sizemask(0, 1, 0); |
| 1297 | sizemask |= tcg_gen_sizemask(1, 1, 0); |
| 1298 | sizemask |= tcg_gen_sizemask(2, 1, 0); |
| 1299 | tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2); |
| 1300 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1301 | } |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1302 | #endif /* TCG_TARGET_REG_BITS == 32 */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1303 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1304 | static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1305 | { |
| 1306 | /* some cases can be optimized here */ |
| 1307 | if (arg2 == 0) { |
| 1308 | tcg_gen_mov_i64(ret, arg1); |
| 1309 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1310 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1311 | tcg_gen_add_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1312 | tcg_temp_free_i64(t0); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1313 | } |
| 1314 | } |
| 1315 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1316 | static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1317 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1318 | TCGv_i64 t0 = tcg_const_i64(arg1); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1319 | tcg_gen_sub_i64(ret, t0, arg2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1320 | tcg_temp_free_i64(t0); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1321 | } |
| 1322 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1323 | static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1324 | { |
| 1325 | /* some cases can be optimized here */ |
| 1326 | if (arg2 == 0) { |
| 1327 | tcg_gen_mov_i64(ret, arg1); |
| 1328 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1329 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1330 | tcg_gen_sub_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1331 | tcg_temp_free_i64(t0); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1332 | } |
| 1333 | } |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1334 | static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, |
| 1335 | int64_t arg2, int label_index) |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1336 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1337 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1338 | tcg_gen_brcond_i64(cond, arg1, t0, label_index); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1339 | tcg_temp_free_i64(t0); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1340 | } |
| 1341 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 1342 | static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
| 1343 | TCGv_i64 arg1, int64_t arg2) |
Aurelien Jarno | 5105c55 | 2010-02-08 12:10:15 +0100 | [diff] [blame] | 1344 | { |
| 1345 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 1346 | tcg_gen_setcond_i64(cond, ret, arg1, t0); |
| 1347 | tcg_temp_free_i64(t0); |
| 1348 | } |
| 1349 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1350 | static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1351 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1352 | TCGv_i64 t0 = tcg_const_i64(arg2); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1353 | tcg_gen_mul_i64(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1354 | tcg_temp_free_i64(t0); |
aurel32 | f02bb95 | 2008-11-03 07:08:26 +0000 | [diff] [blame] | 1355 | } |
| 1356 | |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 1357 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1358 | /***************************************/ |
| 1359 | /* optional operations */ |
| 1360 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1361 | static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1362 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1363 | if (TCG_TARGET_HAS_ext8s_i32) { |
| 1364 | tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg); |
| 1365 | } else { |
| 1366 | tcg_gen_shli_i32(ret, arg, 24); |
| 1367 | tcg_gen_sari_i32(ret, ret, 24); |
| 1368 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1369 | } |
| 1370 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1371 | static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1372 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1373 | if (TCG_TARGET_HAS_ext16s_i32) { |
| 1374 | tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg); |
| 1375 | } else { |
| 1376 | tcg_gen_shli_i32(ret, arg, 16); |
| 1377 | tcg_gen_sari_i32(ret, ret, 16); |
| 1378 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1379 | } |
| 1380 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1381 | static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1382 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1383 | if (TCG_TARGET_HAS_ext8u_i32) { |
| 1384 | tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); |
| 1385 | } else { |
| 1386 | tcg_gen_andi_i32(ret, arg, 0xffu); |
| 1387 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1388 | } |
| 1389 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1390 | static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1391 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1392 | if (TCG_TARGET_HAS_ext16u_i32) { |
| 1393 | tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); |
| 1394 | } else { |
| 1395 | tcg_gen_andi_i32(ret, arg, 0xffffu); |
| 1396 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1397 | } |
| 1398 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1399 | /* Note: we assume the two high bytes are set to zero */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1400 | static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1401 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1402 | if (TCG_TARGET_HAS_bswap16_i32) { |
| 1403 | tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg); |
| 1404 | } else { |
| 1405 | TCGv_i32 t0 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1406 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1407 | tcg_gen_ext8u_i32(t0, arg); |
| 1408 | tcg_gen_shli_i32(t0, t0, 8); |
| 1409 | tcg_gen_shri_i32(ret, arg, 8); |
| 1410 | tcg_gen_or_i32(ret, ret, t0); |
| 1411 | tcg_temp_free_i32(t0); |
| 1412 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1413 | } |
| 1414 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1415 | static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1416 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1417 | if (TCG_TARGET_HAS_bswap32_i32) { |
| 1418 | tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg); |
| 1419 | } else { |
| 1420 | TCGv_i32 t0, t1; |
| 1421 | t0 = tcg_temp_new_i32(); |
| 1422 | t1 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1423 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1424 | tcg_gen_shli_i32(t0, arg, 24); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1425 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1426 | tcg_gen_andi_i32(t1, arg, 0x0000ff00); |
| 1427 | tcg_gen_shli_i32(t1, t1, 8); |
| 1428 | tcg_gen_or_i32(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1429 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1430 | tcg_gen_shri_i32(t1, arg, 8); |
| 1431 | tcg_gen_andi_i32(t1, t1, 0x0000ff00); |
| 1432 | tcg_gen_or_i32(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1433 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1434 | tcg_gen_shri_i32(t1, arg, 24); |
| 1435 | tcg_gen_or_i32(ret, t0, t1); |
| 1436 | tcg_temp_free_i32(t0); |
| 1437 | tcg_temp_free_i32(t1); |
| 1438 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1439 | } |
| 1440 | |
| 1441 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1442 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1443 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1444 | tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1445 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1446 | } |
| 1447 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1448 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1449 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1450 | tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1451 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1452 | } |
| 1453 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1454 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1455 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1456 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1457 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1458 | } |
| 1459 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1460 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1461 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1462 | tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1463 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1464 | } |
| 1465 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1466 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1467 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1468 | tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1469 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1470 | } |
| 1471 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1472 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1473 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1474 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1475 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
| 1476 | } |
| 1477 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1478 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1479 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1480 | tcg_gen_mov_i32(ret, TCGV_LOW(arg)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1481 | } |
| 1482 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1483 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1484 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1485 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1486 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1487 | } |
| 1488 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1489 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1490 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1491 | tcg_gen_mov_i32(TCGV_LOW(ret), arg); |
| 1492 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1493 | } |
| 1494 | |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1495 | /* Note: we assume the six high bytes are set to zero */ |
| 1496 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1497 | { |
| 1498 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 1499 | tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1500 | } |
| 1501 | |
| 1502 | /* Note: we assume the four high bytes are set to zero */ |
| 1503 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1504 | { |
| 1505 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
| 1506 | tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1507 | } |
| 1508 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1509 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1510 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1511 | TCGv_i32 t0, t1; |
| 1512 | t0 = tcg_temp_new_i32(); |
| 1513 | t1 = tcg_temp_new_i32(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1514 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1515 | tcg_gen_bswap32_i32(t0, TCGV_LOW(arg)); |
| 1516 | tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1517 | tcg_gen_mov_i32(TCGV_LOW(ret), t1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1518 | tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1519 | tcg_temp_free_i32(t0); |
| 1520 | tcg_temp_free_i32(t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1521 | } |
| 1522 | #else |
| 1523 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1524 | static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1525 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1526 | if (TCG_TARGET_HAS_ext8s_i64) { |
| 1527 | tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg); |
| 1528 | } else { |
| 1529 | tcg_gen_shli_i64(ret, arg, 56); |
| 1530 | tcg_gen_sari_i64(ret, ret, 56); |
| 1531 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1532 | } |
| 1533 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1534 | static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1535 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1536 | if (TCG_TARGET_HAS_ext16s_i64) { |
| 1537 | tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg); |
| 1538 | } else { |
| 1539 | tcg_gen_shli_i64(ret, arg, 48); |
| 1540 | tcg_gen_sari_i64(ret, ret, 48); |
| 1541 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1542 | } |
| 1543 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1544 | static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1545 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1546 | if (TCG_TARGET_HAS_ext32s_i64) { |
| 1547 | tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg); |
| 1548 | } else { |
| 1549 | tcg_gen_shli_i64(ret, arg, 32); |
| 1550 | tcg_gen_sari_i64(ret, ret, 32); |
| 1551 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1552 | } |
| 1553 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1554 | static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1555 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1556 | if (TCG_TARGET_HAS_ext8u_i64) { |
| 1557 | tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); |
| 1558 | } else { |
| 1559 | tcg_gen_andi_i64(ret, arg, 0xffu); |
| 1560 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1561 | } |
| 1562 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1563 | static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1564 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1565 | if (TCG_TARGET_HAS_ext16u_i64) { |
| 1566 | tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); |
| 1567 | } else { |
| 1568 | tcg_gen_andi_i64(ret, arg, 0xffffu); |
| 1569 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1570 | } |
| 1571 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1572 | static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1573 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1574 | if (TCG_TARGET_HAS_ext32u_i64) { |
| 1575 | tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); |
| 1576 | } else { |
| 1577 | tcg_gen_andi_i64(ret, arg, 0xffffffffu); |
| 1578 | } |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1579 | } |
| 1580 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1581 | /* Note: we assume the target supports move between 32 and 64 bit |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 1582 | registers. This will probably break MIPS64 targets. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1583 | static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1584 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1585 | tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1586 | } |
| 1587 | |
| 1588 | /* Note: we assume the target supports move between 32 and 64 bit |
| 1589 | registers */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1590 | static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1591 | { |
Aurelien Jarno | cfc8698 | 2009-09-30 23:09:35 +0200 | [diff] [blame] | 1592 | tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1593 | } |
| 1594 | |
| 1595 | /* Note: we assume the target supports move between 32 and 64 bit |
| 1596 | registers */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1597 | static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1598 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1599 | tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1600 | } |
| 1601 | |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1602 | /* Note: we assume the six high bytes are set to zero */ |
| 1603 | static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1604 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1605 | if (TCG_TARGET_HAS_bswap16_i64) { |
| 1606 | tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg); |
| 1607 | } else { |
| 1608 | TCGv_i64 t0 = tcg_temp_new_i64(); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1609 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1610 | tcg_gen_ext8u_i64(t0, arg); |
| 1611 | tcg_gen_shli_i64(t0, t0, 8); |
| 1612 | tcg_gen_shri_i64(ret, arg, 8); |
| 1613 | tcg_gen_or_i64(ret, ret, t0); |
| 1614 | tcg_temp_free_i64(t0); |
| 1615 | } |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1616 | } |
| 1617 | |
| 1618 | /* Note: we assume the four high bytes are set to zero */ |
| 1619 | static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg) |
| 1620 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1621 | if (TCG_TARGET_HAS_bswap32_i64) { |
| 1622 | tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg); |
| 1623 | } else { |
| 1624 | TCGv_i64 t0, t1; |
| 1625 | t0 = tcg_temp_new_i64(); |
| 1626 | t1 = tcg_temp_new_i64(); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1627 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1628 | tcg_gen_shli_i64(t0, arg, 24); |
| 1629 | tcg_gen_ext32u_i64(t0, t0); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1630 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1631 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
| 1632 | tcg_gen_shli_i64(t1, t1, 8); |
| 1633 | tcg_gen_or_i64(t0, t0, t1); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1634 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1635 | tcg_gen_shri_i64(t1, arg, 8); |
| 1636 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); |
| 1637 | tcg_gen_or_i64(t0, t0, t1); |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1638 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1639 | tcg_gen_shri_i64(t1, arg, 24); |
| 1640 | tcg_gen_or_i64(ret, t0, t1); |
| 1641 | tcg_temp_free_i64(t0); |
| 1642 | tcg_temp_free_i64(t1); |
| 1643 | } |
aurel32 | 9a5c57f | 2009-03-13 09:35:12 +0000 | [diff] [blame] | 1644 | } |
| 1645 | |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1646 | static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1647 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1648 | if (TCG_TARGET_HAS_bswap64_i64) { |
| 1649 | tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg); |
| 1650 | } else { |
| 1651 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1652 | TCGv_i64 t1 = tcg_temp_new_i64(); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1653 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1654 | tcg_gen_shli_i64(t0, arg, 56); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1655 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1656 | tcg_gen_andi_i64(t1, arg, 0x0000ff00); |
| 1657 | tcg_gen_shli_i64(t1, t1, 40); |
| 1658 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1659 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1660 | tcg_gen_andi_i64(t1, arg, 0x00ff0000); |
| 1661 | tcg_gen_shli_i64(t1, t1, 24); |
| 1662 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1663 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1664 | tcg_gen_andi_i64(t1, arg, 0xff000000); |
| 1665 | tcg_gen_shli_i64(t1, t1, 8); |
| 1666 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1667 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1668 | tcg_gen_shri_i64(t1, arg, 8); |
| 1669 | tcg_gen_andi_i64(t1, t1, 0xff000000); |
| 1670 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1671 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1672 | tcg_gen_shri_i64(t1, arg, 24); |
| 1673 | tcg_gen_andi_i64(t1, t1, 0x00ff0000); |
| 1674 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1675 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1676 | tcg_gen_shri_i64(t1, arg, 40); |
| 1677 | tcg_gen_andi_i64(t1, t1, 0x0000ff00); |
| 1678 | tcg_gen_or_i64(t0, t0, t1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1679 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1680 | tcg_gen_shri_i64(t1, arg, 56); |
| 1681 | tcg_gen_or_i64(ret, t0, t1); |
| 1682 | tcg_temp_free_i64(t0); |
| 1683 | tcg_temp_free_i64(t1); |
| 1684 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1685 | } |
| 1686 | |
| 1687 | #endif |
| 1688 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1689 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1690 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1691 | if (TCG_TARGET_HAS_neg_i32) { |
| 1692 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
| 1693 | } else { |
| 1694 | TCGv_i32 t0 = tcg_const_i32(0); |
| 1695 | tcg_gen_sub_i32(ret, t0, arg); |
| 1696 | tcg_temp_free_i32(t0); |
| 1697 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1698 | } |
| 1699 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1700 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1701 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1702 | if (TCG_TARGET_HAS_neg_i64) { |
| 1703 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
| 1704 | } else { |
| 1705 | TCGv_i64 t0 = tcg_const_i64(0); |
| 1706 | tcg_gen_sub_i64(ret, t0, arg); |
| 1707 | tcg_temp_free_i64(t0); |
| 1708 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1709 | } |
| 1710 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1711 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1712 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1713 | if (TCG_TARGET_HAS_not_i32) { |
| 1714 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
| 1715 | } else { |
| 1716 | tcg_gen_xori_i32(ret, arg, -1); |
| 1717 | } |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1718 | } |
| 1719 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1720 | static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1721 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1722 | #if TCG_TARGET_REG_BITS == 64 |
| 1723 | if (TCG_TARGET_HAS_not_i64) { |
| 1724 | tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg); |
| 1725 | } else { |
| 1726 | tcg_gen_xori_i64(ret, arg, -1); |
| 1727 | } |
| 1728 | #else |
Richard Henderson | a10f9f4 | 2010-03-19 12:44:47 -0700 | [diff] [blame] | 1729 | tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg)); |
| 1730 | tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
aurel32 | d260428 | 2009-03-09 22:35:13 +0000 | [diff] [blame] | 1731 | #endif |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1732 | } |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1733 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1734 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1735 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1736 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1737 | } |
| 1738 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1739 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1740 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1741 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1742 | tcg_gen_discard_i32(TCGV_LOW(arg)); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1743 | tcg_gen_discard_i32(TCGV_HIGH(arg)); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1744 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1745 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1746 | #endif |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1747 | } |
bellard | 5ff9d6a | 2008-02-04 00:37:54 +0000 | [diff] [blame] | 1748 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1749 | static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 1750 | { |
| 1751 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1752 | tcg_gen_mov_i32(TCGV_LOW(dest), low); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 1753 | tcg_gen_mov_i32(TCGV_HIGH(dest), high); |
| 1754 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1755 | TCGv_i64 tmp = tcg_temp_new_i64(); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 1756 | /* This extension is only needed for type correctness. |
| 1757 | We may be able to do better given target specific information. */ |
| 1758 | tcg_gen_extu_i32_i64(tmp, high); |
| 1759 | tcg_gen_shli_i64(tmp, tmp, 32); |
| 1760 | tcg_gen_extu_i32_i64(dest, low); |
| 1761 | tcg_gen_or_i64(dest, dest, tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1762 | tcg_temp_free_i64(tmp); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 1763 | #endif |
| 1764 | } |
| 1765 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1766 | static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1767 | { |
| 1768 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1769 | tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1770 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1771 | TCGv_i64 tmp = tcg_temp_new_i64(); |
pbrook | 88422e2 | 2008-09-23 22:31:10 +0000 | [diff] [blame] | 1772 | tcg_gen_ext32u_i64(dest, low); |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1773 | tcg_gen_shli_i64(tmp, high, 32); |
pbrook | 88422e2 | 2008-09-23 22:31:10 +0000 | [diff] [blame] | 1774 | tcg_gen_or_i64(dest, dest, tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1775 | tcg_temp_free_i64(tmp); |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1776 | #endif |
| 1777 | } |
| 1778 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1779 | static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1780 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1781 | if (TCG_TARGET_HAS_andc_i32) { |
| 1782 | tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); |
| 1783 | } else { |
| 1784 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 1785 | tcg_gen_not_i32(t0, arg2); |
| 1786 | tcg_gen_and_i32(ret, arg1, t0); |
| 1787 | tcg_temp_free_i32(t0); |
| 1788 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1789 | } |
| 1790 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1791 | static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1792 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1793 | #if TCG_TARGET_REG_BITS == 64 |
| 1794 | if (TCG_TARGET_HAS_andc_i64) { |
| 1795 | tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); |
| 1796 | } else { |
| 1797 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1798 | tcg_gen_not_i64(t0, arg2); |
| 1799 | tcg_gen_and_i64(ret, arg1, t0); |
| 1800 | tcg_temp_free_i64(t0); |
| 1801 | } |
| 1802 | #else |
Richard Henderson | 241cbed | 2010-02-16 14:10:13 -0800 | [diff] [blame] | 1803 | tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1804 | tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 241cbed | 2010-02-16 14:10:13 -0800 | [diff] [blame] | 1805 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1806 | } |
| 1807 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1808 | static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1809 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1810 | if (TCG_TARGET_HAS_eqv_i32) { |
| 1811 | tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); |
| 1812 | } else { |
| 1813 | tcg_gen_xor_i32(ret, arg1, arg2); |
| 1814 | tcg_gen_not_i32(ret, ret); |
| 1815 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1816 | } |
| 1817 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1818 | static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1819 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1820 | #if TCG_TARGET_REG_BITS == 64 |
| 1821 | if (TCG_TARGET_HAS_eqv_i64) { |
| 1822 | tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); |
| 1823 | } else { |
| 1824 | tcg_gen_xor_i64(ret, arg1, arg2); |
| 1825 | tcg_gen_not_i64(ret, ret); |
| 1826 | } |
| 1827 | #else |
Richard Henderson | 8d625cf | 2010-03-19 13:02:02 -0700 | [diff] [blame] | 1828 | tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1829 | tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 8d625cf | 2010-03-19 13:02:02 -0700 | [diff] [blame] | 1830 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1831 | } |
| 1832 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1833 | static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1834 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1835 | if (TCG_TARGET_HAS_nand_i32) { |
| 1836 | tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); |
| 1837 | } else { |
| 1838 | tcg_gen_and_i32(ret, arg1, arg2); |
| 1839 | tcg_gen_not_i32(ret, ret); |
| 1840 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1841 | } |
| 1842 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1843 | static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1844 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1845 | #if TCG_TARGET_REG_BITS == 64 |
| 1846 | if (TCG_TARGET_HAS_nand_i64) { |
| 1847 | tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); |
| 1848 | } else { |
| 1849 | tcg_gen_and_i64(ret, arg1, arg2); |
| 1850 | tcg_gen_not_i64(ret, ret); |
| 1851 | } |
| 1852 | #else |
Richard Henderson | 9940a96 | 2010-03-19 13:03:58 -0700 | [diff] [blame] | 1853 | tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1854 | tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 9940a96 | 2010-03-19 13:03:58 -0700 | [diff] [blame] | 1855 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1856 | } |
| 1857 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1858 | static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1859 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1860 | if (TCG_TARGET_HAS_nor_i32) { |
| 1861 | tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2); |
| 1862 | } else { |
| 1863 | tcg_gen_or_i32(ret, arg1, arg2); |
| 1864 | tcg_gen_not_i32(ret, ret); |
| 1865 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1866 | } |
| 1867 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1868 | static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1869 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1870 | #if TCG_TARGET_REG_BITS == 64 |
| 1871 | if (TCG_TARGET_HAS_nor_i64) { |
| 1872 | tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2); |
| 1873 | } else { |
| 1874 | tcg_gen_or_i64(ret, arg1, arg2); |
| 1875 | tcg_gen_not_i64(ret, ret); |
| 1876 | } |
| 1877 | #else |
Richard Henderson | 32d98fb | 2010-03-19 13:08:56 -0700 | [diff] [blame] | 1878 | tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1879 | tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 32d98fb | 2010-03-19 13:08:56 -0700 | [diff] [blame] | 1880 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1881 | } |
| 1882 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1883 | static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1884 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1885 | if (TCG_TARGET_HAS_orc_i32) { |
| 1886 | tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2); |
| 1887 | } else { |
| 1888 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 1889 | tcg_gen_not_i32(t0, arg2); |
| 1890 | tcg_gen_or_i32(ret, arg1, t0); |
| 1891 | tcg_temp_free_i32(t0); |
| 1892 | } |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1893 | } |
| 1894 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1895 | static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1896 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1897 | #if TCG_TARGET_REG_BITS == 64 |
| 1898 | if (TCG_TARGET_HAS_orc_i64) { |
| 1899 | tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2); |
| 1900 | } else { |
| 1901 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 1902 | tcg_gen_not_i64(t0, arg2); |
| 1903 | tcg_gen_or_i64(ret, arg1, t0); |
| 1904 | tcg_temp_free_i64(t0); |
| 1905 | } |
| 1906 | #else |
Richard Henderson | 791d126 | 2010-02-16 14:15:28 -0800 | [diff] [blame] | 1907 | tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); |
| 1908 | tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
Richard Henderson | 791d126 | 2010-02-16 14:15:28 -0800 | [diff] [blame] | 1909 | #endif |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1910 | } |
| 1911 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1912 | static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1913 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1914 | if (TCG_TARGET_HAS_rot_i32) { |
| 1915 | tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); |
| 1916 | } else { |
| 1917 | TCGv_i32 t0, t1; |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1918 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1919 | t0 = tcg_temp_new_i32(); |
| 1920 | t1 = tcg_temp_new_i32(); |
| 1921 | tcg_gen_shl_i32(t0, arg1, arg2); |
| 1922 | tcg_gen_subfi_i32(t1, 32, arg2); |
| 1923 | tcg_gen_shr_i32(t1, arg1, t1); |
| 1924 | tcg_gen_or_i32(ret, t0, t1); |
| 1925 | tcg_temp_free_i32(t0); |
| 1926 | tcg_temp_free_i32(t1); |
| 1927 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1928 | } |
| 1929 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1930 | static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1931 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1932 | if (TCG_TARGET_HAS_rot_i64) { |
| 1933 | tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); |
| 1934 | } else { |
| 1935 | TCGv_i64 t0, t1; |
| 1936 | t0 = tcg_temp_new_i64(); |
| 1937 | t1 = tcg_temp_new_i64(); |
| 1938 | tcg_gen_shl_i64(t0, arg1, arg2); |
| 1939 | tcg_gen_subfi_i64(t1, 64, arg2); |
| 1940 | tcg_gen_shr_i64(t1, arg1, t1); |
| 1941 | tcg_gen_or_i64(ret, t0, t1); |
| 1942 | tcg_temp_free_i64(t0); |
| 1943 | tcg_temp_free_i64(t1); |
| 1944 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1945 | } |
| 1946 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1947 | static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1948 | { |
| 1949 | /* some cases can be optimized here */ |
| 1950 | if (arg2 == 0) { |
| 1951 | tcg_gen_mov_i32(ret, arg1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1952 | } else if (TCG_TARGET_HAS_rot_i32) { |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1953 | TCGv_i32 t0 = tcg_const_i32(arg2); |
| 1954 | tcg_gen_rotl_i32(ret, arg1, t0); |
| 1955 | tcg_temp_free_i32(t0); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1956 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1957 | TCGv_i32 t0, t1; |
| 1958 | t0 = tcg_temp_new_i32(); |
| 1959 | t1 = tcg_temp_new_i32(); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1960 | tcg_gen_shli_i32(t0, arg1, arg2); |
| 1961 | tcg_gen_shri_i32(t1, arg1, 32 - arg2); |
| 1962 | tcg_gen_or_i32(ret, t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1963 | tcg_temp_free_i32(t0); |
| 1964 | tcg_temp_free_i32(t1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1965 | } |
| 1966 | } |
| 1967 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1968 | static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1969 | { |
| 1970 | /* some cases can be optimized here */ |
| 1971 | if (arg2 == 0) { |
| 1972 | tcg_gen_mov_i64(ret, arg1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1973 | } else if (TCG_TARGET_HAS_rot_i64) { |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1974 | TCGv_i64 t0 = tcg_const_i64(arg2); |
| 1975 | tcg_gen_rotl_i64(ret, arg1, t0); |
| 1976 | tcg_temp_free_i64(t0); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1977 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1978 | TCGv_i64 t0, t1; |
| 1979 | t0 = tcg_temp_new_i64(); |
| 1980 | t1 = tcg_temp_new_i64(); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1981 | tcg_gen_shli_i64(t0, arg1, arg2); |
| 1982 | tcg_gen_shri_i64(t1, arg1, 64 - arg2); |
| 1983 | tcg_gen_or_i64(ret, t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1984 | tcg_temp_free_i64(t0); |
| 1985 | tcg_temp_free_i64(t1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1986 | } |
| 1987 | } |
| 1988 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1989 | static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1990 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1991 | if (TCG_TARGET_HAS_rot_i32) { |
| 1992 | tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); |
| 1993 | } else { |
| 1994 | TCGv_i32 t0, t1; |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1995 | |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 1996 | t0 = tcg_temp_new_i32(); |
| 1997 | t1 = tcg_temp_new_i32(); |
| 1998 | tcg_gen_shr_i32(t0, arg1, arg2); |
| 1999 | tcg_gen_subfi_i32(t1, 32, arg2); |
| 2000 | tcg_gen_shl_i32(t1, arg1, t1); |
| 2001 | tcg_gen_or_i32(ret, t0, t1); |
| 2002 | tcg_temp_free_i32(t0); |
| 2003 | tcg_temp_free_i32(t1); |
| 2004 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2005 | } |
| 2006 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2007 | static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2008 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2009 | if (TCG_TARGET_HAS_rot_i64) { |
| 2010 | tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); |
| 2011 | } else { |
| 2012 | TCGv_i64 t0, t1; |
| 2013 | t0 = tcg_temp_new_i64(); |
| 2014 | t1 = tcg_temp_new_i64(); |
| 2015 | tcg_gen_shr_i64(t0, arg1, arg2); |
| 2016 | tcg_gen_subfi_i64(t1, 64, arg2); |
| 2017 | tcg_gen_shl_i64(t1, arg1, t1); |
| 2018 | tcg_gen_or_i64(ret, t0, t1); |
| 2019 | tcg_temp_free_i64(t0); |
| 2020 | tcg_temp_free_i64(t1); |
| 2021 | } |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2022 | } |
| 2023 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2024 | static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2025 | { |
| 2026 | /* some cases can be optimized here */ |
| 2027 | if (arg2 == 0) { |
| 2028 | tcg_gen_mov_i32(ret, arg1); |
| 2029 | } else { |
| 2030 | tcg_gen_rotli_i32(ret, arg1, 32 - arg2); |
| 2031 | } |
| 2032 | } |
| 2033 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2034 | static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2035 | { |
| 2036 | /* some cases can be optimized here */ |
| 2037 | if (arg2 == 0) { |
pbrook | de3526b | 2008-11-03 13:30:50 +0000 | [diff] [blame] | 2038 | tcg_gen_mov_i64(ret, arg1); |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2039 | } else { |
| 2040 | tcg_gen_rotli_i64(ret, arg1, 64 - arg2); |
| 2041 | } |
| 2042 | } |
| 2043 | |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2044 | static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, |
Richard Henderson | 0756e71 | 2011-11-01 15:06:43 -0700 | [diff] [blame] | 2045 | TCGv_i32 arg2, unsigned int ofs, |
| 2046 | unsigned int len) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2047 | { |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2048 | uint32_t mask; |
| 2049 | TCGv_i32 t1; |
| 2050 | |
| 2051 | if (ofs == 0 && len == 32) { |
| 2052 | tcg_gen_mov_i32(ret, arg2); |
| 2053 | return; |
| 2054 | } |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 2055 | if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2056 | tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2057 | return; |
| 2058 | } |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2059 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2060 | mask = (1u << len) - 1; |
| 2061 | t1 = tcg_temp_new_i32(); |
| 2062 | |
| 2063 | if (ofs + len < 32) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2064 | tcg_gen_andi_i32(t1, arg2, mask); |
| 2065 | tcg_gen_shli_i32(t1, t1, ofs); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2066 | } else { |
| 2067 | tcg_gen_shli_i32(t1, arg2, ofs); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2068 | } |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2069 | tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); |
| 2070 | tcg_gen_or_i32(ret, ret, t1); |
| 2071 | |
| 2072 | tcg_temp_free_i32(t1); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2073 | } |
| 2074 | |
| 2075 | static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, |
Richard Henderson | 0756e71 | 2011-11-01 15:06:43 -0700 | [diff] [blame] | 2076 | TCGv_i64 arg2, unsigned int ofs, |
| 2077 | unsigned int len) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2078 | { |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2079 | uint64_t mask; |
| 2080 | TCGv_i64 t1; |
| 2081 | |
| 2082 | if (ofs == 0 && len == 64) { |
| 2083 | tcg_gen_mov_i64(ret, arg2); |
| 2084 | return; |
| 2085 | } |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 2086 | if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2087 | tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2088 | return; |
| 2089 | } |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2090 | |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2091 | #if TCG_TARGET_REG_BITS == 32 |
| 2092 | if (ofs >= 32) { |
Richard Henderson | 2f98c9d | 2011-11-01 15:06:42 -0700 | [diff] [blame] | 2093 | tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2094 | tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), |
| 2095 | TCGV_LOW(arg2), ofs - 32, len); |
| 2096 | return; |
| 2097 | } |
| 2098 | if (ofs + len <= 32) { |
| 2099 | tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), |
| 2100 | TCGV_LOW(arg2), ofs, len); |
Richard Henderson | 2f98c9d | 2011-11-01 15:06:42 -0700 | [diff] [blame] | 2101 | tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2102 | return; |
| 2103 | } |
| 2104 | #endif |
| 2105 | |
| 2106 | mask = (1ull << len) - 1; |
| 2107 | t1 = tcg_temp_new_i64(); |
| 2108 | |
| 2109 | if (ofs + len < 64) { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2110 | tcg_gen_andi_i64(t1, arg2, mask); |
| 2111 | tcg_gen_shli_i64(t1, t1, ofs); |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2112 | } else { |
| 2113 | tcg_gen_shli_i64(t1, arg2, ofs); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 2114 | } |
Richard Henderson | df07277 | 2011-10-27 14:15:00 -0700 | [diff] [blame] | 2115 | tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); |
| 2116 | tcg_gen_or_i64(ret, ret, t1); |
| 2117 | |
| 2118 | tcg_temp_free_i64(t1); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2119 | } |
| 2120 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2121 | /***************************************/ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2122 | /* QEMU specific operations. Their type depend on the QEMU CPU |
| 2123 | type. */ |
| 2124 | #ifndef TARGET_LONG_BITS |
| 2125 | #error must include QEMU headers |
| 2126 | #endif |
| 2127 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2128 | #if TARGET_LONG_BITS == 32 |
| 2129 | #define TCGv TCGv_i32 |
| 2130 | #define tcg_temp_new() tcg_temp_new_i32() |
| 2131 | #define tcg_global_reg_new tcg_global_reg_new_i32 |
| 2132 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 2133 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2134 | #define tcg_temp_free tcg_temp_free_i32 |
| 2135 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 |
| 2136 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 |
| 2137 | #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 2138 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2139 | #else |
| 2140 | #define TCGv TCGv_i64 |
| 2141 | #define tcg_temp_new() tcg_temp_new_i64() |
| 2142 | #define tcg_global_reg_new tcg_global_reg_new_i64 |
| 2143 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 2144 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2145 | #define tcg_temp_free tcg_temp_free_i64 |
| 2146 | #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 |
| 2147 | #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 |
| 2148 | #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) |
aurel32 | fe75bcf | 2009-03-10 08:57:16 +0000 | [diff] [blame] | 2149 | #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2150 | #endif |
| 2151 | |
bellard | 7e4597d | 2008-05-22 16:56:05 +0000 | [diff] [blame] | 2152 | /* debug info: write the PC of the corresponding QEMU CPU instruction */ |
| 2153 | static inline void tcg_gen_debug_insn_start(uint64_t pc) |
| 2154 | { |
| 2155 | /* XXX: must really use a 32 bit size for TCGArg in all cases */ |
| 2156 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 2157 | tcg_gen_op2ii(INDEX_op_debug_insn_start, |
| 2158 | (uint32_t)(pc), (uint32_t)(pc >> 32)); |
bellard | 7e4597d | 2008-05-22 16:56:05 +0000 | [diff] [blame] | 2159 | #else |
| 2160 | tcg_gen_op1i(INDEX_op_debug_insn_start, pc); |
| 2161 | #endif |
| 2162 | } |
| 2163 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2164 | static inline void tcg_gen_exit_tb(tcg_target_long val) |
| 2165 | { |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2166 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2167 | } |
| 2168 | |
| 2169 | static inline void tcg_gen_goto_tb(int idx) |
| 2170 | { |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2171 | tcg_gen_op1i(INDEX_op_goto_tb, idx); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2172 | } |
| 2173 | |
| 2174 | #if TCG_TARGET_REG_BITS == 32 |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2175 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2176 | { |
| 2177 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2178 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2179 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2180 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2181 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2182 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2183 | #endif |
| 2184 | } |
| 2185 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2186 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2187 | { |
| 2188 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2189 | tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2190 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2191 | tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2192 | TCGV_HIGH(addr), mem_index); |
| 2193 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2194 | #endif |
| 2195 | } |
| 2196 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2197 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2198 | { |
| 2199 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2200 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2201 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2202 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2203 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2204 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2205 | #endif |
| 2206 | } |
| 2207 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2208 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2209 | { |
| 2210 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2211 | tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2212 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2213 | tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr), |
| 2214 | TCGV_HIGH(addr), mem_index); |
| 2215 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2216 | #endif |
| 2217 | } |
| 2218 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2219 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2220 | { |
| 2221 | #if TARGET_LONG_BITS == 32 |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2222 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2223 | #else |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2224 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2225 | TCGV_HIGH(addr), mem_index); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2226 | tcg_gen_movi_i32(TCGV_HIGH(ret), 0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2227 | #endif |
| 2228 | } |
| 2229 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2230 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2231 | { |
| 2232 | #if TARGET_LONG_BITS == 32 |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2233 | tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2234 | #else |
Richard Henderson | 86feb1c | 2010-03-19 12:00:26 -0700 | [diff] [blame] | 2235 | tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr), |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2236 | TCGV_HIGH(addr), mem_index); |
| 2237 | tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2238 | #endif |
| 2239 | } |
| 2240 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2241 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2242 | { |
| 2243 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2244 | tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2245 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2246 | tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), |
| 2247 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2248 | #endif |
| 2249 | } |
| 2250 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2251 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2252 | { |
| 2253 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2254 | tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2255 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2256 | tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2257 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2258 | #endif |
| 2259 | } |
| 2260 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2261 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2262 | { |
| 2263 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2264 | tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2265 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2266 | tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2267 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2268 | #endif |
| 2269 | } |
| 2270 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2271 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2272 | { |
| 2273 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2274 | tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2275 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2276 | tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr), |
| 2277 | TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2278 | #endif |
| 2279 | } |
| 2280 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2281 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2282 | { |
| 2283 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2284 | tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr, |
| 2285 | mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2286 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2287 | tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), |
| 2288 | TCGV_LOW(addr), TCGV_HIGH(addr), mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2289 | #endif |
| 2290 | } |
| 2291 | |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2292 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 2293 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2294 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2295 | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 2296 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2297 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2298 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2299 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2300 | } |
| 2301 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2302 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2303 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2304 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2305 | } |
| 2306 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2307 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2308 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2309 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2310 | } |
| 2311 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2312 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2313 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2314 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2315 | } |
| 2316 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2317 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2318 | { |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2319 | #if TARGET_LONG_BITS == 32 |
| 2320 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
| 2321 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2322 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2323 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2324 | } |
| 2325 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2326 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2327 | { |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2328 | #if TARGET_LONG_BITS == 32 |
| 2329 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index); |
| 2330 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2331 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
Richard Henderson | 3e1dbad | 2010-05-03 16:30:48 -0700 | [diff] [blame] | 2332 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2333 | } |
| 2334 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2335 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2336 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2337 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2338 | } |
| 2339 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2340 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2341 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2342 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2343 | } |
| 2344 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2345 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2346 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2347 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2348 | } |
| 2349 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 2350 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2351 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2352 | tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2353 | } |
| 2354 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2355 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2356 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2357 | tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2358 | } |
| 2359 | |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2360 | #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 2361 | #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2362 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 2363 | #endif /* TCG_TARGET_REG_BITS != 32 */ |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2364 | |
| 2365 | #if TARGET_LONG_BITS == 64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2366 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
| 2367 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
| 2368 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
| 2369 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
| 2370 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
| 2371 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
| 2372 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
| 2373 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
| 2374 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
| 2375 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
| 2376 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
| 2377 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
| 2378 | #define tcg_gen_st_tl tcg_gen_st_i64 |
| 2379 | #define tcg_gen_add_tl tcg_gen_add_i64 |
| 2380 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
| 2381 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 2382 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
pbrook | 10460c8 | 2008-11-02 13:26:16 +0000 | [diff] [blame] | 2383 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2384 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
| 2385 | #define tcg_gen_and_tl tcg_gen_and_i64 |
| 2386 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
| 2387 | #define tcg_gen_or_tl tcg_gen_or_i64 |
| 2388 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
| 2389 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
| 2390 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2391 | #define tcg_gen_not_tl tcg_gen_not_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2392 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
| 2393 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
| 2394 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
| 2395 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
| 2396 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
| 2397 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 2398 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 2399 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 2400 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 2401 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 2402 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
| 2403 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 2404 | #define tcg_gen_div_tl tcg_gen_div_i64 |
| 2405 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 2406 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
| 2407 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 2408 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 2409 | #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32 |
| 2410 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
| 2411 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
| 2412 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
| 2413 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
| 2414 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2415 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
| 2416 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
| 2417 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
| 2418 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
| 2419 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
| 2420 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 2421 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
| 2422 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
| 2423 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 2424 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 2425 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
| 2426 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
| 2427 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
| 2428 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
| 2429 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2430 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
| 2431 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
| 2432 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
| 2433 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2434 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 2435 | #define tcg_const_tl tcg_const_i64 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 2436 | #define tcg_const_local_tl tcg_const_local_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2437 | #else |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2438 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
| 2439 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
| 2440 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
| 2441 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
| 2442 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
| 2443 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
| 2444 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
| 2445 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
| 2446 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
| 2447 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
| 2448 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
| 2449 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
| 2450 | #define tcg_gen_st_tl tcg_gen_st_i32 |
| 2451 | #define tcg_gen_add_tl tcg_gen_add_i32 |
| 2452 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
| 2453 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 2454 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 2455 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2456 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
| 2457 | #define tcg_gen_and_tl tcg_gen_and_i32 |
| 2458 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
| 2459 | #define tcg_gen_or_tl tcg_gen_or_i32 |
| 2460 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
| 2461 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
| 2462 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2463 | #define tcg_gen_not_tl tcg_gen_not_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2464 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
| 2465 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
| 2466 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
| 2467 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
| 2468 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
| 2469 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 2470 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 2471 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 2472 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 2473 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 2474 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
| 2475 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 2476 | #define tcg_gen_div_tl tcg_gen_div_i32 |
| 2477 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 2478 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
| 2479 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 2480 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 2481 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
| 2482 | #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32 |
| 2483 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
| 2484 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
| 2485 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
| 2486 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 2487 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
| 2488 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
| 2489 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
| 2490 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
| 2491 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
| 2492 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 2493 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
| 2494 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 2495 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 2496 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
| 2497 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
| 2498 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
| 2499 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
| 2500 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 2501 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
| 2502 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
| 2503 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
| 2504 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 2505 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 2506 | #define tcg_const_tl tcg_const_i32 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 2507 | #define tcg_const_local_tl tcg_const_local_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 2508 | #endif |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2509 | |
| 2510 | #if TCG_TARGET_REG_BITS == 32 |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2511 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \ |
| 2512 | TCGV_PTR_TO_NAT(A), \ |
| 2513 | TCGV_PTR_TO_NAT(B)) |
| 2514 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \ |
| 2515 | TCGV_PTR_TO_NAT(A), (B)) |
| 2516 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2517 | #else /* TCG_TARGET_REG_BITS == 32 */ |
Peter Maydell | ebecf36 | 2011-05-27 13:12:13 +0100 | [diff] [blame] | 2518 | #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \ |
| 2519 | TCGV_PTR_TO_NAT(A), \ |
| 2520 | TCGV_PTR_TO_NAT(B)) |
| 2521 | #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \ |
| 2522 | TCGV_PTR_TO_NAT(A), (B)) |
| 2523 | #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 2524 | #endif /* TCG_TARGET_REG_BITS != 32 */ |