ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 2 | * Generic ARM Programmable Interrupt Controller support. |
| 3 | * |
| 4 | * Copyright (c) 2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the LGPL |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 10 | #include "hw.h" |
| 11 | #include "arm-misc.h" |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 12 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 13 | /* Input 0 is IRQ and input 1 is FIQ. */ |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 14 | static void arm_pic_cpu_handler(void *opaque, int irq, int level) |
| 15 | { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 16 | CPUState *env = (CPUState *)opaque; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 17 | switch (irq) { |
| 18 | case ARM_PIC_CPU_IRQ: |
| 19 | if (level) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 20 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 21 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 22 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 23 | break; |
| 24 | case ARM_PIC_CPU_FIQ: |
| 25 | if (level) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 26 | cpu_interrupt(env, CPU_INTERRUPT_FIQ); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 27 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 28 | cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 29 | break; |
| 30 | default: |
Andreas Färber | 47601f2 | 2011-10-10 01:27:01 +0200 | [diff] [blame] | 31 | hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 32 | } |
| 33 | } |
| 34 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 35 | qemu_irq *arm_pic_init_cpu(CPUState *env) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 36 | { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 37 | return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 38 | } |