Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 1 | /* |
| 2 | * ARM GICv3 support - common bits of emulated and KVM kernel model |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited |
| 5 | * Copyright (c) 2015 Huawei. |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 6 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 7 | * Written by Peter Maydell |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 8 | * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation, either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along |
| 21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 22 | */ |
| 23 | |
Peter Maydell | 8ef94f0 | 2016-01-26 18:17:05 +0000 | [diff] [blame] | 24 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 25 | #include "qapi/error.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 26 | #include "qemu/module.h" |
Philippe Mathieu-Daudé | 0c40daf | 2023-04-05 13:48:26 +0200 | [diff] [blame] | 27 | #include "qemu/error-report.h" |
Markus Armbruster | 2e5b09f | 2019-07-09 17:20:52 +0200 | [diff] [blame] | 28 | #include "hw/core/cpu.h" |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 29 | #include "hw/intc/arm_gicv3_common.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 30 | #include "hw/qdev-properties.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 31 | #include "migration/vmstate.h" |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 32 | #include "gicv3_internal.h" |
| 33 | #include "hw/arm/linux-boot-if.h" |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 34 | #include "sysemu/kvm.h" |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 35 | |
Peter Maydell | 341823c | 2018-08-06 13:34:45 +0100 | [diff] [blame] | 36 | |
| 37 | static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) |
| 38 | { |
| 39 | if (cs->gicd_no_migration_shift_bug) { |
| 40 | return; |
| 41 | } |
| 42 | |
| 43 | /* Older versions of QEMU had a bug in the handling of state save/restore |
| 44 | * to the KVM GICv3: they got the offset in the bitmap arrays wrong, |
| 45 | * so that instead of the data for external interrupts 32 and up |
| 46 | * starting at bit position 32 in the bitmap, it started at bit |
| 47 | * position 64. If we're receiving data from a QEMU with that bug, |
| 48 | * we must move the data down into the right place. |
| 49 | */ |
| 50 | memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, |
| 51 | sizeof(cs->group) - GIC_INTERNAL / 8); |
| 52 | memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, |
| 53 | sizeof(cs->grpmod) - GIC_INTERNAL / 8); |
| 54 | memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8, |
| 55 | sizeof(cs->enabled) - GIC_INTERNAL / 8); |
| 56 | memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8, |
| 57 | sizeof(cs->pending) - GIC_INTERNAL / 8); |
| 58 | memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8, |
| 59 | sizeof(cs->active) - GIC_INTERNAL / 8); |
| 60 | memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8, |
| 61 | sizeof(cs->edge_trigger) - GIC_INTERNAL / 8); |
| 62 | |
| 63 | /* |
| 64 | * While this new version QEMU doesn't have this kind of bug as we fix it, |
| 65 | * so it needs to set the flag to true to indicate that and it's necessary |
| 66 | * for next migration to work from this new version QEMU. |
| 67 | */ |
| 68 | cs->gicd_no_migration_shift_bug = true; |
| 69 | } |
| 70 | |
Dr. David Alan Gilbert | 44b1ff3 | 2017-09-25 12:29:12 +0100 | [diff] [blame] | 71 | static int gicv3_pre_save(void *opaque) |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 72 | { |
| 73 | GICv3State *s = (GICv3State *)opaque; |
| 74 | ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); |
| 75 | |
| 76 | if (c->pre_save) { |
| 77 | c->pre_save(s); |
| 78 | } |
Dr. David Alan Gilbert | 44b1ff3 | 2017-09-25 12:29:12 +0100 | [diff] [blame] | 79 | |
| 80 | return 0; |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 81 | } |
| 82 | |
| 83 | static int gicv3_post_load(void *opaque, int version_id) |
| 84 | { |
| 85 | GICv3State *s = (GICv3State *)opaque; |
| 86 | ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s); |
| 87 | |
Peter Maydell | 341823c | 2018-08-06 13:34:45 +0100 | [diff] [blame] | 88 | gicv3_gicd_no_migration_shift_bug_post_load(s); |
| 89 | |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 90 | if (c->post_load) { |
| 91 | c->post_load(s); |
| 92 | } |
| 93 | return 0; |
| 94 | } |
| 95 | |
Peter Maydell | 4eb833b | 2017-01-20 11:15:09 +0000 | [diff] [blame] | 96 | static bool virt_state_needed(void *opaque) |
| 97 | { |
| 98 | GICv3CPUState *cs = opaque; |
| 99 | |
| 100 | return cs->num_list_regs != 0; |
| 101 | } |
| 102 | |
| 103 | static const VMStateDescription vmstate_gicv3_cpu_virt = { |
| 104 | .name = "arm_gicv3_cpu/virt", |
| 105 | .version_id = 1, |
| 106 | .minimum_version_id = 1, |
| 107 | .needed = virt_state_needed, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 108 | .fields = (const VMStateField[]) { |
Peter Maydell | 4eb833b | 2017-01-20 11:15:09 +0000 | [diff] [blame] | 109 | VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4), |
| 110 | VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState), |
| 111 | VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX), |
| 112 | VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState), |
| 113 | VMSTATE_END_OF_LIST() |
| 114 | } |
| 115 | }; |
| 116 | |
Peter Maydell | 326049c | 2018-08-06 13:34:44 +0100 | [diff] [blame] | 117 | static int vmstate_gicv3_cpu_pre_load(void *opaque) |
Vijaya Kumar K | 6692aac | 2017-02-23 17:21:10 +0530 | [diff] [blame] | 118 | { |
| 119 | GICv3CPUState *cs = opaque; |
| 120 | |
| 121 | /* |
| 122 | * If the sre_el1 subsection is not transferred this |
| 123 | * means SRE_EL1 is 0x7 (which might not be the same as |
| 124 | * our reset value). |
| 125 | */ |
| 126 | cs->icc_sre_el1 = 0x7; |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | static bool icc_sre_el1_reg_needed(void *opaque) |
| 131 | { |
| 132 | GICv3CPUState *cs = opaque; |
| 133 | |
| 134 | return cs->icc_sre_el1 != 7; |
| 135 | } |
| 136 | |
| 137 | const VMStateDescription vmstate_gicv3_cpu_sre_el1 = { |
| 138 | .name = "arm_gicv3_cpu/sre_el1", |
| 139 | .version_id = 1, |
| 140 | .minimum_version_id = 1, |
Vijaya Kumar K | 6692aac | 2017-02-23 17:21:10 +0530 | [diff] [blame] | 141 | .needed = icc_sre_el1_reg_needed, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 142 | .fields = (const VMStateField[]) { |
Vijaya Kumar K | 6692aac | 2017-02-23 17:21:10 +0530 | [diff] [blame] | 143 | VMSTATE_UINT64(icc_sre_el1, GICv3CPUState), |
| 144 | VMSTATE_END_OF_LIST() |
| 145 | } |
| 146 | }; |
| 147 | |
Peter Maydell | 641be69 | 2022-04-08 15:15:32 +0100 | [diff] [blame] | 148 | static bool gicv4_needed(void *opaque) |
| 149 | { |
| 150 | GICv3CPUState *cs = opaque; |
| 151 | |
| 152 | return cs->gic->revision > 3; |
| 153 | } |
| 154 | |
| 155 | const VMStateDescription vmstate_gicv3_gicv4 = { |
| 156 | .name = "arm_gicv3_cpu/gicv4", |
| 157 | .version_id = 1, |
| 158 | .minimum_version_id = 1, |
| 159 | .needed = gicv4_needed, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 160 | .fields = (const VMStateField[]) { |
Peter Maydell | 641be69 | 2022-04-08 15:15:32 +0100 | [diff] [blame] | 161 | VMSTATE_UINT64(gicr_vpropbaser, GICv3CPUState), |
| 162 | VMSTATE_UINT64(gicr_vpendbaser, GICv3CPUState), |
| 163 | VMSTATE_END_OF_LIST() |
| 164 | } |
| 165 | }; |
| 166 | |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 167 | static const VMStateDescription vmstate_gicv3_cpu = { |
| 168 | .name = "arm_gicv3_cpu", |
| 169 | .version_id = 1, |
| 170 | .minimum_version_id = 1, |
Peter Maydell | 326049c | 2018-08-06 13:34:44 +0100 | [diff] [blame] | 171 | .pre_load = vmstate_gicv3_cpu_pre_load, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 172 | .fields = (const VMStateField[]) { |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 173 | VMSTATE_UINT32(level, GICv3CPUState), |
| 174 | VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), |
| 175 | VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2), |
| 176 | VMSTATE_UINT32(gicr_waker, GICv3CPUState), |
| 177 | VMSTATE_UINT64(gicr_propbaser, GICv3CPUState), |
| 178 | VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState), |
| 179 | VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState), |
| 180 | VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState), |
| 181 | VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState), |
| 182 | VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState), |
| 183 | VMSTATE_UINT32(edge_trigger, GICv3CPUState), |
| 184 | VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), |
| 185 | VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), |
| 186 | VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), |
| 187 | VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), |
| 188 | VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), |
| 189 | VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), |
| 190 | VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4), |
| 191 | VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3), |
| 192 | VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState), |
| 193 | VMSTATE_END_OF_LIST() |
Peter Maydell | 4eb833b | 2017-01-20 11:15:09 +0000 | [diff] [blame] | 194 | }, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 195 | .subsections = (const VMStateDescription * const []) { |
Peter Maydell | 4eb833b | 2017-01-20 11:15:09 +0000 | [diff] [blame] | 196 | &vmstate_gicv3_cpu_virt, |
Vijaya Kumar K | 6692aac | 2017-02-23 17:21:10 +0530 | [diff] [blame] | 197 | &vmstate_gicv3_cpu_sre_el1, |
Peter Maydell | 641be69 | 2022-04-08 15:15:32 +0100 | [diff] [blame] | 198 | &vmstate_gicv3_gicv4, |
Vijaya Kumar K | 6692aac | 2017-02-23 17:21:10 +0530 | [diff] [blame] | 199 | NULL |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 200 | } |
| 201 | }; |
| 202 | |
Peter Maydell | 326049c | 2018-08-06 13:34:44 +0100 | [diff] [blame] | 203 | static int gicv3_pre_load(void *opaque) |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 204 | { |
| 205 | GICv3State *cs = opaque; |
| 206 | |
| 207 | /* |
| 208 | * The gicd_no_migration_shift_bug flag is used for migration compatibility |
| 209 | * for old version QEMU which may have the GICD bmp shift bug under KVM mode. |
| 210 | * Strictly, what we want to know is whether the migration source is using |
| 211 | * KVM. Since we don't have any way to determine that, we look at whether the |
| 212 | * destination is using KVM; this is close enough because for the older QEMU |
| 213 | * versions with this bug KVM -> TCG migration didn't work anyway. If the |
| 214 | * source is a newer QEMU without this bug it will transmit the migration |
| 215 | * subsection which sets the flag to true; otherwise it will remain set to |
| 216 | * the value we select here. |
| 217 | */ |
| 218 | if (kvm_enabled()) { |
| 219 | cs->gicd_no_migration_shift_bug = false; |
| 220 | } |
| 221 | |
| 222 | return 0; |
| 223 | } |
| 224 | |
Peter Maydell | 78e9ddd | 2018-08-06 13:34:41 +0100 | [diff] [blame] | 225 | static bool needed_always(void *opaque) |
| 226 | { |
| 227 | return true; |
| 228 | } |
| 229 | |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 230 | const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = { |
| 231 | .name = "arm_gicv3/gicd_no_migration_shift_bug", |
| 232 | .version_id = 1, |
| 233 | .minimum_version_id = 1, |
Peter Maydell | 78e9ddd | 2018-08-06 13:34:41 +0100 | [diff] [blame] | 234 | .needed = needed_always, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 235 | .fields = (const VMStateField[]) { |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 236 | VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State), |
| 237 | VMSTATE_END_OF_LIST() |
| 238 | } |
| 239 | }; |
| 240 | |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 241 | static const VMStateDescription vmstate_gicv3 = { |
| 242 | .name = "arm_gicv3", |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 243 | .version_id = 1, |
| 244 | .minimum_version_id = 1, |
Peter Maydell | 326049c | 2018-08-06 13:34:44 +0100 | [diff] [blame] | 245 | .pre_load = gicv3_pre_load, |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 246 | .pre_save = gicv3_pre_save, |
| 247 | .post_load = gicv3_post_load, |
Eric Auger | 252a7a6 | 2017-06-13 14:57:01 +0100 | [diff] [blame] | 248 | .priority = MIG_PRI_GICV3, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 249 | .fields = (const VMStateField[]) { |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 250 | VMSTATE_UINT32(gicd_ctlr, GICv3State), |
| 251 | VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), |
| 252 | VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE), |
| 253 | VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE), |
| 254 | VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE), |
| 255 | VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE), |
| 256 | VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE), |
| 257 | VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE), |
| 258 | VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE), |
| 259 | VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ), |
| 260 | VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ), |
| 261 | VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State, |
| 262 | DIV_ROUND_UP(GICV3_MAXIRQ, 16)), |
| 263 | VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, |
| 264 | vmstate_gicv3_cpu, GICv3CPUState), |
| 265 | VMSTATE_END_OF_LIST() |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 266 | }, |
Richard Henderson | 45b1f81 | 2023-12-21 14:16:15 +1100 | [diff] [blame] | 267 | .subsections = (const VMStateDescription * const []) { |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 268 | &vmstate_gicv3_gicd_no_migration_shift_bug, |
| 269 | NULL |
Pavel Fedin | 757caee | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 270 | } |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 271 | }; |
| 272 | |
| 273 | void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, |
Peter Maydell | 01b5ab8 | 2021-09-30 16:08:40 +0100 | [diff] [blame] | 274 | const MemoryRegionOps *ops) |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 275 | { |
| 276 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); |
| 277 | int i; |
Peter Maydell | e5cba10 | 2021-09-30 16:08:42 +0100 | [diff] [blame] | 278 | int cpuidx; |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 279 | |
| 280 | /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. |
| 281 | * GPIO array layout is thus: |
| 282 | * [0..N-1] spi |
| 283 | * [N..N+31] PPIs for CPU 0 |
| 284 | * [N+32..N+63] PPIs for CPU 1 |
| 285 | * ... |
| 286 | */ |
| 287 | i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu; |
| 288 | qdev_init_gpio_in(DEVICE(s), handler, i); |
| 289 | |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 290 | for (i = 0; i < s->num_cpu; i++) { |
Peter Maydell | 3faf2b0 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 291 | sysbus_init_irq(sbd, &s->cpu[i].parent_irq); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 292 | } |
| 293 | for (i = 0; i < s->num_cpu; i++) { |
Peter Maydell | 3faf2b0 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 294 | sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 295 | } |
Peter Maydell | b53db42 | 2017-01-20 11:15:08 +0000 | [diff] [blame] | 296 | for (i = 0; i < s->num_cpu; i++) { |
| 297 | sysbus_init_irq(sbd, &s->cpu[i].parent_virq); |
| 298 | } |
| 299 | for (i = 0; i < s->num_cpu; i++) { |
| 300 | sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); |
| 301 | } |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 302 | |
| 303 | memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, |
| 304 | "gicv3_dist", 0x10000); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 305 | sysbus_init_mmio(sbd, &s->iomem_dist); |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 306 | |
Peter Maydell | e5cba10 | 2021-09-30 16:08:42 +0100 | [diff] [blame] | 307 | s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions); |
| 308 | cpuidx = 0; |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 309 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 310 | char *name = g_strdup_printf("gicv3_redist_region[%d]", i); |
Peter Maydell | e5cba10 | 2021-09-30 16:08:42 +0100 | [diff] [blame] | 311 | GICv3RedistRegion *region = &s->redist_regions[i]; |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 312 | |
Peter Maydell | e5cba10 | 2021-09-30 16:08:42 +0100 | [diff] [blame] | 313 | region->gic = s; |
| 314 | region->cpuidx = cpuidx; |
| 315 | cpuidx += s->redist_region_count[i]; |
| 316 | |
| 317 | memory_region_init_io(®ion->iomem, OBJECT(s), |
| 318 | ops ? &ops[1] : NULL, region, name, |
Peter Maydell | ae3b3ba | 2022-04-08 15:15:31 +0100 | [diff] [blame] | 319 | s->redist_region_count[i] * gicv3_redist_size(s)); |
Peter Maydell | e5cba10 | 2021-09-30 16:08:42 +0100 | [diff] [blame] | 320 | sysbus_init_mmio(sbd, ®ion->iomem); |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 321 | g_free(name); |
| 322 | } |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) |
| 326 | { |
| 327 | GICv3State *s = ARM_GICV3_COMMON(dev); |
Peter Maydell | 0461641 | 2021-09-30 16:08:41 +0100 | [diff] [blame] | 328 | int i, rdist_capacity, cpuidx; |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 329 | |
Peter Maydell | 445d582 | 2022-04-08 15:15:47 +0100 | [diff] [blame] | 330 | /* |
| 331 | * This GIC device supports only revisions 3 and 4. The GICv1/v2 |
| 332 | * is a separate device. |
| 333 | * Note that subclasses of this device may impose further restrictions |
| 334 | * on the GIC revision: notably, the in-kernel KVM GIC doesn't |
| 335 | * support GICv4. |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 336 | */ |
Peter Maydell | 445d582 | 2022-04-08 15:15:47 +0100 | [diff] [blame] | 337 | if (s->revision != 3 && s->revision != 4) { |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 338 | error_setg(errp, "unsupported GIC revision %d", s->revision); |
| 339 | return; |
| 340 | } |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 341 | |
| 342 | if (s->num_irq > GICV3_MAXIRQ) { |
| 343 | error_setg(errp, |
| 344 | "requested %u interrupt lines exceeds GIC maximum %d", |
| 345 | s->num_irq, GICV3_MAXIRQ); |
| 346 | return; |
| 347 | } |
| 348 | if (s->num_irq < GIC_INTERNAL) { |
| 349 | error_setg(errp, |
| 350 | "requested %u interrupt lines is below GIC minimum %d", |
| 351 | s->num_irq, GIC_INTERNAL); |
| 352 | return; |
| 353 | } |
Peter Maydell | 89ac9d0 | 2022-04-08 15:15:11 +0100 | [diff] [blame] | 354 | if (s->num_cpu == 0) { |
| 355 | error_setg(errp, "num-cpu must be at least 1"); |
| 356 | return; |
| 357 | } |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 358 | |
| 359 | /* ITLinesNumber is represented as (N / 32) - 1, so this is an |
| 360 | * implementation imposed restriction, not an architectural one, |
| 361 | * so we don't have to deal with bitfields where only some of the |
| 362 | * bits in a 32-bit word should be valid. |
| 363 | */ |
| 364 | if (s->num_irq % 32) { |
| 365 | error_setg(errp, |
| 366 | "%d interrupt lines unsupported: not divisible by 32", |
| 367 | s->num_irq); |
| 368 | return; |
| 369 | } |
| 370 | |
Shashi Mallela | ac30dec | 2021-09-13 16:07:23 +0100 | [diff] [blame] | 371 | if (s->lpi_enable && !s->dma) { |
| 372 | error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set"); |
| 373 | return; |
| 374 | } |
| 375 | |
Peter Maydell | 01b5ab8 | 2021-09-30 16:08:40 +0100 | [diff] [blame] | 376 | rdist_capacity = 0; |
| 377 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 378 | rdist_capacity += s->redist_region_count[i]; |
| 379 | } |
Peter Maydell | 671927a | 2022-04-08 15:15:12 +0100 | [diff] [blame] | 380 | if (rdist_capacity != s->num_cpu) { |
Peter Maydell | 01b5ab8 | 2021-09-30 16:08:40 +0100 | [diff] [blame] | 381 | error_setg(errp, "Capacity of the redist regions(%d) " |
Peter Maydell | 671927a | 2022-04-08 15:15:12 +0100 | [diff] [blame] | 382 | "does not match the number of vcpus(%d)", |
Peter Maydell | 01b5ab8 | 2021-09-30 16:08:40 +0100 | [diff] [blame] | 383 | rdist_capacity, s->num_cpu); |
| 384 | return; |
| 385 | } |
| 386 | |
Peter Maydell | e5ff041 | 2022-01-22 18:24:33 +0000 | [diff] [blame] | 387 | if (s->lpi_enable) { |
| 388 | address_space_init(&s->dma_as, s->dma, |
| 389 | "gicv3-its-sysmem"); |
| 390 | } |
| 391 | |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 392 | s->cpu = g_new0(GICv3CPUState, s->num_cpu); |
| 393 | |
| 394 | for (i = 0; i < s->num_cpu; i++) { |
| 395 | CPUState *cpu = qemu_get_cpu(i); |
| 396 | uint64_t cpu_affid; |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 397 | |
| 398 | s->cpu[i].cpu = cpu; |
| 399 | s->cpu[i].gic = s; |
Vijaya Kumar K | d3a3e52 | 2017-02-23 17:21:12 +0530 | [diff] [blame] | 400 | /* Store GICv3CPUState in CPUARMState gicv3state pointer */ |
| 401 | gicv3_set_gicv3state(cpu, &s->cpu[i]); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 402 | |
| 403 | /* Pre-construct the GICR_TYPER: |
| 404 | * For our implementation: |
| 405 | * Top 32 bits are the affinity value of the associated CPU |
| 406 | * CommonLPIAff == 01 (redistributors with same Aff3 share LPI table) |
| 407 | * Processor_Number == CPU index starting from 0 |
| 408 | * DPGS == 0 (GICR_CTLR.DPG* not supported) |
| 409 | * Last == 1 if this is the last redistributor in a series of |
| 410 | * contiguous redistributor pages |
| 411 | * DirectLPI == 0 (direct injection of LPIs not supported) |
Peter Maydell | e2d5e18 | 2022-04-08 15:15:46 +0100 | [diff] [blame] | 412 | * VLPIS == 1 if vLPIs supported (GICv4 and up) |
| 413 | * PLPIS == 1 if LPIs supported |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 414 | */ |
Marc-André Lureau | 77a7a36 | 2017-06-07 20:36:26 +0400 | [diff] [blame] | 415 | cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 416 | |
| 417 | /* The CPU mp-affinity property is in MPIDR register format; squash |
| 418 | * the affinity bytes into 32 bits as the GICR_TYPER has them. |
| 419 | */ |
Andrew Jones | 9220440 | 2016-12-27 14:59:24 +0000 | [diff] [blame] | 420 | cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) | |
| 421 | (cpu_affid & 0xFFFFFF); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 422 | s->cpu[i].gicr_typer = (cpu_affid << 32) | |
| 423 | (1 << 24) | |
Peter Maydell | 0461641 | 2021-09-30 16:08:41 +0100 | [diff] [blame] | 424 | (i << 8); |
Shashi Mallela | ac30dec | 2021-09-13 16:07:23 +0100 | [diff] [blame] | 425 | |
| 426 | if (s->lpi_enable) { |
| 427 | s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS; |
Peter Maydell | e2d5e18 | 2022-04-08 15:15:46 +0100 | [diff] [blame] | 428 | if (s->revision > 3) { |
| 429 | s->cpu[i].gicr_typer |= GICR_TYPER_VLPIS; |
| 430 | } |
Shashi Mallela | ac30dec | 2021-09-13 16:07:23 +0100 | [diff] [blame] | 431 | } |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 432 | } |
Peter Maydell | 0461641 | 2021-09-30 16:08:41 +0100 | [diff] [blame] | 433 | |
| 434 | /* |
| 435 | * Now go through and set GICR_TYPER.Last for the final |
| 436 | * redistributor in each region. |
| 437 | */ |
| 438 | cpuidx = 0; |
| 439 | for (i = 0; i < s->nb_redist_regions; i++) { |
| 440 | cpuidx += s->redist_region_count[i]; |
| 441 | s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST; |
| 442 | } |
Peter Maydell | 7c087bd | 2022-04-08 15:15:24 +0100 | [diff] [blame] | 443 | |
| 444 | s->itslist = g_ptr_array_new(); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 445 | } |
| 446 | |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 447 | static void arm_gicv3_finalize(Object *obj) |
| 448 | { |
| 449 | GICv3State *s = ARM_GICV3_COMMON(obj); |
| 450 | |
| 451 | g_free(s->redist_region_count); |
| 452 | } |
| 453 | |
Peter Maydell | 183cac3 | 2022-12-14 14:27:11 +0000 | [diff] [blame] | 454 | static void arm_gicv3_common_reset_hold(Object *obj) |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 455 | { |
Peter Maydell | 183cac3 | 2022-12-14 14:27:11 +0000 | [diff] [blame] | 456 | GICv3State *s = ARM_GICV3_COMMON(obj); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 457 | int i; |
| 458 | |
| 459 | for (i = 0; i < s->num_cpu; i++) { |
| 460 | GICv3CPUState *cs = &s->cpu[i]; |
| 461 | |
| 462 | cs->level = 0; |
| 463 | cs->gicr_ctlr = 0; |
Peter Maydell | 1611956 | 2022-01-22 18:24:39 +0000 | [diff] [blame] | 464 | if (s->lpi_enable) { |
| 465 | /* Our implementation supports clearing GICR_CTLR.EnableLPIs */ |
| 466 | cs->gicr_ctlr |= GICR_CTLR_CES; |
| 467 | } |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 468 | cs->gicr_statusr[GICV3_S] = 0; |
| 469 | cs->gicr_statusr[GICV3_NS] = 0; |
| 470 | cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; |
| 471 | cs->gicr_propbaser = 0; |
| 472 | cs->gicr_pendbaser = 0; |
Peter Maydell | 641be69 | 2022-04-08 15:15:32 +0100 | [diff] [blame] | 473 | cs->gicr_vpropbaser = 0; |
| 474 | cs->gicr_vpendbaser = 0; |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 475 | /* If we're resetting a TZ-aware GIC as if secure firmware |
| 476 | * had set it up ready to start a kernel in non-secure, we |
| 477 | * need to set interrupts to group 1 so the kernel can use them. |
| 478 | * Otherwise they reset to group 0 like the hardware. |
| 479 | */ |
| 480 | if (s->irq_reset_nonsecure) { |
| 481 | cs->gicr_igroupr0 = 0xffffffff; |
| 482 | } else { |
| 483 | cs->gicr_igroupr0 = 0; |
| 484 | } |
| 485 | |
| 486 | cs->gicr_ienabler0 = 0; |
| 487 | cs->gicr_ipendr0 = 0; |
| 488 | cs->gicr_iactiver0 = 0; |
| 489 | cs->edge_trigger = 0xffff; |
| 490 | cs->gicr_igrpmodr0 = 0; |
| 491 | cs->gicr_nsacr = 0; |
| 492 | memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); |
| 493 | |
Peter Maydell | ce187c3 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 494 | cs->hppi.prio = 0xff; |
Shashi Mallela | 17fb5e3 | 2021-09-13 16:07:24 +0100 | [diff] [blame] | 495 | cs->hpplpi.prio = 0xff; |
Peter Maydell | c3f21b0 | 2022-04-08 15:15:34 +0100 | [diff] [blame] | 496 | cs->hppvlpi.prio = 0xff; |
Peter Maydell | ce187c3 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 497 | |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 498 | /* State in the CPU interface must *not* be reset here, because it |
| 499 | * is part of the CPU's reset domain, not the GIC device's. |
| 500 | */ |
| 501 | } |
| 502 | |
| 503 | /* For our implementation affinity routing is always enabled */ |
| 504 | if (s->security_extn) { |
| 505 | s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS; |
| 506 | } else { |
| 507 | s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE; |
| 508 | } |
| 509 | |
| 510 | s->gicd_statusr[GICV3_S] = 0; |
| 511 | s->gicd_statusr[GICV3_NS] = 0; |
| 512 | |
| 513 | memset(s->group, 0, sizeof(s->group)); |
| 514 | memset(s->grpmod, 0, sizeof(s->grpmod)); |
| 515 | memset(s->enabled, 0, sizeof(s->enabled)); |
| 516 | memset(s->pending, 0, sizeof(s->pending)); |
| 517 | memset(s->active, 0, sizeof(s->active)); |
| 518 | memset(s->level, 0, sizeof(s->level)); |
| 519 | memset(s->edge_trigger, 0, sizeof(s->edge_trigger)); |
| 520 | memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority)); |
| 521 | memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter)); |
| 522 | memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr)); |
Peter Maydell | ce187c3 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 523 | /* GICD_IROUTER are UNKNOWN at reset so in theory the guest must |
| 524 | * write these to get sane behaviour and we need not populate the |
| 525 | * pointer cache here; however having the cache be different for |
| 526 | * "happened to be 0 from reset" and "guest wrote 0" would be |
| 527 | * too confusing. |
| 528 | */ |
| 529 | gicv3_cache_all_target_cpustates(s); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 530 | |
| 531 | if (s->irq_reset_nonsecure) { |
| 532 | /* If we're resetting a TZ-aware GIC as if secure firmware |
| 533 | * had set it up ready to start a kernel in non-secure, we |
| 534 | * need to set interrupts to group 1 so the kernel can use them. |
| 535 | * Otherwise they reset to group 0 like the hardware. |
| 536 | */ |
| 537 | for (i = GIC_INTERNAL; i < s->num_irq; i++) { |
| 538 | gicv3_gicd_group_set(s, i); |
| 539 | } |
| 540 | } |
Shannon Zhao | 910e204 | 2018-06-08 13:15:32 +0100 | [diff] [blame] | 541 | s->gicd_no_migration_shift_bug = true; |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, |
| 545 | bool secure_boot) |
| 546 | { |
| 547 | GICv3State *s = ARM_GICV3_COMMON(obj); |
| 548 | |
| 549 | if (s->security_extn && !secure_boot) { |
| 550 | /* We're directly booting a kernel into NonSecure. If this GIC |
| 551 | * implements the security extensions then we must configure it |
| 552 | * to have all the interrupts be NonSecure (this is a job that |
| 553 | * is done by the Secure boot firmware in real hardware, and in |
| 554 | * this mode QEMU is acting as a minimalist firmware-and-bootloader |
| 555 | * equivalent). |
| 556 | */ |
| 557 | s->irq_reset_nonsecure = true; |
| 558 | } |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | static Property arm_gicv3_common_properties[] = { |
| 562 | DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1), |
| 563 | DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), |
| 564 | DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), |
Shashi Mallela | ac30dec | 2021-09-13 16:07:23 +0100 | [diff] [blame] | 565 | DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 566 | DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), |
Peter Maydell | 39f29e5 | 2022-05-12 16:14:56 +0100 | [diff] [blame] | 567 | /* |
| 568 | * Compatibility property: force 8 bits of physical priority, even |
| 569 | * if the CPU being emulated should have fewer. |
| 570 | */ |
| 571 | DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0), |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 572 | DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, |
| 573 | redist_region_count, qdev_prop_uint32, uint32_t), |
Shashi Mallela | ac30dec | 2021-09-13 16:07:23 +0100 | [diff] [blame] | 574 | DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, |
| 575 | MemoryRegion *), |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 576 | DEFINE_PROP_END_OF_LIST(), |
| 577 | }; |
| 578 | |
| 579 | static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) |
| 580 | { |
| 581 | DeviceClass *dc = DEVICE_CLASS(klass); |
Peter Maydell | 183cac3 | 2022-12-14 14:27:11 +0000 | [diff] [blame] | 582 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 583 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 584 | |
Peter Maydell | 183cac3 | 2022-12-14 14:27:11 +0000 | [diff] [blame] | 585 | rc->phases.hold = arm_gicv3_common_reset_hold; |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 586 | dc->realize = arm_gicv3_common_realize; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 587 | device_class_set_props(dc, arm_gicv3_common_properties); |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 588 | dc->vmsd = &vmstate_gicv3; |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 589 | albifc->arm_linux_init = arm_gic_common_linux_init; |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 590 | } |
| 591 | |
| 592 | static const TypeInfo arm_gicv3_common_type = { |
| 593 | .name = TYPE_ARM_GICV3_COMMON, |
| 594 | .parent = TYPE_SYS_BUS_DEVICE, |
| 595 | .instance_size = sizeof(GICv3State), |
| 596 | .class_size = sizeof(ARMGICv3CommonClass), |
| 597 | .class_init = arm_gicv3_common_class_init, |
Eric Auger | 1e575b6 | 2018-06-22 13:28:36 +0100 | [diff] [blame] | 598 | .instance_finalize = arm_gicv3_finalize, |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 599 | .abstract = true, |
Pavel Fedin | 07e2034 | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 600 | .interfaces = (InterfaceInfo []) { |
| 601 | { TYPE_ARM_LINUX_BOOT_IF }, |
| 602 | { }, |
| 603 | }, |
Shlomo Pongratz | ff8f06e | 2015-09-24 01:29:36 +0100 | [diff] [blame] | 604 | }; |
| 605 | |
| 606 | static void register_types(void) |
| 607 | { |
| 608 | type_register_static(&arm_gicv3_common_type); |
| 609 | } |
| 610 | |
| 611 | type_init(register_types) |
Philippe Mathieu-Daudé | 0c40daf | 2023-04-05 13:48:26 +0200 | [diff] [blame] | 612 | |
| 613 | const char *gicv3_class_name(void) |
| 614 | { |
| 615 | if (kvm_irqchip_in_kernel()) { |
| 616 | return "kvm-arm-gicv3"; |
| 617 | } else { |
| 618 | if (kvm_enabled()) { |
| 619 | error_report("Userspace GICv3 is not supported with KVM"); |
| 620 | exit(1); |
| 621 | } |
| 622 | return "arm-gicv3"; |
| 623 | } |
| 624 | } |