blob: 944835e8800af3adc8eed68d4033a97fb3d037c3 [file] [log] [blame]
bellard34751872005-07-02 14:31:34 +00001/*
2 * QEMU Sparc SLAVIO aux io port emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard34751872005-07-02 14:31:34 +00004 * Copyright (c) 2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard34751872005-07-02 14:31:34 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirl2582cfa2009-07-13 16:51:27 +000024
pbrook87ecb682007-11-17 17:14:51 +000025#include "sysemu.h"
Blue Swirl2582cfa2009-07-13 16:51:27 +000026#include "sysbus.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000027#include "trace.h"
bellard34751872005-07-02 14:31:34 +000028
29/*
30 * This is the auxio port, chip control and system control part of
31 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
33 *
34 * This also includes the PMC CPU idle controller.
35 */
36
bellard34751872005-07-02 14:31:34 +000037typedef struct MiscState {
Blue Swirl2582cfa2009-07-13 16:51:27 +000038 SysBusDevice busdev;
Benoît Canetdd703aa2011-11-15 12:13:52 +010039 MemoryRegion cfg_iomem;
Benoît Canet96891e52011-11-15 12:13:53 +010040 MemoryRegion diag_iomem;
Benoît Canet2e66ac32011-11-15 12:13:54 +010041 MemoryRegion mdm_iomem;
Benoît Canetaca23c72011-11-15 12:13:55 +010042 MemoryRegion led_iomem;
Benoît Canetcd64a522011-11-15 12:13:56 +010043 MemoryRegion sysctrl_iomem;
Benoît Canetcccd43c2011-11-15 12:13:57 +010044 MemoryRegion aux1_iomem;
Benoît Canet40ce02f2011-11-15 12:13:58 +010045 MemoryRegion aux2_iomem;
pbrookd537cf62007-04-07 18:14:41 +000046 qemu_irq irq;
Blue Swirl97bbb102011-08-07 19:03:18 +000047 qemu_irq fdc_tc;
Blue Swirld37adb02009-08-29 16:37:09 +030048 uint32_t dummy;
bellard34751872005-07-02 14:31:34 +000049 uint8_t config;
50 uint8_t aux1, aux2;
blueswir1bfa30a32007-11-04 17:27:07 +000051 uint8_t diag, mctrl;
Blue Swirld37adb02009-08-29 16:37:09 +030052 uint8_t sysctrl;
blueswir16a3b9cc2007-11-11 17:56:38 +000053 uint16_t leds;
bellard34751872005-07-02 14:31:34 +000054} MiscState;
55
Blue Swirl2582cfa2009-07-13 16:51:27 +000056typedef struct APCState {
57 SysBusDevice busdev;
Benoît Canet9c48dee2011-11-15 12:13:51 +010058 MemoryRegion iomem;
Blue Swirl2582cfa2009-07-13 16:51:27 +000059 qemu_irq cpu_halt;
60} APCState;
61
blueswir15aca8c32007-05-26 17:39:43 +000062#define MISC_SIZE 1
blueswir1a8f48dc2008-12-02 17:51:19 +000063#define SYSCTRL_SIZE 4
bellard34751872005-07-02 14:31:34 +000064
blueswir12be17eb2008-03-21 18:05:23 +000065#define AUX1_TC 0x02
66
blueswir17debeb82007-12-01 14:53:22 +000067#define AUX2_PWROFF 0x01
68#define AUX2_PWRINTCLR 0x02
69#define AUX2_PWRFAIL 0x20
70
71#define CFG_PWRINTEN 0x08
72
73#define SYS_RESET 0x01
74#define SYS_RESETSTAT 0x02
75
bellard34751872005-07-02 14:31:34 +000076static void slavio_misc_update_irq(void *opaque)
77{
78 MiscState *s = opaque;
79
blueswir17debeb82007-12-01 14:53:22 +000080 if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
Blue Swirl97bf4852010-10-31 09:24:14 +000081 trace_slavio_misc_update_irq_raise();
pbrookd537cf62007-04-07 18:14:41 +000082 qemu_irq_raise(s->irq);
bellard34751872005-07-02 14:31:34 +000083 } else {
Blue Swirl97bf4852010-10-31 09:24:14 +000084 trace_slavio_misc_update_irq_lower();
pbrookd537cf62007-04-07 18:14:41 +000085 qemu_irq_lower(s->irq);
bellard34751872005-07-02 14:31:34 +000086 }
87}
88
Blue Swirl17950572009-10-24 15:27:23 +000089static void slavio_misc_reset(DeviceState *d)
bellard34751872005-07-02 14:31:34 +000090{
Blue Swirl17950572009-10-24 15:27:23 +000091 MiscState *s = container_of(d, MiscState, busdev.qdev);
bellard34751872005-07-02 14:31:34 +000092
bellard4e3b1ea2005-10-30 17:24:19 +000093 // Diagnostic and system control registers not cleared in reset
bellard34751872005-07-02 14:31:34 +000094 s->config = s->aux1 = s->aux2 = s->mctrl = 0;
95}
96
Blue Swirlb2b6f6e2009-08-09 07:27:29 +000097static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
bellard34751872005-07-02 14:31:34 +000098{
99 MiscState *s = opaque;
100
Blue Swirl97bf4852010-10-31 09:24:14 +0000101 trace_slavio_set_power_fail(power_failing, s->config);
blueswir17debeb82007-12-01 14:53:22 +0000102 if (power_failing && (s->config & CFG_PWRINTEN)) {
103 s->aux2 |= AUX2_PWRFAIL;
bellard34751872005-07-02 14:31:34 +0000104 } else {
blueswir17debeb82007-12-01 14:53:22 +0000105 s->aux2 &= ~AUX2_PWRFAIL;
bellard34751872005-07-02 14:31:34 +0000106 }
107 slavio_misc_update_irq(s);
108}
109
Anthony Liguoric227f092009-10-01 16:12:16 -0500110static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
Benoît Canetdd703aa2011-11-15 12:13:52 +0100111 uint64_t val, unsigned size)
bellard34751872005-07-02 14:31:34 +0000112{
113 MiscState *s = opaque;
114
Blue Swirl97bf4852010-10-31 09:24:14 +0000115 trace_slavio_cfg_mem_writeb(val & 0xff);
blueswir1a8f48dc2008-12-02 17:51:19 +0000116 s->config = val & 0xff;
117 slavio_misc_update_irq(s);
bellard34751872005-07-02 14:31:34 +0000118}
119
Benoît Canetdd703aa2011-11-15 12:13:52 +0100120static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
121 unsigned size)
bellard34751872005-07-02 14:31:34 +0000122{
123 MiscState *s = opaque;
124 uint32_t ret = 0;
125
blueswir1a8f48dc2008-12-02 17:51:19 +0000126 ret = s->config;
Blue Swirl97bf4852010-10-31 09:24:14 +0000127 trace_slavio_cfg_mem_readb(ret);
bellard34751872005-07-02 14:31:34 +0000128 return ret;
129}
130
Benoît Canetdd703aa2011-11-15 12:13:52 +0100131static const MemoryRegionOps slavio_cfg_mem_ops = {
132 .read = slavio_cfg_mem_readb,
133 .write = slavio_cfg_mem_writeb,
134 .endianness = DEVICE_NATIVE_ENDIAN,
135 .valid = {
136 .min_access_size = 1,
137 .max_access_size = 1,
138 },
blueswir1a8f48dc2008-12-02 17:51:19 +0000139};
140
Anthony Liguoric227f092009-10-01 16:12:16 -0500141static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
Benoît Canet96891e52011-11-15 12:13:53 +0100142 uint64_t val, unsigned size)
blueswir1a8f48dc2008-12-02 17:51:19 +0000143{
144 MiscState *s = opaque;
145
Blue Swirl97bf4852010-10-31 09:24:14 +0000146 trace_slavio_diag_mem_writeb(val & 0xff);
blueswir1a8f48dc2008-12-02 17:51:19 +0000147 s->diag = val & 0xff;
148}
149
Benoît Canet96891e52011-11-15 12:13:53 +0100150static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
151 unsigned size)
blueswir1a8f48dc2008-12-02 17:51:19 +0000152{
153 MiscState *s = opaque;
154 uint32_t ret = 0;
155
156 ret = s->diag;
Blue Swirl97bf4852010-10-31 09:24:14 +0000157 trace_slavio_diag_mem_readb(ret);
blueswir1a8f48dc2008-12-02 17:51:19 +0000158 return ret;
159}
160
Benoît Canet96891e52011-11-15 12:13:53 +0100161static const MemoryRegionOps slavio_diag_mem_ops = {
162 .read = slavio_diag_mem_readb,
163 .write = slavio_diag_mem_writeb,
164 .endianness = DEVICE_NATIVE_ENDIAN,
165 .valid = {
166 .min_access_size = 1,
167 .max_access_size = 1,
168 },
blueswir1a8f48dc2008-12-02 17:51:19 +0000169};
170
Anthony Liguoric227f092009-10-01 16:12:16 -0500171static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
Benoît Canet2e66ac32011-11-15 12:13:54 +0100172 uint64_t val, unsigned size)
blueswir1a8f48dc2008-12-02 17:51:19 +0000173{
174 MiscState *s = opaque;
175
Blue Swirl97bf4852010-10-31 09:24:14 +0000176 trace_slavio_mdm_mem_writeb(val & 0xff);
blueswir1a8f48dc2008-12-02 17:51:19 +0000177 s->mctrl = val & 0xff;
178}
179
Benoît Canet2e66ac32011-11-15 12:13:54 +0100180static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
181 unsigned size)
blueswir1a8f48dc2008-12-02 17:51:19 +0000182{
183 MiscState *s = opaque;
184 uint32_t ret = 0;
185
186 ret = s->mctrl;
Blue Swirl97bf4852010-10-31 09:24:14 +0000187 trace_slavio_mdm_mem_readb(ret);
blueswir1a8f48dc2008-12-02 17:51:19 +0000188 return ret;
189}
190
Benoît Canet2e66ac32011-11-15 12:13:54 +0100191static const MemoryRegionOps slavio_mdm_mem_ops = {
192 .read = slavio_mdm_mem_readb,
193 .write = slavio_mdm_mem_writeb,
194 .endianness = DEVICE_NATIVE_ENDIAN,
195 .valid = {
196 .min_access_size = 1,
197 .max_access_size = 1,
198 },
bellard34751872005-07-02 14:31:34 +0000199};
200
Anthony Liguoric227f092009-10-01 16:12:16 -0500201static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
Benoît Canetcccd43c2011-11-15 12:13:57 +0100202 uint64_t val, unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000203{
204 MiscState *s = opaque;
205
Blue Swirl97bf4852010-10-31 09:24:14 +0000206 trace_slavio_aux1_mem_writeb(val & 0xff);
blueswir12be17eb2008-03-21 18:05:23 +0000207 if (val & AUX1_TC) {
208 // Send a pulse to floppy terminal count line
209 if (s->fdc_tc) {
210 qemu_irq_raise(s->fdc_tc);
211 qemu_irq_lower(s->fdc_tc);
212 }
213 val &= ~AUX1_TC;
214 }
blueswir10019ad52008-01-27 09:49:28 +0000215 s->aux1 = val & 0xff;
216}
217
Benoît Canetcccd43c2011-11-15 12:13:57 +0100218static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
219 unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000220{
221 MiscState *s = opaque;
222 uint32_t ret = 0;
223
224 ret = s->aux1;
Blue Swirl97bf4852010-10-31 09:24:14 +0000225 trace_slavio_aux1_mem_readb(ret);
blueswir10019ad52008-01-27 09:49:28 +0000226 return ret;
227}
228
Benoît Canetcccd43c2011-11-15 12:13:57 +0100229static const MemoryRegionOps slavio_aux1_mem_ops = {
230 .read = slavio_aux1_mem_readb,
231 .write = slavio_aux1_mem_writeb,
232 .endianness = DEVICE_NATIVE_ENDIAN,
233 .valid = {
234 .min_access_size = 1,
235 .max_access_size = 1,
236 },
blueswir10019ad52008-01-27 09:49:28 +0000237};
238
Anthony Liguoric227f092009-10-01 16:12:16 -0500239static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
Benoît Canet40ce02f2011-11-15 12:13:58 +0100240 uint64_t val, unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000241{
242 MiscState *s = opaque;
243
244 val &= AUX2_PWRINTCLR | AUX2_PWROFF;
Blue Swirl97bf4852010-10-31 09:24:14 +0000245 trace_slavio_aux2_mem_writeb(val & 0xff);
blueswir10019ad52008-01-27 09:49:28 +0000246 val |= s->aux2 & AUX2_PWRFAIL;
247 if (val & AUX2_PWRINTCLR) // Clear Power Fail int
248 val &= AUX2_PWROFF;
249 s->aux2 = val;
250 if (val & AUX2_PWROFF)
251 qemu_system_shutdown_request();
252 slavio_misc_update_irq(s);
253}
254
Benoît Canet40ce02f2011-11-15 12:13:58 +0100255static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
256 unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000257{
258 MiscState *s = opaque;
259 uint32_t ret = 0;
260
261 ret = s->aux2;
Blue Swirl97bf4852010-10-31 09:24:14 +0000262 trace_slavio_aux2_mem_readb(ret);
blueswir10019ad52008-01-27 09:49:28 +0000263 return ret;
264}
265
Benoît Canet40ce02f2011-11-15 12:13:58 +0100266static const MemoryRegionOps slavio_aux2_mem_ops = {
267 .read = slavio_aux2_mem_readb,
268 .write = slavio_aux2_mem_writeb,
269 .endianness = DEVICE_NATIVE_ENDIAN,
270 .valid = {
271 .min_access_size = 1,
272 .max_access_size = 1,
273 },
blueswir10019ad52008-01-27 09:49:28 +0000274};
275
Benoît Canet9c48dee2011-11-15 12:13:51 +0100276static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
277 uint64_t val, unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000278{
Blue Swirl2582cfa2009-07-13 16:51:27 +0000279 APCState *s = opaque;
blueswir10019ad52008-01-27 09:49:28 +0000280
Blue Swirl97bf4852010-10-31 09:24:14 +0000281 trace_apc_mem_writeb(val & 0xff);
blueswir16d0c2932008-11-02 10:51:05 +0000282 qemu_irq_raise(s->cpu_halt);
blueswir10019ad52008-01-27 09:49:28 +0000283}
284
Benoît Canet9c48dee2011-11-15 12:13:51 +0100285static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
286 unsigned size)
blueswir10019ad52008-01-27 09:49:28 +0000287{
288 uint32_t ret = 0;
289
Blue Swirl97bf4852010-10-31 09:24:14 +0000290 trace_apc_mem_readb(ret);
blueswir10019ad52008-01-27 09:49:28 +0000291 return ret;
292}
293
Benoît Canet9c48dee2011-11-15 12:13:51 +0100294static const MemoryRegionOps apc_mem_ops = {
295 .read = apc_mem_readb,
296 .write = apc_mem_writeb,
297 .endianness = DEVICE_NATIVE_ENDIAN,
298 .valid = {
299 .min_access_size = 1,
300 .max_access_size = 1,
301 }
blueswir10019ad52008-01-27 09:49:28 +0000302};
303
Benoît Canetcd64a522011-11-15 12:13:56 +0100304static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
305 unsigned size)
blueswir1bfa30a32007-11-04 17:27:07 +0000306{
307 MiscState *s = opaque;
blueswir1a8f48dc2008-12-02 17:51:19 +0000308 uint32_t ret = 0;
blueswir1bfa30a32007-11-04 17:27:07 +0000309
blueswir1a8f48dc2008-12-02 17:51:19 +0000310 switch (addr) {
blueswir1bfa30a32007-11-04 17:27:07 +0000311 case 0:
312 ret = s->sysctrl;
313 break;
314 default:
315 break;
316 }
Blue Swirl97bf4852010-10-31 09:24:14 +0000317 trace_slavio_sysctrl_mem_readl(ret);
blueswir1bfa30a32007-11-04 17:27:07 +0000318 return ret;
319}
320
Anthony Liguoric227f092009-10-01 16:12:16 -0500321static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
Benoît Canetcd64a522011-11-15 12:13:56 +0100322 uint64_t val, unsigned size)
blueswir1bfa30a32007-11-04 17:27:07 +0000323{
324 MiscState *s = opaque;
blueswir1bfa30a32007-11-04 17:27:07 +0000325
Blue Swirl97bf4852010-10-31 09:24:14 +0000326 trace_slavio_sysctrl_mem_writel(val);
blueswir1a8f48dc2008-12-02 17:51:19 +0000327 switch (addr) {
blueswir1bfa30a32007-11-04 17:27:07 +0000328 case 0:
blueswir17debeb82007-12-01 14:53:22 +0000329 if (val & SYS_RESET) {
330 s->sysctrl = SYS_RESETSTAT;
blueswir1bfa30a32007-11-04 17:27:07 +0000331 qemu_system_reset_request();
332 }
333 break;
334 default:
335 break;
336 }
337}
338
Benoît Canetcd64a522011-11-15 12:13:56 +0100339static const MemoryRegionOps slavio_sysctrl_mem_ops = {
340 .read = slavio_sysctrl_mem_readl,
341 .write = slavio_sysctrl_mem_writel,
342 .endianness = DEVICE_NATIVE_ENDIAN,
343 .valid = {
344 .min_access_size = 4,
345 .max_access_size = 4,
346 },
blueswir1bfa30a32007-11-04 17:27:07 +0000347};
348
Benoît Canetaca23c72011-11-15 12:13:55 +0100349static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
350 unsigned size)
blueswir16a3b9cc2007-11-11 17:56:38 +0000351{
352 MiscState *s = opaque;
blueswir1a8f48dc2008-12-02 17:51:19 +0000353 uint32_t ret = 0;
blueswir16a3b9cc2007-11-11 17:56:38 +0000354
blueswir1a8f48dc2008-12-02 17:51:19 +0000355 switch (addr) {
blueswir16a3b9cc2007-11-11 17:56:38 +0000356 case 0:
357 ret = s->leds;
358 break;
359 default:
360 break;
361 }
Blue Swirl97bf4852010-10-31 09:24:14 +0000362 trace_slavio_led_mem_readw(ret);
blueswir16a3b9cc2007-11-11 17:56:38 +0000363 return ret;
364}
365
Anthony Liguoric227f092009-10-01 16:12:16 -0500366static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
Benoît Canetaca23c72011-11-15 12:13:55 +0100367 uint64_t val, unsigned size)
blueswir16a3b9cc2007-11-11 17:56:38 +0000368{
369 MiscState *s = opaque;
blueswir16a3b9cc2007-11-11 17:56:38 +0000370
Blue Swirl97bf4852010-10-31 09:24:14 +0000371 trace_slavio_led_mem_readw(val & 0xffff);
blueswir1a8f48dc2008-12-02 17:51:19 +0000372 switch (addr) {
blueswir16a3b9cc2007-11-11 17:56:38 +0000373 case 0:
blueswir1d5296cb2007-12-01 15:02:20 +0000374 s->leds = val;
blueswir16a3b9cc2007-11-11 17:56:38 +0000375 break;
376 default:
377 break;
378 }
379}
380
Benoît Canetaca23c72011-11-15 12:13:55 +0100381static const MemoryRegionOps slavio_led_mem_ops = {
382 .read = slavio_led_mem_readw,
383 .write = slavio_led_mem_writew,
384 .endianness = DEVICE_NATIVE_ENDIAN,
385 .valid = {
386 .min_access_size = 2,
387 .max_access_size = 2,
388 },
blueswir16a3b9cc2007-11-11 17:56:38 +0000389};
390
Blue Swirld37adb02009-08-29 16:37:09 +0300391static const VMStateDescription vmstate_misc = {
392 .name ="slavio_misc",
393 .version_id = 1,
394 .minimum_version_id = 1,
395 .minimum_version_id_old = 1,
396 .fields = (VMStateField []) {
397 VMSTATE_UINT32(dummy, MiscState),
398 VMSTATE_UINT8(config, MiscState),
399 VMSTATE_UINT8(aux1, MiscState),
400 VMSTATE_UINT8(aux2, MiscState),
401 VMSTATE_UINT8(diag, MiscState),
402 VMSTATE_UINT8(mctrl, MiscState),
403 VMSTATE_UINT8(sysctrl, MiscState),
404 VMSTATE_END_OF_LIST()
405 }
406};
bellard34751872005-07-02 14:31:34 +0000407
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200408static int apc_init1(SysBusDevice *dev)
Blue Swirl2582cfa2009-07-13 16:51:27 +0000409{
410 APCState *s = FROM_SYSBUS(APCState, dev);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000411
412 sysbus_init_irq(dev, &s->cpu_halt);
413
414 /* Power management (APC) XXX: not a Slavio device */
Benoît Canet9c48dee2011-11-15 12:13:51 +0100415 memory_region_init_io(&s->iomem, &apc_mem_ops, s,
416 "apc", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200417 sysbus_init_mmio(dev, &s->iomem);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200418 return 0;
Blue Swirl2582cfa2009-07-13 16:51:27 +0000419}
420
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200421static int slavio_misc_init1(SysBusDevice *dev)
Blue Swirl2582cfa2009-07-13 16:51:27 +0000422{
423 MiscState *s = FROM_SYSBUS(MiscState, dev);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000424
425 sysbus_init_irq(dev, &s->irq);
426 sysbus_init_irq(dev, &s->fdc_tc);
427
428 /* 8 bit registers */
429 /* Slavio control */
Benoît Canetdd703aa2011-11-15 12:13:52 +0100430 memory_region_init_io(&s->cfg_iomem, &slavio_cfg_mem_ops, s,
431 "configuration", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200432 sysbus_init_mmio(dev, &s->cfg_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000433
434 /* Diagnostics */
Benoît Canet96891e52011-11-15 12:13:53 +0100435 memory_region_init_io(&s->diag_iomem, &slavio_diag_mem_ops, s,
436 "diagnostic", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200437 sysbus_init_mmio(dev, &s->diag_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000438
439 /* Modem control */
Benoît Canet2e66ac32011-11-15 12:13:54 +0100440 memory_region_init_io(&s->mdm_iomem, &slavio_mdm_mem_ops, s,
441 "modem", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200442 sysbus_init_mmio(dev, &s->mdm_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000443
444 /* 16 bit registers */
445 /* ss600mp diag LEDs */
Benoît Canetaca23c72011-11-15 12:13:55 +0100446 memory_region_init_io(&s->led_iomem, &slavio_led_mem_ops, s,
447 "leds", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200448 sysbus_init_mmio(dev, &s->led_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000449
450 /* 32 bit registers */
451 /* System control */
Benoît Canetcd64a522011-11-15 12:13:56 +0100452 memory_region_init_io(&s->sysctrl_iomem, &slavio_sysctrl_mem_ops, s,
453 "system-control", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200454 sysbus_init_mmio(dev, &s->sysctrl_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000455
456 /* AUX 1 (Misc System Functions) */
Benoît Canetcccd43c2011-11-15 12:13:57 +0100457 memory_region_init_io(&s->aux1_iomem, &slavio_aux1_mem_ops, s,
458 "misc-system-functions", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200459 sysbus_init_mmio(dev, &s->aux1_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000460
461 /* AUX 2 (Software Powerdown Control) */
Benoît Canet40ce02f2011-11-15 12:13:58 +0100462 memory_region_init_io(&s->aux2_iomem, &slavio_aux2_mem_ops, s,
463 "software-powerdown-control", MISC_SIZE);
Avi Kivity750ecd42011-11-27 11:38:10 +0200464 sysbus_init_mmio(dev, &s->aux2_iomem);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000465
Blue Swirlb2b6f6e2009-08-09 07:27:29 +0000466 qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
467
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200468 return 0;
bellard34751872005-07-02 14:31:34 +0000469}
Blue Swirl2582cfa2009-07-13 16:51:27 +0000470
Anthony Liguori999e12b2012-01-24 13:12:29 -0600471static void slavio_misc_class_init(ObjectClass *klass, void *data)
472{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600473 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600474 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
475
476 k->init = slavio_misc_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600477 dc->reset = slavio_misc_reset;
478 dc->vmsd = &vmstate_misc;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600479}
480
Anthony Liguori39bffca2011-12-07 21:34:16 -0600481static TypeInfo slavio_misc_info = {
482 .name = "slavio_misc",
483 .parent = TYPE_SYS_BUS_DEVICE,
484 .instance_size = sizeof(MiscState),
485 .class_init = slavio_misc_class_init,
Blue Swirl2582cfa2009-07-13 16:51:27 +0000486};
487
Anthony Liguori999e12b2012-01-24 13:12:29 -0600488static void apc_class_init(ObjectClass *klass, void *data)
489{
490 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
491
492 k->init = apc_init1;
493}
494
Anthony Liguori39bffca2011-12-07 21:34:16 -0600495static TypeInfo apc_info = {
496 .name = "apc",
497 .parent = TYPE_SYS_BUS_DEVICE,
498 .instance_size = sizeof(MiscState),
499 .class_init = apc_class_init,
Blue Swirl2582cfa2009-07-13 16:51:27 +0000500};
501
Andreas Färber83f7d432012-02-09 15:20:55 +0100502static void slavio_misc_register_types(void)
Blue Swirl2582cfa2009-07-13 16:51:27 +0000503{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600504 type_register_static(&slavio_misc_info);
505 type_register_static(&apc_info);
Blue Swirl2582cfa2009-07-13 16:51:27 +0000506}
507
Andreas Färber83f7d432012-02-09 15:20:55 +0100508type_init(slavio_misc_register_types)