bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1 | /* |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 2 | * PowerPC emulation cpu definitions for qemu. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #if !defined (__CPU_PPC_H__) |
| 21 | #define __CPU_PPC_H__ |
| 22 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 23 | #include "config.h" |
j_mayer | de270b3 | 2007-03-28 20:43:46 +0000 | [diff] [blame] | 24 | #include <inttypes.h> |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 25 | |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 26 | //#define PPC_EMULATE_32BITS_HYPV |
| 27 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 28 | #if defined (TARGET_PPC64) |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 29 | /* PowerPC 64 definitions */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 30 | typedef uint64_t ppc_gpr_t; |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 31 | #define TARGET_LONG_BITS 64 |
j_mayer | 35cdaad | 2007-04-24 06:50:21 +0000 | [diff] [blame] | 32 | #define TARGET_PAGE_BITS 12 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 33 | |
| 34 | #else /* defined (TARGET_PPC64) */ |
| 35 | /* PowerPC 32 definitions */ |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 36 | #if (HOST_LONG_BITS >= 64) |
| 37 | /* When using 64 bits temporary registers, |
| 38 | * we can use 64 bits GPR with no extra cost |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 39 | * It's even an optimization as this will prevent |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 40 | * the compiler to do unuseful masking in the micro-ops. |
| 41 | */ |
| 42 | typedef uint64_t ppc_gpr_t; |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 43 | #else /* (HOST_LONG_BITS >= 64) */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 44 | typedef uint32_t ppc_gpr_t; |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 45 | #endif /* (HOST_LONG_BITS >= 64) */ |
| 46 | |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 47 | #define TARGET_LONG_BITS 32 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 48 | |
| 49 | #if defined(TARGET_PPCEMB) |
| 50 | /* Specific definitions for PowerPC embedded */ |
| 51 | /* BookE have 36 bits physical address space */ |
| 52 | #define TARGET_PHYS_ADDR_BITS 64 |
| 53 | #if defined(CONFIG_USER_ONLY) |
| 54 | /* It looks like a lot of Linux programs assume page size |
| 55 | * is 4kB long. This is evil, but we have to deal with it... |
| 56 | */ |
j_mayer | 35cdaad | 2007-04-24 06:50:21 +0000 | [diff] [blame] | 57 | #define TARGET_PAGE_BITS 12 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 58 | #else /* defined(CONFIG_USER_ONLY) */ |
| 59 | /* Pages can be 1 kB small */ |
| 60 | #define TARGET_PAGE_BITS 10 |
| 61 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 62 | #else /* defined(TARGET_PPCEMB) */ |
| 63 | /* "standard" PowerPC 32 definitions */ |
| 64 | #define TARGET_PAGE_BITS 12 |
| 65 | #endif /* defined(TARGET_PPCEMB) */ |
| 66 | |
| 67 | #endif /* defined (TARGET_PPC64) */ |
bellard | 3cf1e03 | 2004-01-24 15:19:09 +0000 | [diff] [blame] | 68 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 69 | #include "cpu-defs.h" |
| 70 | |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 71 | #define REGX "%016" PRIx64 |
j_mayer | e96efcf | 2007-04-14 12:17:09 +0000 | [diff] [blame] | 72 | #define ADDRX TARGET_FMT_lx |
| 73 | #define PADDRX TARGET_FMT_plx |
| 74 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 75 | #include <setjmp.h> |
| 76 | |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 77 | #include "softfloat.h" |
| 78 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 79 | #define TARGET_HAS_ICE 1 |
| 80 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 81 | #if defined (TARGET_PPC64) |
| 82 | #define ELF_MACHINE EM_PPC64 |
| 83 | #else |
| 84 | #define ELF_MACHINE EM_PPC |
| 85 | #endif |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 86 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 87 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 88 | /* MMU model */ |
j_mayer | 7820dbf | 2007-11-17 02:16:14 +0000 | [diff] [blame] | 89 | typedef enum powerpc_mmu_t powerpc_mmu_t; |
| 90 | enum powerpc_mmu_t { |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 91 | POWERPC_MMU_UNKNOWN = 0x00000000, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 92 | /* Standard 32 bits PowerPC MMU */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 93 | POWERPC_MMU_32B = 0x00000001, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 94 | /* PowerPC 6xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 95 | POWERPC_MMU_SOFT_6xx = 0x00000002, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 96 | /* PowerPC 74xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 97 | POWERPC_MMU_SOFT_74xx = 0x00000003, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 98 | /* PowerPC 4xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 99 | POWERPC_MMU_SOFT_4xx = 0x00000004, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 100 | /* PowerPC 4xx MMU with software TLB and zones protections */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 101 | POWERPC_MMU_SOFT_4xx_Z = 0x00000005, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 102 | /* PowerPC MMU in real mode only */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 103 | POWERPC_MMU_REAL = 0x00000006, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 104 | /* Freescale MPC8xx MMU model */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 105 | POWERPC_MMU_MPC8xx = 0x00000007, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 106 | /* BookE MMU model */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 107 | POWERPC_MMU_BOOKE = 0x00000008, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 108 | /* BookE FSL MMU model */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 109 | POWERPC_MMU_BOOKE_FSL = 0x00000009, |
j_mayer | faadf50 | 2007-11-03 13:37:12 +0000 | [diff] [blame] | 110 | /* PowerPC 601 MMU model (specific BATs format) */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 111 | POWERPC_MMU_601 = 0x0000000A, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 112 | #if defined(TARGET_PPC64) |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 113 | #define POWERPC_MMU_64 0x00010000 |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 114 | /* 64 bits PowerPC MMU */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 115 | POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, |
| 116 | /* 620 variant (no segment exceptions) */ |
| 117 | POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 118 | #endif /* defined(TARGET_PPC64) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 119 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 120 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 121 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 122 | /* Exception model */ |
j_mayer | 7820dbf | 2007-11-17 02:16:14 +0000 | [diff] [blame] | 123 | typedef enum powerpc_excp_t powerpc_excp_t; |
| 124 | enum powerpc_excp_t { |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 125 | POWERPC_EXCP_UNKNOWN = 0, |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 126 | /* Standard PowerPC exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 127 | POWERPC_EXCP_STD, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 128 | /* PowerPC 40x exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 129 | POWERPC_EXCP_40x, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 130 | /* PowerPC 601 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 131 | POWERPC_EXCP_601, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 132 | /* PowerPC 602 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 133 | POWERPC_EXCP_602, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 134 | /* PowerPC 603 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 135 | POWERPC_EXCP_603, |
| 136 | /* PowerPC 603e exception model */ |
| 137 | POWERPC_EXCP_603E, |
| 138 | /* PowerPC G2 exception model */ |
| 139 | POWERPC_EXCP_G2, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 140 | /* PowerPC 604 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 141 | POWERPC_EXCP_604, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 142 | /* PowerPC 7x0 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 143 | POWERPC_EXCP_7x0, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 144 | /* PowerPC 7x5 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 145 | POWERPC_EXCP_7x5, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 146 | /* PowerPC 74xx exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 147 | POWERPC_EXCP_74xx, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 148 | /* BookE exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 149 | POWERPC_EXCP_BOOKE, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 150 | #if defined(TARGET_PPC64) |
| 151 | /* PowerPC 970 exception model */ |
| 152 | POWERPC_EXCP_970, |
| 153 | #endif /* defined(TARGET_PPC64) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 154 | }; |
| 155 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 156 | /*****************************************************************************/ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 157 | /* Exception vectors definitions */ |
| 158 | enum { |
| 159 | POWERPC_EXCP_NONE = -1, |
| 160 | /* The 64 first entries are used by the PowerPC embedded specification */ |
| 161 | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
| 162 | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
| 163 | POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
| 164 | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
| 165 | POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
| 166 | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
| 167 | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
| 168 | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
| 169 | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
| 170 | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
| 171 | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
| 172 | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
| 173 | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 174 | POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
| 175 | POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 176 | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
| 177 | /* Vectors 16 to 31 are reserved */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 178 | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
| 179 | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
| 180 | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
| 181 | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
| 182 | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
| 183 | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 184 | /* Vectors 38 to 63 are reserved */ |
| 185 | /* Exceptions defined in the PowerPC server specification */ |
| 186 | POWERPC_EXCP_RESET = 64, /* System reset exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 187 | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
| 188 | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 189 | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 190 | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 191 | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
| 192 | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
| 193 | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
| 194 | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 195 | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
| 196 | /* 40x specific exceptions */ |
| 197 | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
| 198 | /* 601 specific exceptions */ |
| 199 | POWERPC_EXCP_IO = 75, /* IO error exception */ |
| 200 | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
| 201 | /* 602 specific exceptions */ |
| 202 | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
| 203 | /* 602/603 specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 204 | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 205 | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
| 206 | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
| 207 | /* Exceptions available on most PowerPC */ |
| 208 | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 209 | POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
| 210 | POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ |
| 211 | POWERPC_EXCP_SMI = 84, /* System management interrupt */ |
| 212 | POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 213 | /* 7xx/74xx specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 214 | POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 215 | /* 74xx specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 216 | POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 217 | /* 970FX specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 218 | POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
| 219 | POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ |
| 220 | /* Freescale embeded cores specific exceptions */ |
| 221 | POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ |
| 222 | POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ |
| 223 | POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ |
| 224 | POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 225 | /* EOL */ |
| 226 | POWERPC_EXCP_NB = 96, |
| 227 | /* Qemu exceptions: used internally during code translation */ |
| 228 | POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
| 229 | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
| 230 | /* Qemu exceptions: special cases we want to stop translation */ |
| 231 | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
| 232 | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
| 233 | }; |
| 234 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 235 | /* Exceptions error codes */ |
| 236 | enum { |
| 237 | /* Exception subtypes for POWERPC_EXCP_ALIGN */ |
| 238 | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
| 239 | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
| 240 | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
| 241 | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
| 242 | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
| 243 | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
| 244 | /* Exception subtypes for POWERPC_EXCP_PROGRAM */ |
| 245 | /* FP exceptions */ |
| 246 | POWERPC_EXCP_FP = 0x10, |
| 247 | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
| 248 | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
| 249 | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
| 250 | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 251 | POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 252 | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
| 253 | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
| 254 | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
| 255 | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
| 256 | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
| 257 | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
| 258 | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
| 259 | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
| 260 | /* Invalid instruction */ |
| 261 | POWERPC_EXCP_INVAL = 0x20, |
| 262 | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
| 263 | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
| 264 | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
| 265 | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
| 266 | /* Privileged instruction */ |
| 267 | POWERPC_EXCP_PRIV = 0x30, |
| 268 | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
| 269 | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
| 270 | /* Trap */ |
| 271 | POWERPC_EXCP_TRAP = 0x40, |
| 272 | }; |
| 273 | |
| 274 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 275 | /* Input pins model */ |
j_mayer | 7820dbf | 2007-11-17 02:16:14 +0000 | [diff] [blame] | 276 | typedef enum powerpc_input_t powerpc_input_t; |
| 277 | enum powerpc_input_t { |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 278 | PPC_FLAGS_INPUT_UNKNOWN = 0, |
| 279 | /* PowerPC 6xx bus */ |
| 280 | PPC_FLAGS_INPUT_6xx, |
| 281 | /* BookE bus */ |
| 282 | PPC_FLAGS_INPUT_BookE, |
| 283 | /* PowerPC 405 bus */ |
| 284 | PPC_FLAGS_INPUT_405, |
| 285 | /* PowerPC 970 bus */ |
| 286 | PPC_FLAGS_INPUT_970, |
| 287 | /* PowerPC 401 bus */ |
| 288 | PPC_FLAGS_INPUT_401, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 289 | /* Freescale RCPU bus */ |
| 290 | PPC_FLAGS_INPUT_RCPU, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 291 | }; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 292 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 293 | #define PPC_INPUT(env) (env->bus_model) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 294 | |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 295 | /*****************************************************************************/ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 296 | typedef struct ppc_def_t ppc_def_t; |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 297 | typedef struct opc_handler_t opc_handler_t; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 298 | |
| 299 | /*****************************************************************************/ |
| 300 | /* Types used to describe some PowerPC registers */ |
| 301 | typedef struct CPUPPCState CPUPPCState; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 302 | typedef struct ppc_tb_t ppc_tb_t; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 303 | typedef struct ppc_spr_t ppc_spr_t; |
| 304 | typedef struct ppc_dcr_t ppc_dcr_t; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 305 | typedef union ppc_avr_t ppc_avr_t; |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 306 | typedef union ppc_tlb_t ppc_tlb_t; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 307 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 308 | /* SPR access micro-ops generations callbacks */ |
| 309 | struct ppc_spr_t { |
| 310 | void (*uea_read)(void *opaque, int spr_num); |
| 311 | void (*uea_write)(void *opaque, int spr_num); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 312 | #if !defined(CONFIG_USER_ONLY) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 313 | void (*oea_read)(void *opaque, int spr_num); |
| 314 | void (*oea_write)(void *opaque, int spr_num); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 315 | void (*hea_read)(void *opaque, int spr_num); |
| 316 | void (*hea_write)(void *opaque, int spr_num); |
| 317 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 318 | const unsigned char *name; |
| 319 | }; |
| 320 | |
| 321 | /* Altivec registers (128 bits) */ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 322 | union ppc_avr_t { |
| 323 | uint8_t u8[16]; |
| 324 | uint16_t u16[8]; |
| 325 | uint32_t u32[4]; |
| 326 | uint64_t u64[2]; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 327 | }; |
| 328 | |
| 329 | /* Software TLB cache */ |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 330 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
| 331 | struct ppc6xx_tlb_t { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 332 | target_ulong pte0; |
| 333 | target_ulong pte1; |
| 334 | target_ulong EPN; |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
| 338 | struct ppcemb_tlb_t { |
j_mayer | c55e9ae | 2007-04-16 09:21:46 +0000 | [diff] [blame] | 339 | target_phys_addr_t RPN; |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 340 | target_ulong EPN; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 341 | target_ulong PID; |
j_mayer | c55e9ae | 2007-04-16 09:21:46 +0000 | [diff] [blame] | 342 | target_ulong size; |
| 343 | uint32_t prot; |
| 344 | uint32_t attr; /* Storage attributes */ |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | union ppc_tlb_t { |
| 348 | ppc6xx_tlb_t tlb6; |
| 349 | ppcemb_tlb_t tlbe; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 350 | }; |
| 351 | |
| 352 | /*****************************************************************************/ |
| 353 | /* Machine state register bits definition */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 354 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 355 | #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 356 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 357 | #define MSR_SHV 60 /* hypervisor state hflags */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 358 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
| 359 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 360 | #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 361 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 362 | #define MSR_VR 25 /* altivec available x hflags */ |
| 363 | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 364 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
| 365 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 366 | #define MSR_KEY 19 /* key bit on 603e */ |
j_mayer | 25ba3a6 | 2007-10-08 02:58:07 +0000 | [diff] [blame] | 367 | #define MSR_POW 18 /* Power management */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 368 | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
| 369 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 370 | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
| 371 | #define MSR_EE 15 /* External interrupt enable */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 372 | #define MSR_PR 14 /* Problem state hflags */ |
| 373 | #define MSR_FP 13 /* Floating point available hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 374 | #define MSR_ME 12 /* Machine check interrupt enable */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 375 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 376 | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
| 377 | #define MSR_DWE 10 /* Debug wait enable on 405 x */ |
| 378 | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
| 379 | #define MSR_BE 9 /* Branch trace enable x hflags */ |
| 380 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 381 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 382 | #define MSR_AL 7 /* AL bit on POWER */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 383 | #define MSR_EP 6 /* Exception prefix on 601 */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 384 | #define MSR_IR 5 /* Instruction relocate */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 385 | #define MSR_DR 4 /* Data relocate */ |
j_mayer | 25ba3a6 | 2007-10-08 02:58:07 +0000 | [diff] [blame] | 386 | #define MSR_PE 3 /* Protection enable on 403 */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 387 | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
| 388 | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
| 389 | #define MSR_RI 1 /* Recoverable interrupt 1 */ |
| 390 | #define MSR_LE 0 /* Little-endian mode 1 hflags */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 391 | |
| 392 | #define msr_sf ((env->msr >> MSR_SF) & 1) |
| 393 | #define msr_isf ((env->msr >> MSR_ISF) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 394 | #define msr_shv ((env->msr >> MSR_SHV) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 395 | #define msr_cm ((env->msr >> MSR_CM) & 1) |
| 396 | #define msr_icm ((env->msr >> MSR_ICM) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 397 | #define msr_thv ((env->msr >> MSR_THV) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 398 | #define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
| 399 | #define msr_vr ((env->msr >> MSR_VR) & 1) |
aurel32 | f932041 | 2008-05-06 14:58:15 +0000 | [diff] [blame] | 400 | #define msr_spe ((env->msr >> MSR_SPE) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 401 | #define msr_ap ((env->msr >> MSR_AP) & 1) |
| 402 | #define msr_sa ((env->msr >> MSR_SA) & 1) |
| 403 | #define msr_key ((env->msr >> MSR_KEY) & 1) |
| 404 | #define msr_pow ((env->msr >> MSR_POW) & 1) |
| 405 | #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) |
| 406 | #define msr_ce ((env->msr >> MSR_CE) & 1) |
| 407 | #define msr_ile ((env->msr >> MSR_ILE) & 1) |
| 408 | #define msr_ee ((env->msr >> MSR_EE) & 1) |
| 409 | #define msr_pr ((env->msr >> MSR_PR) & 1) |
| 410 | #define msr_fp ((env->msr >> MSR_FP) & 1) |
| 411 | #define msr_me ((env->msr >> MSR_ME) & 1) |
| 412 | #define msr_fe0 ((env->msr >> MSR_FE0) & 1) |
| 413 | #define msr_se ((env->msr >> MSR_SE) & 1) |
| 414 | #define msr_dwe ((env->msr >> MSR_DWE) & 1) |
| 415 | #define msr_uble ((env->msr >> MSR_UBLE) & 1) |
| 416 | #define msr_be ((env->msr >> MSR_BE) & 1) |
| 417 | #define msr_de ((env->msr >> MSR_DE) & 1) |
| 418 | #define msr_fe1 ((env->msr >> MSR_FE1) & 1) |
| 419 | #define msr_al ((env->msr >> MSR_AL) & 1) |
| 420 | #define msr_ep ((env->msr >> MSR_EP) & 1) |
| 421 | #define msr_ir ((env->msr >> MSR_IR) & 1) |
| 422 | #define msr_dr ((env->msr >> MSR_DR) & 1) |
| 423 | #define msr_pe ((env->msr >> MSR_PE) & 1) |
| 424 | #define msr_px ((env->msr >> MSR_PX) & 1) |
| 425 | #define msr_pmm ((env->msr >> MSR_PMM) & 1) |
| 426 | #define msr_ri ((env->msr >> MSR_RI) & 1) |
| 427 | #define msr_le ((env->msr >> MSR_LE) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 428 | /* Hypervisor bit is more specific */ |
| 429 | #if defined(TARGET_PPC64) |
| 430 | #define MSR_HVB (1ULL << MSR_SHV) |
| 431 | #define msr_hv msr_shv |
| 432 | #else |
| 433 | #if defined(PPC_EMULATE_32BITS_HYPV) |
| 434 | #define MSR_HVB (1ULL << MSR_THV) |
| 435 | #define msr_hv msr_thv |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 436 | #else |
| 437 | #define MSR_HVB (0ULL) |
| 438 | #define msr_hv (0) |
| 439 | #endif |
| 440 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 441 | |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 442 | enum { |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 443 | POWERPC_FLAG_NONE = 0x00000000, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 444 | /* Flag for MSR bit 25 signification (VRE/SPE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 445 | POWERPC_FLAG_SPE = 0x00000001, |
| 446 | POWERPC_FLAG_VRE = 0x00000002, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 447 | /* Flag for MSR bit 17 signification (TGPR/CE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 448 | POWERPC_FLAG_TGPR = 0x00000004, |
| 449 | POWERPC_FLAG_CE = 0x00000008, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 450 | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 451 | POWERPC_FLAG_SE = 0x00000010, |
| 452 | POWERPC_FLAG_DWE = 0x00000020, |
| 453 | POWERPC_FLAG_UBLE = 0x00000040, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 454 | /* Flag for MSR bit 9 signification (BE/DE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 455 | POWERPC_FLAG_BE = 0x00000080, |
| 456 | POWERPC_FLAG_DE = 0x00000100, |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 457 | /* Flag for MSR bit 2 signification (PX/PMM) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 458 | POWERPC_FLAG_PX = 0x00000200, |
| 459 | POWERPC_FLAG_PMM = 0x00000400, |
| 460 | /* Flag for special features */ |
| 461 | /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ |
| 462 | POWERPC_FLAG_RTC_CLK = 0x00010000, |
| 463 | POWERPC_FLAG_BUS_CLK = 0x00020000, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 464 | }; |
| 465 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 466 | /*****************************************************************************/ |
| 467 | /* Floating point status and control register */ |
| 468 | #define FPSCR_FX 31 /* Floating-point exception summary */ |
| 469 | #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ |
| 470 | #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ |
| 471 | #define FPSCR_OX 28 /* Floating-point overflow exception */ |
| 472 | #define FPSCR_UX 27 /* Floating-point underflow exception */ |
| 473 | #define FPSCR_ZX 26 /* Floating-point zero divide exception */ |
| 474 | #define FPSCR_XX 25 /* Floating-point inexact exception */ |
| 475 | #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ |
| 476 | #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ |
| 477 | #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ |
| 478 | #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ |
| 479 | #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ |
| 480 | #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ |
| 481 | #define FPSCR_FR 18 /* Floating-point fraction rounded */ |
| 482 | #define FPSCR_FI 17 /* Floating-point fraction inexact */ |
| 483 | #define FPSCR_C 16 /* Floating-point result class descriptor */ |
| 484 | #define FPSCR_FL 15 /* Floating-point less than or negative */ |
| 485 | #define FPSCR_FG 14 /* Floating-point greater than or negative */ |
| 486 | #define FPSCR_FE 13 /* Floating-point equal or zero */ |
| 487 | #define FPSCR_FU 12 /* Floating-point unordered or NaN */ |
| 488 | #define FPSCR_FPCC 12 /* Floating-point condition code */ |
| 489 | #define FPSCR_FPRF 12 /* Floating-point result flags */ |
| 490 | #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ |
| 491 | #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ |
| 492 | #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ |
| 493 | #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ |
| 494 | #define FPSCR_OE 6 /* Floating-point overflow exception enable */ |
| 495 | #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ |
| 496 | #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ |
| 497 | #define FPSCR_XE 3 /* Floating-point inexact exception enable */ |
| 498 | #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ |
| 499 | #define FPSCR_RN1 1 |
| 500 | #define FPSCR_RN 0 /* Floating-point rounding control */ |
| 501 | #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) |
| 502 | #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) |
| 503 | #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) |
| 504 | #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) |
| 505 | #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) |
| 506 | #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) |
| 507 | #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) |
| 508 | #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) |
| 509 | #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) |
| 510 | #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) |
| 511 | #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) |
| 512 | #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) |
| 513 | #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) |
| 514 | #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) |
| 515 | #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) |
| 516 | #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) |
| 517 | #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) |
| 518 | #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) |
| 519 | #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) |
| 520 | #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) |
| 521 | #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) |
| 522 | #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) |
| 523 | #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) |
| 524 | /* Invalid operation exception summary */ |
| 525 | #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ |
| 526 | (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ |
| 527 | (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ |
| 528 | (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ |
| 529 | (1 << FPSCR_VXCVI))) |
| 530 | /* exception summary */ |
| 531 | #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) |
| 532 | /* enabled exception summary */ |
| 533 | #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ |
| 534 | 0x1F) |
| 535 | |
| 536 | /*****************************************************************************/ |
| 537 | /* The whole PowerPC CPU context */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 538 | #define NB_MMU_MODES 3 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 539 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 540 | struct CPUPPCState { |
| 541 | /* First are the most commonly used resources |
| 542 | * during translated code execution |
| 543 | */ |
j_mayer | 57c2627 | 2007-11-14 18:45:52 +0000 | [diff] [blame] | 544 | #if (HOST_LONG_BITS == 32) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 545 | /* temporary fixed-point registers |
j_mayer | 57c2627 | 2007-11-14 18:45:52 +0000 | [diff] [blame] | 546 | * used to emulate 64 bits registers on 32 bits hosts |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 547 | */ |
j_mayer | 57c2627 | 2007-11-14 18:45:52 +0000 | [diff] [blame] | 548 | uint64_t t0, t1, t2; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 549 | #endif |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 550 | ppc_avr_t avr0, avr1, avr2; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 551 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 552 | /* general purpose registers */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 553 | ppc_gpr_t gpr[32]; |
j_mayer | 65d6c0f | 2007-11-12 23:29:14 +0000 | [diff] [blame] | 554 | #if !defined(TARGET_PPC64) |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 555 | /* Storage for GPR MSB, used by the SPE extension */ |
| 556 | ppc_gpr_t gprh[32]; |
| 557 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 558 | /* LR */ |
| 559 | target_ulong lr; |
| 560 | /* CTR */ |
| 561 | target_ulong ctr; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 562 | /* condition register */ |
| 563 | uint8_t crf[8]; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 564 | /* XER */ |
| 565 | /* XXX: We use only 5 fields, but we want to keep the structure aligned */ |
| 566 | uint8_t xer[8]; |
| 567 | /* Reservation address */ |
| 568 | target_ulong reserve; |
| 569 | |
| 570 | /* Those ones are used in supervisor mode only */ |
| 571 | /* machine state register */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 572 | target_ulong msr; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 573 | /* temporary general purpose registers */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 574 | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 575 | |
| 576 | /* Floating point execution context */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 577 | /* temporary float registers */ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 578 | float64 ft0; |
| 579 | float64 ft1; |
| 580 | float64 ft2; |
| 581 | float_status fp_status; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 582 | /* floating point registers */ |
| 583 | float64 fpr[32]; |
| 584 | /* floating point status and control register */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 585 | uint32_t fpscr; |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 586 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 587 | CPU_COMMON |
| 588 | |
bellard | ac9eb07 | 2004-01-04 23:26:24 +0000 | [diff] [blame] | 589 | int access_type; /* when a memory exception occurs, the access |
| 590 | type is stored here */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 591 | |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 592 | /* MMU context - only relevant for full system emulation */ |
| 593 | #if !defined(CONFIG_USER_ONLY) |
| 594 | #if defined(TARGET_PPC64) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 595 | /* Address space register */ |
| 596 | target_ulong asr; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 597 | /* PowerPC 64 SLB area */ |
| 598 | int slb_nr; |
| 599 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 600 | /* segment registers */ |
| 601 | target_ulong sdr1; |
| 602 | target_ulong sr[16]; |
| 603 | /* BATs */ |
| 604 | int nb_BATs; |
| 605 | target_ulong DBAT[2][8]; |
| 606 | target_ulong IBAT[2][8]; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 607 | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 608 | int nb_tlb; /* Total number of TLB */ |
| 609 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
| 610 | int nb_ways; /* Number of ways in the TLB set */ |
| 611 | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 612 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 613 | int nb_pids; /* Number of available PID registers */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 614 | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 615 | /* 403 dedicated access protection registers */ |
| 616 | target_ulong pb[4]; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 617 | #endif |
| 618 | |
| 619 | /* Other registers */ |
| 620 | /* Special purpose registers */ |
| 621 | target_ulong spr[1024]; |
| 622 | ppc_spr_t spr_cb[1024]; |
| 623 | /* Altivec registers */ |
| 624 | ppc_avr_t avr[32]; |
| 625 | uint32_t vscr; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 626 | /* SPE registers */ |
| 627 | ppc_gpr_t spe_acc; |
| 628 | float_status spe_status; |
| 629 | uint32_t spe_fscr; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 630 | |
| 631 | /* Internal devices resources */ |
| 632 | /* Time base and decrementer */ |
| 633 | ppc_tb_t *tb_env; |
| 634 | /* Device control registers */ |
| 635 | ppc_dcr_t *dcr_env; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 636 | |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 637 | int dcache_line_size; |
| 638 | int icache_line_size; |
| 639 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 640 | /* Those resources are used during exception processing */ |
| 641 | /* CPU model definition */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 642 | target_ulong msr_mask; |
j_mayer | 7820dbf | 2007-11-17 02:16:14 +0000 | [diff] [blame] | 643 | powerpc_mmu_t mmu_model; |
| 644 | powerpc_excp_t excp_model; |
| 645 | powerpc_input_t bus_model; |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 646 | int bfd_mach; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 647 | uint32_t flags; |
| 648 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 649 | int error_code; |
| 650 | int interrupt_request; |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 651 | uint32_t pending_interrupts; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 652 | #if !defined(CONFIG_USER_ONLY) |
| 653 | /* This is the IRQ controller, which is implementation dependant |
| 654 | * and only relevant when emulating a complete machine. |
| 655 | */ |
| 656 | uint32_t irq_input_state; |
| 657 | void **irq_inputs; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 658 | /* Exception vectors */ |
| 659 | target_ulong excp_vectors[POWERPC_EXCP_NB]; |
| 660 | target_ulong excp_prefix; |
| 661 | target_ulong ivor_mask; |
| 662 | target_ulong ivpr_mask; |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 663 | target_ulong hreset_vector; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 664 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 665 | |
| 666 | /* Those resources are used only during code translation */ |
| 667 | /* Next instruction pointer */ |
| 668 | target_ulong nip; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 669 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 670 | /* opcode handlers */ |
| 671 | opc_handler_t *opcodes[0x40]; |
| 672 | |
| 673 | /* Those resources are used only in Qemu core */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 674 | int user_mode_only; /* user mode only simulation */ |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 675 | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
| 676 | target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 677 | int mmu_idx; /* precomputed MMU index to speed up mem accesses */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 678 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 679 | /* Power management */ |
| 680 | int power_mode; |
j_mayer | cd34634 | 2007-10-25 23:27:04 +0000 | [diff] [blame] | 681 | int (*check_pow)(CPUPPCState *env); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 682 | |
bellard | 6d506e6 | 2005-06-04 22:16:41 +0000 | [diff] [blame] | 683 | /* temporary hack to handle OSI calls (only used if non NULL) */ |
| 684 | int (*osi_call)(struct CPUPPCState *env); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 685 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 686 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 687 | /* Context used internally during MMU translations */ |
| 688 | typedef struct mmu_ctx_t mmu_ctx_t; |
| 689 | struct mmu_ctx_t { |
| 690 | target_phys_addr_t raddr; /* Real address */ |
| 691 | int prot; /* Protection bits */ |
| 692 | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
| 693 | target_ulong ptem; /* Virtual segment ID | API */ |
| 694 | int key; /* Access key */ |
j_mayer | b227a8e | 2007-10-14 10:21:20 +0000 | [diff] [blame] | 695 | int nx; /* Non-execute area */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 696 | }; |
| 697 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 698 | /*****************************************************************************/ |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 699 | CPUPPCState *cpu_ppc_init (const char *cpu_model); |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 700 | int cpu_ppc_exec (CPUPPCState *s); |
| 701 | void cpu_ppc_close (CPUPPCState *s); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 702 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 703 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 704 | is returned if the signal was handled by the virtual CPU. */ |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 705 | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
| 706 | void *puc); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 707 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 708 | void do_interrupt (CPUPPCState *env); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 709 | void ppc_hw_interrupt (CPUPPCState *env); |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 710 | void cpu_loop_exit (void); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 711 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 712 | void dump_stack (CPUPPCState *env); |
| 713 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 714 | #if !defined(CONFIG_USER_ONLY) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 715 | target_ulong do_load_ibatu (CPUPPCState *env, int nr); |
| 716 | target_ulong do_load_ibatl (CPUPPCState *env, int nr); |
| 717 | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
| 718 | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
| 719 | target_ulong do_load_dbatu (CPUPPCState *env, int nr); |
| 720 | target_ulong do_load_dbatl (CPUPPCState *env, int nr); |
| 721 | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
| 722 | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 723 | void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); |
| 724 | void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 725 | target_ulong do_load_sdr1 (CPUPPCState *env); |
| 726 | void do_store_sdr1 (CPUPPCState *env, target_ulong value); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 727 | #if defined(TARGET_PPC64) |
| 728 | target_ulong ppc_load_asr (CPUPPCState *env); |
| 729 | void ppc_store_asr (CPUPPCState *env, target_ulong value); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 730 | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr); |
| 731 | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs); |
| 732 | #endif /* defined(TARGET_PPC64) */ |
| 733 | #if 0 // Unused |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 734 | target_ulong do_load_sr (CPUPPCState *env, int srnum); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 735 | #endif |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 736 | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
| 737 | #endif /* !defined(CONFIG_USER_ONLY) */ |
j_mayer | bfa1e5c | 2007-09-30 00:50:23 +0000 | [diff] [blame] | 738 | target_ulong ppc_load_xer (CPUPPCState *env); |
| 739 | void ppc_store_xer (CPUPPCState *env, target_ulong value); |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 740 | void ppc_store_msr (CPUPPCState *env, target_ulong value); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 741 | |
j_mayer | 0a032cb | 2007-04-16 08:56:52 +0000 | [diff] [blame] | 742 | void cpu_ppc_reset (void *opaque); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 743 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 744 | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 745 | |
| 746 | const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name); |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 747 | int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); |
bellard | 85c4adf | 2004-05-23 21:25:39 +0000 | [diff] [blame] | 748 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 749 | /* Time-base and decrementer management */ |
| 750 | #ifndef NO_CPU_IO_DEFS |
| 751 | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
| 752 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
| 753 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); |
| 754 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 755 | uint32_t cpu_ppc_load_atbl (CPUPPCState *env); |
| 756 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
| 757 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); |
| 758 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 759 | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
| 760 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 761 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
| 762 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); |
| 763 | uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
| 764 | void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 765 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
| 766 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
| 767 | #if !defined(CONFIG_USER_ONLY) |
| 768 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); |
| 769 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); |
| 770 | target_ulong load_40x_pit (CPUPPCState *env); |
| 771 | void store_40x_pit (CPUPPCState *env, target_ulong val); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 772 | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); |
j_mayer | c294fc5 | 2007-04-24 06:44:14 +0000 | [diff] [blame] | 773 | void store_40x_sler (CPUPPCState *env, uint32_t val); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 774 | void store_booke_tcr (CPUPPCState *env, target_ulong val); |
| 775 | void store_booke_tsr (CPUPPCState *env, target_ulong val); |
j_mayer | 0a032cb | 2007-04-16 08:56:52 +0000 | [diff] [blame] | 776 | void ppc_tlb_invalidate_all (CPUPPCState *env); |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 777 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); |
| 778 | #if defined(TARGET_PPC64) |
| 779 | void ppc_slb_invalidate_all (CPUPPCState *env); |
| 780 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0); |
| 781 | #endif |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 782 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 783 | #endif |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 784 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 785 | |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 786 | static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn) |
| 787 | { |
| 788 | uint64_t gprv; |
| 789 | |
| 790 | gprv = env->gpr[gprn]; |
| 791 | #if !defined(TARGET_PPC64) |
| 792 | if (env->flags & POWERPC_FLAG_SPE) { |
| 793 | /* If the CPU implements the SPE extension, we have to get the |
| 794 | * high bits of the GPR from the gprh storage area |
| 795 | */ |
| 796 | gprv &= 0xFFFFFFFFULL; |
| 797 | gprv |= (uint64_t)env->gprh[gprn] << 32; |
| 798 | } |
| 799 | #endif |
| 800 | |
| 801 | return gprv; |
| 802 | } |
| 803 | |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 804 | /* Device control registers */ |
| 805 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
| 806 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
| 807 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 808 | #define CPUState CPUPPCState |
| 809 | #define cpu_init cpu_ppc_init |
| 810 | #define cpu_exec cpu_ppc_exec |
| 811 | #define cpu_gen_code cpu_ppc_gen_code |
| 812 | #define cpu_signal_handler cpu_ppc_signal_handler |
j_mayer | c732abe | 2007-10-12 06:47:46 +0000 | [diff] [blame] | 813 | #define cpu_list ppc_cpu_list |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 814 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 815 | /* MMU modes definitions */ |
| 816 | #define MMU_MODE0_SUFFIX _user |
| 817 | #define MMU_MODE1_SUFFIX _kernel |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 818 | #define MMU_MODE2_SUFFIX _hypv |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 819 | #define MMU_USER_IDX 0 |
| 820 | static inline int cpu_mmu_index (CPUState *env) |
| 821 | { |
| 822 | return env->mmu_idx; |
| 823 | } |
| 824 | |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 825 | #if defined(CONFIG_USER_ONLY) |
| 826 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
| 827 | { |
| 828 | int i; |
pbrook | f8ed707 | 2008-05-30 17:54:15 +0000 | [diff] [blame] | 829 | if (newsp) |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 830 | env->gpr[1] = newsp; |
| 831 | for (i = 7; i < 32; i++) |
| 832 | env->gpr[i] = 0; |
| 833 | } |
| 834 | #endif |
| 835 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 836 | #include "cpu-all.h" |
| 837 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 838 | /*****************************************************************************/ |
| 839 | /* Registers definitions */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 840 | #define XER_SO 31 |
| 841 | #define XER_OV 30 |
| 842 | #define XER_CA 29 |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 843 | #define XER_CMP 8 |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 844 | #define XER_BC 0 |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 845 | #define xer_so env->xer[4] |
| 846 | #define xer_ov env->xer[6] |
| 847 | #define xer_ca env->xer[2] |
| 848 | #define xer_cmp env->xer[1] |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 849 | #define xer_bc env->xer[0] |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 850 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 851 | /* SPR definitions */ |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 852 | #define SPR_MQ (0x000) |
| 853 | #define SPR_XER (0x001) |
| 854 | #define SPR_601_VRTCU (0x004) |
| 855 | #define SPR_601_VRTCL (0x005) |
| 856 | #define SPR_601_UDECR (0x006) |
| 857 | #define SPR_LR (0x008) |
| 858 | #define SPR_CTR (0x009) |
| 859 | #define SPR_DSISR (0x012) |
| 860 | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
| 861 | #define SPR_601_RTCU (0x014) |
| 862 | #define SPR_601_RTCL (0x015) |
| 863 | #define SPR_DECR (0x016) |
| 864 | #define SPR_SDR1 (0x019) |
| 865 | #define SPR_SRR0 (0x01A) |
| 866 | #define SPR_SRR1 (0x01B) |
| 867 | #define SPR_AMR (0x01D) |
| 868 | #define SPR_BOOKE_PID (0x030) |
| 869 | #define SPR_BOOKE_DECAR (0x036) |
| 870 | #define SPR_BOOKE_CSRR0 (0x03A) |
| 871 | #define SPR_BOOKE_CSRR1 (0x03B) |
| 872 | #define SPR_BOOKE_DEAR (0x03D) |
| 873 | #define SPR_BOOKE_ESR (0x03E) |
| 874 | #define SPR_BOOKE_IVPR (0x03F) |
| 875 | #define SPR_MPC_EIE (0x050) |
| 876 | #define SPR_MPC_EID (0x051) |
| 877 | #define SPR_MPC_NRI (0x052) |
| 878 | #define SPR_CTRL (0x088) |
| 879 | #define SPR_MPC_CMPA (0x090) |
| 880 | #define SPR_MPC_CMPB (0x091) |
| 881 | #define SPR_MPC_CMPC (0x092) |
| 882 | #define SPR_MPC_CMPD (0x093) |
| 883 | #define SPR_MPC_ECR (0x094) |
| 884 | #define SPR_MPC_DER (0x095) |
| 885 | #define SPR_MPC_COUNTA (0x096) |
| 886 | #define SPR_MPC_COUNTB (0x097) |
| 887 | #define SPR_UCTRL (0x098) |
| 888 | #define SPR_MPC_CMPE (0x098) |
| 889 | #define SPR_MPC_CMPF (0x099) |
| 890 | #define SPR_MPC_CMPG (0x09A) |
| 891 | #define SPR_MPC_CMPH (0x09B) |
| 892 | #define SPR_MPC_LCTRL1 (0x09C) |
| 893 | #define SPR_MPC_LCTRL2 (0x09D) |
| 894 | #define SPR_MPC_ICTRL (0x09E) |
| 895 | #define SPR_MPC_BAR (0x09F) |
| 896 | #define SPR_VRSAVE (0x100) |
| 897 | #define SPR_USPRG0 (0x100) |
| 898 | #define SPR_USPRG1 (0x101) |
| 899 | #define SPR_USPRG2 (0x102) |
| 900 | #define SPR_USPRG3 (0x103) |
| 901 | #define SPR_USPRG4 (0x104) |
| 902 | #define SPR_USPRG5 (0x105) |
| 903 | #define SPR_USPRG6 (0x106) |
| 904 | #define SPR_USPRG7 (0x107) |
| 905 | #define SPR_VTBL (0x10C) |
| 906 | #define SPR_VTBU (0x10D) |
| 907 | #define SPR_SPRG0 (0x110) |
| 908 | #define SPR_SPRG1 (0x111) |
| 909 | #define SPR_SPRG2 (0x112) |
| 910 | #define SPR_SPRG3 (0x113) |
| 911 | #define SPR_SPRG4 (0x114) |
| 912 | #define SPR_SCOMC (0x114) |
| 913 | #define SPR_SPRG5 (0x115) |
| 914 | #define SPR_SCOMD (0x115) |
| 915 | #define SPR_SPRG6 (0x116) |
| 916 | #define SPR_SPRG7 (0x117) |
| 917 | #define SPR_ASR (0x118) |
| 918 | #define SPR_EAR (0x11A) |
| 919 | #define SPR_TBL (0x11C) |
| 920 | #define SPR_TBU (0x11D) |
| 921 | #define SPR_TBU40 (0x11E) |
| 922 | #define SPR_SVR (0x11E) |
| 923 | #define SPR_BOOKE_PIR (0x11E) |
| 924 | #define SPR_PVR (0x11F) |
| 925 | #define SPR_HSPRG0 (0x130) |
| 926 | #define SPR_BOOKE_DBSR (0x130) |
| 927 | #define SPR_HSPRG1 (0x131) |
| 928 | #define SPR_HDSISR (0x132) |
| 929 | #define SPR_HDAR (0x133) |
| 930 | #define SPR_BOOKE_DBCR0 (0x134) |
| 931 | #define SPR_IBCR (0x135) |
| 932 | #define SPR_PURR (0x135) |
| 933 | #define SPR_BOOKE_DBCR1 (0x135) |
| 934 | #define SPR_DBCR (0x136) |
| 935 | #define SPR_HDEC (0x136) |
| 936 | #define SPR_BOOKE_DBCR2 (0x136) |
| 937 | #define SPR_HIOR (0x137) |
| 938 | #define SPR_MBAR (0x137) |
| 939 | #define SPR_RMOR (0x138) |
| 940 | #define SPR_BOOKE_IAC1 (0x138) |
| 941 | #define SPR_HRMOR (0x139) |
| 942 | #define SPR_BOOKE_IAC2 (0x139) |
| 943 | #define SPR_HSRR0 (0x13A) |
| 944 | #define SPR_BOOKE_IAC3 (0x13A) |
| 945 | #define SPR_HSRR1 (0x13B) |
| 946 | #define SPR_BOOKE_IAC4 (0x13B) |
| 947 | #define SPR_LPCR (0x13C) |
| 948 | #define SPR_BOOKE_DAC1 (0x13C) |
| 949 | #define SPR_LPIDR (0x13D) |
| 950 | #define SPR_DABR2 (0x13D) |
| 951 | #define SPR_BOOKE_DAC2 (0x13D) |
| 952 | #define SPR_BOOKE_DVC1 (0x13E) |
| 953 | #define SPR_BOOKE_DVC2 (0x13F) |
| 954 | #define SPR_BOOKE_TSR (0x150) |
| 955 | #define SPR_BOOKE_TCR (0x154) |
| 956 | #define SPR_BOOKE_IVOR0 (0x190) |
| 957 | #define SPR_BOOKE_IVOR1 (0x191) |
| 958 | #define SPR_BOOKE_IVOR2 (0x192) |
| 959 | #define SPR_BOOKE_IVOR3 (0x193) |
| 960 | #define SPR_BOOKE_IVOR4 (0x194) |
| 961 | #define SPR_BOOKE_IVOR5 (0x195) |
| 962 | #define SPR_BOOKE_IVOR6 (0x196) |
| 963 | #define SPR_BOOKE_IVOR7 (0x197) |
| 964 | #define SPR_BOOKE_IVOR8 (0x198) |
| 965 | #define SPR_BOOKE_IVOR9 (0x199) |
| 966 | #define SPR_BOOKE_IVOR10 (0x19A) |
| 967 | #define SPR_BOOKE_IVOR11 (0x19B) |
| 968 | #define SPR_BOOKE_IVOR12 (0x19C) |
| 969 | #define SPR_BOOKE_IVOR13 (0x19D) |
| 970 | #define SPR_BOOKE_IVOR14 (0x19E) |
| 971 | #define SPR_BOOKE_IVOR15 (0x19F) |
| 972 | #define SPR_BOOKE_SPEFSCR (0x200) |
| 973 | #define SPR_Exxx_BBEAR (0x201) |
| 974 | #define SPR_Exxx_BBTAR (0x202) |
| 975 | #define SPR_Exxx_L1CFG0 (0x203) |
| 976 | #define SPR_Exxx_NPIDR (0x205) |
| 977 | #define SPR_ATBL (0x20E) |
| 978 | #define SPR_ATBU (0x20F) |
| 979 | #define SPR_IBAT0U (0x210) |
| 980 | #define SPR_BOOKE_IVOR32 (0x210) |
| 981 | #define SPR_RCPU_MI_GRA (0x210) |
| 982 | #define SPR_IBAT0L (0x211) |
| 983 | #define SPR_BOOKE_IVOR33 (0x211) |
| 984 | #define SPR_IBAT1U (0x212) |
| 985 | #define SPR_BOOKE_IVOR34 (0x212) |
| 986 | #define SPR_IBAT1L (0x213) |
| 987 | #define SPR_BOOKE_IVOR35 (0x213) |
| 988 | #define SPR_IBAT2U (0x214) |
| 989 | #define SPR_BOOKE_IVOR36 (0x214) |
| 990 | #define SPR_IBAT2L (0x215) |
| 991 | #define SPR_BOOKE_IVOR37 (0x215) |
| 992 | #define SPR_IBAT3U (0x216) |
| 993 | #define SPR_IBAT3L (0x217) |
| 994 | #define SPR_DBAT0U (0x218) |
| 995 | #define SPR_RCPU_L2U_GRA (0x218) |
| 996 | #define SPR_DBAT0L (0x219) |
| 997 | #define SPR_DBAT1U (0x21A) |
| 998 | #define SPR_DBAT1L (0x21B) |
| 999 | #define SPR_DBAT2U (0x21C) |
| 1000 | #define SPR_DBAT2L (0x21D) |
| 1001 | #define SPR_DBAT3U (0x21E) |
| 1002 | #define SPR_DBAT3L (0x21F) |
| 1003 | #define SPR_IBAT4U (0x230) |
| 1004 | #define SPR_RPCU_BBCMCR (0x230) |
| 1005 | #define SPR_MPC_IC_CST (0x230) |
| 1006 | #define SPR_Exxx_CTXCR (0x230) |
| 1007 | #define SPR_IBAT4L (0x231) |
| 1008 | #define SPR_MPC_IC_ADR (0x231) |
| 1009 | #define SPR_Exxx_DBCR3 (0x231) |
| 1010 | #define SPR_IBAT5U (0x232) |
| 1011 | #define SPR_MPC_IC_DAT (0x232) |
| 1012 | #define SPR_Exxx_DBCNT (0x232) |
| 1013 | #define SPR_IBAT5L (0x233) |
| 1014 | #define SPR_IBAT6U (0x234) |
| 1015 | #define SPR_IBAT6L (0x235) |
| 1016 | #define SPR_IBAT7U (0x236) |
| 1017 | #define SPR_IBAT7L (0x237) |
| 1018 | #define SPR_DBAT4U (0x238) |
| 1019 | #define SPR_RCPU_L2U_MCR (0x238) |
| 1020 | #define SPR_MPC_DC_CST (0x238) |
| 1021 | #define SPR_Exxx_ALTCTXCR (0x238) |
| 1022 | #define SPR_DBAT4L (0x239) |
| 1023 | #define SPR_MPC_DC_ADR (0x239) |
| 1024 | #define SPR_DBAT5U (0x23A) |
| 1025 | #define SPR_BOOKE_MCSRR0 (0x23A) |
| 1026 | #define SPR_MPC_DC_DAT (0x23A) |
| 1027 | #define SPR_DBAT5L (0x23B) |
| 1028 | #define SPR_BOOKE_MCSRR1 (0x23B) |
| 1029 | #define SPR_DBAT6U (0x23C) |
| 1030 | #define SPR_BOOKE_MCSR (0x23C) |
| 1031 | #define SPR_DBAT6L (0x23D) |
| 1032 | #define SPR_Exxx_MCAR (0x23D) |
| 1033 | #define SPR_DBAT7U (0x23E) |
| 1034 | #define SPR_BOOKE_DSRR0 (0x23E) |
| 1035 | #define SPR_DBAT7L (0x23F) |
| 1036 | #define SPR_BOOKE_DSRR1 (0x23F) |
| 1037 | #define SPR_BOOKE_SPRG8 (0x25C) |
| 1038 | #define SPR_BOOKE_SPRG9 (0x25D) |
| 1039 | #define SPR_BOOKE_MAS0 (0x270) |
| 1040 | #define SPR_BOOKE_MAS1 (0x271) |
| 1041 | #define SPR_BOOKE_MAS2 (0x272) |
| 1042 | #define SPR_BOOKE_MAS3 (0x273) |
| 1043 | #define SPR_BOOKE_MAS4 (0x274) |
| 1044 | #define SPR_BOOKE_MAS5 (0x275) |
| 1045 | #define SPR_BOOKE_MAS6 (0x276) |
| 1046 | #define SPR_BOOKE_PID1 (0x279) |
| 1047 | #define SPR_BOOKE_PID2 (0x27A) |
| 1048 | #define SPR_MPC_DPDR (0x280) |
| 1049 | #define SPR_MPC_IMMR (0x288) |
| 1050 | #define SPR_BOOKE_TLB0CFG (0x2B0) |
| 1051 | #define SPR_BOOKE_TLB1CFG (0x2B1) |
| 1052 | #define SPR_BOOKE_TLB2CFG (0x2B2) |
| 1053 | #define SPR_BOOKE_TLB3CFG (0x2B3) |
| 1054 | #define SPR_BOOKE_EPR (0x2BE) |
| 1055 | #define SPR_PERF0 (0x300) |
| 1056 | #define SPR_RCPU_MI_RBA0 (0x300) |
| 1057 | #define SPR_MPC_MI_CTR (0x300) |
| 1058 | #define SPR_PERF1 (0x301) |
| 1059 | #define SPR_RCPU_MI_RBA1 (0x301) |
| 1060 | #define SPR_PERF2 (0x302) |
| 1061 | #define SPR_RCPU_MI_RBA2 (0x302) |
| 1062 | #define SPR_MPC_MI_AP (0x302) |
| 1063 | #define SPR_PERF3 (0x303) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1064 | #define SPR_620_PMC1R (0x303) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1065 | #define SPR_RCPU_MI_RBA3 (0x303) |
| 1066 | #define SPR_MPC_MI_EPN (0x303) |
| 1067 | #define SPR_PERF4 (0x304) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1068 | #define SPR_620_PMC2R (0x304) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1069 | #define SPR_PERF5 (0x305) |
| 1070 | #define SPR_MPC_MI_TWC (0x305) |
| 1071 | #define SPR_PERF6 (0x306) |
| 1072 | #define SPR_MPC_MI_RPN (0x306) |
| 1073 | #define SPR_PERF7 (0x307) |
| 1074 | #define SPR_PERF8 (0x308) |
| 1075 | #define SPR_RCPU_L2U_RBA0 (0x308) |
| 1076 | #define SPR_MPC_MD_CTR (0x308) |
| 1077 | #define SPR_PERF9 (0x309) |
| 1078 | #define SPR_RCPU_L2U_RBA1 (0x309) |
| 1079 | #define SPR_MPC_MD_CASID (0x309) |
| 1080 | #define SPR_PERFA (0x30A) |
| 1081 | #define SPR_RCPU_L2U_RBA2 (0x30A) |
| 1082 | #define SPR_MPC_MD_AP (0x30A) |
| 1083 | #define SPR_PERFB (0x30B) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1084 | #define SPR_620_MMCR0R (0x30B) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1085 | #define SPR_RCPU_L2U_RBA3 (0x30B) |
| 1086 | #define SPR_MPC_MD_EPN (0x30B) |
| 1087 | #define SPR_PERFC (0x30C) |
| 1088 | #define SPR_MPC_MD_TWB (0x30C) |
| 1089 | #define SPR_PERFD (0x30D) |
| 1090 | #define SPR_MPC_MD_TWC (0x30D) |
| 1091 | #define SPR_PERFE (0x30E) |
| 1092 | #define SPR_MPC_MD_RPN (0x30E) |
| 1093 | #define SPR_PERFF (0x30F) |
| 1094 | #define SPR_MPC_MD_TW (0x30F) |
| 1095 | #define SPR_UPERF0 (0x310) |
| 1096 | #define SPR_UPERF1 (0x311) |
| 1097 | #define SPR_UPERF2 (0x312) |
| 1098 | #define SPR_UPERF3 (0x313) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1099 | #define SPR_620_PMC1W (0x313) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1100 | #define SPR_UPERF4 (0x314) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1101 | #define SPR_620_PMC2W (0x314) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1102 | #define SPR_UPERF5 (0x315) |
| 1103 | #define SPR_UPERF6 (0x316) |
| 1104 | #define SPR_UPERF7 (0x317) |
| 1105 | #define SPR_UPERF8 (0x318) |
| 1106 | #define SPR_UPERF9 (0x319) |
| 1107 | #define SPR_UPERFA (0x31A) |
| 1108 | #define SPR_UPERFB (0x31B) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1109 | #define SPR_620_MMCR0W (0x31B) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1110 | #define SPR_UPERFC (0x31C) |
| 1111 | #define SPR_UPERFD (0x31D) |
| 1112 | #define SPR_UPERFE (0x31E) |
| 1113 | #define SPR_UPERFF (0x31F) |
| 1114 | #define SPR_RCPU_MI_RA0 (0x320) |
| 1115 | #define SPR_MPC_MI_DBCAM (0x320) |
| 1116 | #define SPR_RCPU_MI_RA1 (0x321) |
| 1117 | #define SPR_MPC_MI_DBRAM0 (0x321) |
| 1118 | #define SPR_RCPU_MI_RA2 (0x322) |
| 1119 | #define SPR_MPC_MI_DBRAM1 (0x322) |
| 1120 | #define SPR_RCPU_MI_RA3 (0x323) |
| 1121 | #define SPR_RCPU_L2U_RA0 (0x328) |
| 1122 | #define SPR_MPC_MD_DBCAM (0x328) |
| 1123 | #define SPR_RCPU_L2U_RA1 (0x329) |
| 1124 | #define SPR_MPC_MD_DBRAM0 (0x329) |
| 1125 | #define SPR_RCPU_L2U_RA2 (0x32A) |
| 1126 | #define SPR_MPC_MD_DBRAM1 (0x32A) |
| 1127 | #define SPR_RCPU_L2U_RA3 (0x32B) |
| 1128 | #define SPR_440_INV0 (0x370) |
| 1129 | #define SPR_440_INV1 (0x371) |
| 1130 | #define SPR_440_INV2 (0x372) |
| 1131 | #define SPR_440_INV3 (0x373) |
| 1132 | #define SPR_440_ITV0 (0x374) |
| 1133 | #define SPR_440_ITV1 (0x375) |
| 1134 | #define SPR_440_ITV2 (0x376) |
| 1135 | #define SPR_440_ITV3 (0x377) |
| 1136 | #define SPR_440_CCR1 (0x378) |
| 1137 | #define SPR_DCRIPR (0x37B) |
| 1138 | #define SPR_PPR (0x380) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1139 | #define SPR_750_GQR0 (0x390) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1140 | #define SPR_440_DNV0 (0x390) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1141 | #define SPR_750_GQR1 (0x391) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1142 | #define SPR_440_DNV1 (0x391) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1143 | #define SPR_750_GQR2 (0x392) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1144 | #define SPR_440_DNV2 (0x392) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1145 | #define SPR_750_GQR3 (0x393) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1146 | #define SPR_440_DNV3 (0x393) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1147 | #define SPR_750_GQR4 (0x394) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1148 | #define SPR_440_DTV0 (0x394) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1149 | #define SPR_750_GQR5 (0x395) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1150 | #define SPR_440_DTV1 (0x395) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1151 | #define SPR_750_GQR6 (0x396) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1152 | #define SPR_440_DTV2 (0x396) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1153 | #define SPR_750_GQR7 (0x397) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1154 | #define SPR_440_DTV3 (0x397) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1155 | #define SPR_750_THRM4 (0x398) |
| 1156 | #define SPR_750CL_HID2 (0x398) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1157 | #define SPR_440_DVLIM (0x398) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1158 | #define SPR_750_WPAR (0x399) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1159 | #define SPR_440_IVLIM (0x399) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1160 | #define SPR_750_DMAU (0x39A) |
| 1161 | #define SPR_750_DMAL (0x39B) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1162 | #define SPR_440_RSTCFG (0x39B) |
| 1163 | #define SPR_BOOKE_DCDBTRL (0x39C) |
| 1164 | #define SPR_BOOKE_DCDBTRH (0x39D) |
| 1165 | #define SPR_BOOKE_ICDBTRL (0x39E) |
| 1166 | #define SPR_BOOKE_ICDBTRH (0x39F) |
| 1167 | #define SPR_UMMCR2 (0x3A0) |
| 1168 | #define SPR_UPMC5 (0x3A1) |
| 1169 | #define SPR_UPMC6 (0x3A2) |
| 1170 | #define SPR_UBAMR (0x3A7) |
| 1171 | #define SPR_UMMCR0 (0x3A8) |
| 1172 | #define SPR_UPMC1 (0x3A9) |
| 1173 | #define SPR_UPMC2 (0x3AA) |
| 1174 | #define SPR_USIAR (0x3AB) |
| 1175 | #define SPR_UMMCR1 (0x3AC) |
| 1176 | #define SPR_UPMC3 (0x3AD) |
| 1177 | #define SPR_UPMC4 (0x3AE) |
| 1178 | #define SPR_USDA (0x3AF) |
| 1179 | #define SPR_40x_ZPR (0x3B0) |
| 1180 | #define SPR_BOOKE_MAS7 (0x3B0) |
| 1181 | #define SPR_620_PMR0 (0x3B0) |
| 1182 | #define SPR_MMCR2 (0x3B0) |
| 1183 | #define SPR_PMC5 (0x3B1) |
| 1184 | #define SPR_40x_PID (0x3B1) |
| 1185 | #define SPR_620_PMR1 (0x3B1) |
| 1186 | #define SPR_PMC6 (0x3B2) |
| 1187 | #define SPR_440_MMUCR (0x3B2) |
| 1188 | #define SPR_620_PMR2 (0x3B2) |
| 1189 | #define SPR_4xx_CCR0 (0x3B3) |
| 1190 | #define SPR_BOOKE_EPLC (0x3B3) |
| 1191 | #define SPR_620_PMR3 (0x3B3) |
| 1192 | #define SPR_405_IAC3 (0x3B4) |
| 1193 | #define SPR_BOOKE_EPSC (0x3B4) |
| 1194 | #define SPR_620_PMR4 (0x3B4) |
| 1195 | #define SPR_405_IAC4 (0x3B5) |
| 1196 | #define SPR_620_PMR5 (0x3B5) |
| 1197 | #define SPR_405_DVC1 (0x3B6) |
| 1198 | #define SPR_620_PMR6 (0x3B6) |
| 1199 | #define SPR_405_DVC2 (0x3B7) |
| 1200 | #define SPR_620_PMR7 (0x3B7) |
| 1201 | #define SPR_BAMR (0x3B7) |
| 1202 | #define SPR_MMCR0 (0x3B8) |
| 1203 | #define SPR_620_PMR8 (0x3B8) |
| 1204 | #define SPR_PMC1 (0x3B9) |
| 1205 | #define SPR_40x_SGR (0x3B9) |
| 1206 | #define SPR_620_PMR9 (0x3B9) |
| 1207 | #define SPR_PMC2 (0x3BA) |
| 1208 | #define SPR_40x_DCWR (0x3BA) |
| 1209 | #define SPR_620_PMRA (0x3BA) |
| 1210 | #define SPR_SIAR (0x3BB) |
| 1211 | #define SPR_405_SLER (0x3BB) |
| 1212 | #define SPR_620_PMRB (0x3BB) |
| 1213 | #define SPR_MMCR1 (0x3BC) |
| 1214 | #define SPR_405_SU0R (0x3BC) |
| 1215 | #define SPR_620_PMRC (0x3BC) |
| 1216 | #define SPR_401_SKR (0x3BC) |
| 1217 | #define SPR_PMC3 (0x3BD) |
| 1218 | #define SPR_405_DBCR1 (0x3BD) |
| 1219 | #define SPR_620_PMRD (0x3BD) |
| 1220 | #define SPR_PMC4 (0x3BE) |
| 1221 | #define SPR_620_PMRE (0x3BE) |
| 1222 | #define SPR_SDA (0x3BF) |
| 1223 | #define SPR_620_PMRF (0x3BF) |
| 1224 | #define SPR_403_VTBL (0x3CC) |
| 1225 | #define SPR_403_VTBU (0x3CD) |
| 1226 | #define SPR_DMISS (0x3D0) |
| 1227 | #define SPR_DCMP (0x3D1) |
| 1228 | #define SPR_HASH1 (0x3D2) |
| 1229 | #define SPR_HASH2 (0x3D3) |
| 1230 | #define SPR_BOOKE_ICDBDR (0x3D3) |
| 1231 | #define SPR_TLBMISS (0x3D4) |
| 1232 | #define SPR_IMISS (0x3D4) |
| 1233 | #define SPR_40x_ESR (0x3D4) |
| 1234 | #define SPR_PTEHI (0x3D5) |
| 1235 | #define SPR_ICMP (0x3D5) |
| 1236 | #define SPR_40x_DEAR (0x3D5) |
| 1237 | #define SPR_PTELO (0x3D6) |
| 1238 | #define SPR_RPA (0x3D6) |
| 1239 | #define SPR_40x_EVPR (0x3D6) |
| 1240 | #define SPR_L3PM (0x3D7) |
| 1241 | #define SPR_403_CDBCR (0x3D7) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1242 | #define SPR_L3ITCR0 (0x3D8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1243 | #define SPR_TCR (0x3D8) |
| 1244 | #define SPR_40x_TSR (0x3D8) |
| 1245 | #define SPR_IBR (0x3DA) |
| 1246 | #define SPR_40x_TCR (0x3DA) |
| 1247 | #define SPR_ESASRR (0x3DB) |
| 1248 | #define SPR_40x_PIT (0x3DB) |
| 1249 | #define SPR_403_TBL (0x3DC) |
| 1250 | #define SPR_403_TBU (0x3DD) |
| 1251 | #define SPR_SEBR (0x3DE) |
| 1252 | #define SPR_40x_SRR2 (0x3DE) |
| 1253 | #define SPR_SER (0x3DF) |
| 1254 | #define SPR_40x_SRR3 (0x3DF) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1255 | #define SPR_L3OHCR (0x3E8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1256 | #define SPR_L3ITCR1 (0x3E9) |
| 1257 | #define SPR_L3ITCR2 (0x3EA) |
| 1258 | #define SPR_L3ITCR3 (0x3EB) |
| 1259 | #define SPR_HID0 (0x3F0) |
| 1260 | #define SPR_40x_DBSR (0x3F0) |
| 1261 | #define SPR_HID1 (0x3F1) |
| 1262 | #define SPR_IABR (0x3F2) |
| 1263 | #define SPR_40x_DBCR0 (0x3F2) |
| 1264 | #define SPR_601_HID2 (0x3F2) |
| 1265 | #define SPR_Exxx_L1CSR0 (0x3F2) |
| 1266 | #define SPR_ICTRL (0x3F3) |
| 1267 | #define SPR_HID2 (0x3F3) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1268 | #define SPR_750CL_HID4 (0x3F3) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1269 | #define SPR_Exxx_L1CSR1 (0x3F3) |
| 1270 | #define SPR_440_DBDR (0x3F3) |
| 1271 | #define SPR_LDSTDB (0x3F4) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1272 | #define SPR_750_TDCL (0x3F4) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1273 | #define SPR_40x_IAC1 (0x3F4) |
| 1274 | #define SPR_MMUCSR0 (0x3F4) |
| 1275 | #define SPR_DABR (0x3F5) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1276 | #define DABR_MASK (~(target_ulong)0x7) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1277 | #define SPR_Exxx_BUCSR (0x3F5) |
| 1278 | #define SPR_40x_IAC2 (0x3F5) |
| 1279 | #define SPR_601_HID5 (0x3F5) |
| 1280 | #define SPR_40x_DAC1 (0x3F6) |
| 1281 | #define SPR_MSSCR0 (0x3F6) |
| 1282 | #define SPR_970_HID5 (0x3F6) |
| 1283 | #define SPR_MSSSR0 (0x3F7) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1284 | #define SPR_MSSCR1 (0x3F7) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1285 | #define SPR_DABRX (0x3F7) |
| 1286 | #define SPR_40x_DAC2 (0x3F7) |
| 1287 | #define SPR_MMUCFG (0x3F7) |
| 1288 | #define SPR_LDSTCR (0x3F8) |
| 1289 | #define SPR_L2PMCR (0x3F8) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1290 | #define SPR_750FX_HID2 (0x3F8) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1291 | #define SPR_620_BUSCSR (0x3F8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1292 | #define SPR_Exxx_L1FINV0 (0x3F8) |
| 1293 | #define SPR_L2CR (0x3F9) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1294 | #define SPR_620_L2CR (0x3F9) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1295 | #define SPR_L3CR (0x3FA) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1296 | #define SPR_750_TDCH (0x3FA) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1297 | #define SPR_IABR2 (0x3FA) |
| 1298 | #define SPR_40x_DCCR (0x3FA) |
j_mayer | 082c668 | 2007-11-19 13:22:47 +0000 | [diff] [blame] | 1299 | #define SPR_620_L2SR (0x3FA) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1300 | #define SPR_ICTC (0x3FB) |
| 1301 | #define SPR_40x_ICCR (0x3FB) |
| 1302 | #define SPR_THRM1 (0x3FC) |
| 1303 | #define SPR_403_PBL1 (0x3FC) |
| 1304 | #define SPR_SP (0x3FD) |
| 1305 | #define SPR_THRM2 (0x3FD) |
| 1306 | #define SPR_403_PBU1 (0x3FD) |
| 1307 | #define SPR_604_HID13 (0x3FD) |
| 1308 | #define SPR_LT (0x3FE) |
| 1309 | #define SPR_THRM3 (0x3FE) |
| 1310 | #define SPR_RCPU_FPECR (0x3FE) |
| 1311 | #define SPR_403_PBL2 (0x3FE) |
| 1312 | #define SPR_PIR (0x3FF) |
| 1313 | #define SPR_403_PBU2 (0x3FF) |
| 1314 | #define SPR_601_HID15 (0x3FF) |
| 1315 | #define SPR_604_HID15 (0x3FF) |
| 1316 | #define SPR_E500_SVR (0x3FF) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1317 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1318 | /*****************************************************************************/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1319 | /* Memory access type : |
| 1320 | * may be needed for precise access rights control and precise exceptions. |
| 1321 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1322 | enum { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1323 | /* 1 bit to define user level / supervisor access */ |
| 1324 | ACCESS_USER = 0x00, |
| 1325 | ACCESS_SUPER = 0x01, |
| 1326 | /* Type of instruction that generated the access */ |
| 1327 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 1328 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 1329 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 1330 | ACCESS_RES = 0x40, /* load/store with reservation */ |
| 1331 | ACCESS_EXT = 0x50, /* external access */ |
| 1332 | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 1333 | }; |
| 1334 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1335 | /* Hardware interruption sources: |
| 1336 | * all those exception can be raised simulteaneously |
| 1337 | */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1338 | /* Input pins definitions */ |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1339 | enum { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1340 | /* 6xx bus input pins */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1341 | PPC6xx_INPUT_HRESET = 0, |
| 1342 | PPC6xx_INPUT_SRESET = 1, |
| 1343 | PPC6xx_INPUT_CKSTP_IN = 2, |
| 1344 | PPC6xx_INPUT_MCP = 3, |
| 1345 | PPC6xx_INPUT_SMI = 4, |
| 1346 | PPC6xx_INPUT_INT = 5, |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1347 | PPC6xx_INPUT_TBEN = 6, |
| 1348 | PPC6xx_INPUT_WAKEUP = 7, |
| 1349 | PPC6xx_INPUT_NB, |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1350 | }; |
| 1351 | |
| 1352 | enum { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1353 | /* Embedded PowerPC input pins */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1354 | PPCBookE_INPUT_HRESET = 0, |
| 1355 | PPCBookE_INPUT_SRESET = 1, |
| 1356 | PPCBookE_INPUT_CKSTP_IN = 2, |
| 1357 | PPCBookE_INPUT_MCP = 3, |
| 1358 | PPCBookE_INPUT_SMI = 4, |
| 1359 | PPCBookE_INPUT_INT = 5, |
| 1360 | PPCBookE_INPUT_CINT = 6, |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1361 | PPCBookE_INPUT_NB, |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1362 | }; |
| 1363 | |
| 1364 | enum { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 1365 | /* PowerPC 40x input pins */ |
| 1366 | PPC40x_INPUT_RESET_CORE = 0, |
| 1367 | PPC40x_INPUT_RESET_CHIP = 1, |
| 1368 | PPC40x_INPUT_RESET_SYS = 2, |
| 1369 | PPC40x_INPUT_CINT = 3, |
| 1370 | PPC40x_INPUT_INT = 4, |
| 1371 | PPC40x_INPUT_HALT = 5, |
| 1372 | PPC40x_INPUT_DEBUG = 6, |
| 1373 | PPC40x_INPUT_NB, |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1374 | }; |
| 1375 | |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 1376 | enum { |
| 1377 | /* RCPU input pins */ |
| 1378 | PPCRCPU_INPUT_PORESET = 0, |
| 1379 | PPCRCPU_INPUT_HRESET = 1, |
| 1380 | PPCRCPU_INPUT_SRESET = 2, |
| 1381 | PPCRCPU_INPUT_IRQ0 = 3, |
| 1382 | PPCRCPU_INPUT_IRQ1 = 4, |
| 1383 | PPCRCPU_INPUT_IRQ2 = 5, |
| 1384 | PPCRCPU_INPUT_IRQ3 = 6, |
| 1385 | PPCRCPU_INPUT_IRQ4 = 7, |
| 1386 | PPCRCPU_INPUT_IRQ5 = 8, |
| 1387 | PPCRCPU_INPUT_IRQ6 = 9, |
| 1388 | PPCRCPU_INPUT_IRQ7 = 10, |
| 1389 | PPCRCPU_INPUT_NB, |
| 1390 | }; |
| 1391 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 1392 | #if defined(TARGET_PPC64) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 1393 | enum { |
| 1394 | /* PowerPC 970 input pins */ |
| 1395 | PPC970_INPUT_HRESET = 0, |
| 1396 | PPC970_INPUT_SRESET = 1, |
| 1397 | PPC970_INPUT_CKSTP = 2, |
| 1398 | PPC970_INPUT_TBEN = 3, |
| 1399 | PPC970_INPUT_MCP = 4, |
| 1400 | PPC970_INPUT_INT = 5, |
| 1401 | PPC970_INPUT_THINT = 6, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 1402 | PPC970_INPUT_NB, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 1403 | }; |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 1404 | #endif |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 1405 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1406 | /* Hardware exceptions definitions */ |
| 1407 | enum { |
| 1408 | /* External hardware exception sources */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 1409 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1410 | PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ |
| 1411 | PPC_INTERRUPT_MCK, /* Machine check exception */ |
| 1412 | PPC_INTERRUPT_EXT, /* External interrupt */ |
| 1413 | PPC_INTERRUPT_SMI, /* System management interrupt */ |
| 1414 | PPC_INTERRUPT_CEXT, /* Critical external interrupt */ |
| 1415 | PPC_INTERRUPT_DEBUG, /* External debug exception */ |
| 1416 | PPC_INTERRUPT_THERM, /* Thermal exception */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1417 | /* Internal hardware exception sources */ |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1418 | PPC_INTERRUPT_DECR, /* Decrementer exception */ |
| 1419 | PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ |
| 1420 | PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ |
| 1421 | PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ |
| 1422 | PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ |
| 1423 | PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ |
| 1424 | PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ |
| 1425 | PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1426 | }; |
| 1427 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1428 | /*****************************************************************************/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1429 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1430 | #endif /* !defined (__CPU_PPC_H__) */ |