blob: 758fa9f2ca45a0d5097414b646daa6db50882a4a [file] [log] [blame]
bellardab93bbe2003-08-10 21:35:13 +00001/*
2 * common defines for all CPUs
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardab93bbe2003-08-10 21:35:13 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
aurel32fad6cb12009-01-04 22:05:52 +000018 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
bellardab93bbe2003-08-10 21:35:13 +000019 */
20#ifndef CPU_DEFS_H
21#define CPU_DEFS_H
22
pbrook87ecb682007-11-17 17:14:51 +000023#ifndef NEED_CPU_H
24#error cpu.h included from common code
25#endif
26
bellardab93bbe2003-08-10 21:35:13 +000027#include "config.h"
28#include <setjmp.h>
bellarded1c0bc2004-02-16 22:17:43 +000029#include <inttypes.h>
30#include "osdep.h"
aliguoric0ce9982008-11-25 22:13:57 +000031#include "sys-queue.h"
bellardab93bbe2003-08-10 21:35:13 +000032
bellard35b66fc2004-01-24 15:26:06 +000033#ifndef TARGET_LONG_BITS
34#error TARGET_LONG_BITS must be defined before including this header
35#endif
36
ths5fafdf22007-09-16 21:08:06 +000037#ifndef TARGET_PHYS_ADDR_BITS
bellard4f2ac232004-04-26 19:44:02 +000038#if TARGET_LONG_BITS >= HOST_LONG_BITS
bellardab6d9602004-04-25 21:25:15 +000039#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
bellard4f2ac232004-04-26 19:44:02 +000040#else
41#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
42#endif
bellardab6d9602004-04-25 21:25:15 +000043#endif
44
bellard35b66fc2004-01-24 15:26:06 +000045#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
46
bellardab6d9602004-04-25 21:25:15 +000047/* target_ulong is the type of a virtual address */
bellard35b66fc2004-01-24 15:26:06 +000048#if TARGET_LONG_SIZE == 4
49typedef int32_t target_long;
50typedef uint32_t target_ulong;
bellardc27004e2005-01-03 23:35:10 +000051#define TARGET_FMT_lx "%08x"
j_mayerb62b4612007-04-04 07:58:14 +000052#define TARGET_FMT_ld "%d"
j_mayer71c8b8f2007-09-19 05:46:03 +000053#define TARGET_FMT_lu "%u"
bellard35b66fc2004-01-24 15:26:06 +000054#elif TARGET_LONG_SIZE == 8
55typedef int64_t target_long;
56typedef uint64_t target_ulong;
bellard26a76462006-06-25 18:15:32 +000057#define TARGET_FMT_lx "%016" PRIx64
j_mayerb62b4612007-04-04 07:58:14 +000058#define TARGET_FMT_ld "%" PRId64
j_mayer71c8b8f2007-09-19 05:46:03 +000059#define TARGET_FMT_lu "%" PRIu64
bellard35b66fc2004-01-24 15:26:06 +000060#else
61#error TARGET_LONG_SIZE undefined
62#endif
63
bellardab6d9602004-04-25 21:25:15 +000064/* target_phys_addr_t is the type of a physical address (its size can
bellard4f2ac232004-04-26 19:44:02 +000065 be different from 'target_ulong'). We have sizeof(target_phys_addr)
66 = max(sizeof(unsigned long),
67 sizeof(size_of_target_physical_address)) because we must pass a
68 host pointer to memory operations in some cases */
69
bellardab6d9602004-04-25 21:25:15 +000070#if TARGET_PHYS_ADDR_BITS == 32
71typedef uint32_t target_phys_addr_t;
j_mayerba13c432007-04-14 12:15:36 +000072#define TARGET_FMT_plx "%08x"
bellardab6d9602004-04-25 21:25:15 +000073#elif TARGET_PHYS_ADDR_BITS == 64
74typedef uint64_t target_phys_addr_t;
j_mayerba13c432007-04-14 12:15:36 +000075#define TARGET_FMT_plx "%016" PRIx64
bellardab6d9602004-04-25 21:25:15 +000076#else
77#error TARGET_PHYS_ADDR_BITS undefined
78#endif
79
bellardf193c792004-03-21 17:06:25 +000080#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
81
bellard2be00712005-07-02 22:09:27 +000082#define EXCP_INTERRUPT 0x10000 /* async interruption */
83#define EXCP_HLT 0x10001 /* hlt instruction reached */
84#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
bellard5a1e3cf2005-11-23 21:02:53 +000085#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
bellardab93bbe2003-08-10 21:35:13 +000086
bellarda316d332005-11-20 10:32:34 +000087#define TB_JMP_CACHE_BITS 12
88#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
89
pbrookb362e5e2006-11-12 20:40:55 +000090/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
91 addresses on the same page. The top bits are the same. This allows
92 TLB invalidation to quickly clear a subset of the hash table. */
93#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
94#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
95#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
96#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
97
bellard84b7b8e2005-11-28 21:19:04 +000098#define CPU_TLB_BITS 8
99#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
bellardab93bbe2003-08-10 21:35:13 +0000100
bellardd6564692008-01-31 09:22:27 +0000101#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
102#define CPU_TLB_ENTRY_BITS 4
103#else
104#define CPU_TLB_ENTRY_BITS 5
105#endif
106
bellardab93bbe2003-08-10 21:35:13 +0000107typedef struct CPUTLBEntry {
pbrook0f459d12008-06-09 00:20:13 +0000108 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
109 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
110 go directly to ram.
bellarddb8d7462003-10-27 21:12:17 +0000111 bit 3 : indicates that the entry is invalid
112 bit 2..0 : zero
113 */
ths5fafdf22007-09-16 21:08:06 +0000114 target_ulong addr_read;
115 target_ulong addr_write;
116 target_ulong addr_code;
pbrook0f459d12008-06-09 00:20:13 +0000117 /* Addend to virtual address to get physical address. IO accesses
pbrookee50add2008-11-29 13:33:23 +0000118 use the corresponding iotlb value. */
bellardd6564692008-01-31 09:22:27 +0000119#if TARGET_PHYS_ADDR_BITS == 64
120 /* on i386 Linux make sure it is aligned */
121 target_phys_addr_t addend __attribute__((aligned(8)));
122#else
ths5fafdf22007-09-16 21:08:06 +0000123 target_phys_addr_t addend;
bellardd6564692008-01-31 09:22:27 +0000124#endif
125 /* padding to get a power of two size */
126 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
127 (sizeof(target_ulong) * 3 +
128 ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
129 sizeof(target_phys_addr_t))];
bellardab93bbe2003-08-10 21:35:13 +0000130} CPUTLBEntry;
131
pbrook2e70f6e2008-06-29 01:03:05 +0000132#ifdef WORDS_BIGENDIAN
133typedef struct icount_decr_u16 {
134 uint16_t high;
135 uint16_t low;
136} icount_decr_u16;
137#else
138typedef struct icount_decr_u16 {
139 uint16_t low;
140 uint16_t high;
141} icount_decr_u16;
142#endif
143
aliguori7ba1e612008-11-05 16:04:33 +0000144struct kvm_run;
145struct KVMState;
146
aliguoria1d1bb32008-11-18 20:07:32 +0000147typedef struct CPUBreakpoint {
148 target_ulong pc;
149 int flags; /* BP_* */
aliguoric0ce9982008-11-25 22:13:57 +0000150 TAILQ_ENTRY(CPUBreakpoint) entry;
aliguoria1d1bb32008-11-18 20:07:32 +0000151} CPUBreakpoint;
152
153typedef struct CPUWatchpoint {
154 target_ulong vaddr;
155 target_ulong len_mask;
156 int flags; /* BP_* */
aliguoric0ce9982008-11-25 22:13:57 +0000157 TAILQ_ENTRY(CPUWatchpoint) entry;
aliguoria1d1bb32008-11-18 20:07:32 +0000158} CPUWatchpoint;
159
blueswir1a20e31d2008-04-08 19:29:54 +0000160#define CPU_TEMP_BUF_NLONGS 128
bellarda316d332005-11-20 10:32:34 +0000161#define CPU_COMMON \
162 struct TranslationBlock *current_tb; /* currently executing TB */ \
163 /* soft mmu support */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000164 /* in order to avoid passing too many arguments to the MMIO \
165 helpers, we store some rarely used information in the CPU \
bellarda316d332005-11-20 10:32:34 +0000166 context) */ \
pbrook2e70f6e2008-06-29 01:03:05 +0000167 unsigned long mem_io_pc; /* host pc at which the memory was \
168 accessed */ \
169 target_ulong mem_io_vaddr; /* target virtual addr at which the \
170 memory was accessed */ \
pbrook9656f322008-07-01 20:01:19 +0000171 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
172 uint32_t interrupt_request; \
ths623a9302007-10-28 19:45:05 +0000173 /* The meaning of the MMU modes is defined in the target code. */ \
j_mayer6fa4cea2007-04-05 06:43:27 +0000174 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
pbrook0f459d12008-06-09 00:20:13 +0000175 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
bellarda316d332005-11-20 10:32:34 +0000176 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
blueswir1a20e31d2008-04-08 19:29:54 +0000177 /* buffer for temporaries in the code generator */ \
178 long temp_buf[CPU_TEMP_BUF_NLONGS]; \
bellarda316d332005-11-20 10:32:34 +0000179 \
pbrook2e70f6e2008-06-29 01:03:05 +0000180 int64_t icount_extra; /* Instructions until next timer event. */ \
181 /* Number of cycles left, with interrupt flag in high bit. \
182 This allows a single read-compare-cbranch-write sequence to test \
183 for both decrementer underflow and exceptions. */ \
184 union { \
185 uint32_t u32; \
186 icount_decr_u16 u16; \
187 } icount_decr; \
188 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
189 \
bellarda316d332005-11-20 10:32:34 +0000190 /* from this point: preserved by CPU reset */ \
191 /* ice debug support */ \
aliguoric0ce9982008-11-25 22:13:57 +0000192 TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
bellarda316d332005-11-20 10:32:34 +0000193 int singlestep_enabled; \
194 \
aliguoric0ce9982008-11-25 22:13:57 +0000195 TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
aliguoria1d1bb32008-11-18 20:07:32 +0000196 CPUWatchpoint *watchpoint_hit; \
pbrook6658ffb2007-03-16 23:58:11 +0000197 \
pbrook56aebc82008-10-11 17:55:29 +0000198 struct GDBRegisterState *gdb_regs; \
199 \
bellard9133e392008-05-29 10:08:06 +0000200 /* Core interrupt code */ \
201 jmp_buf jmp_env; \
202 int exception_index; \
203 \
bellard6a00d602005-11-21 23:25:50 +0000204 void *next_cpu; /* next CPU sharing TB cache */ \
205 int cpu_index; /* CPU index (informative) */ \
pbrookd5975362008-06-07 20:50:51 +0000206 int running; /* Nonzero if cpu is currently running(usermode). */ \
bellarda316d332005-11-20 10:32:34 +0000207 /* user data */ \
ths01ba9812007-12-09 02:22:57 +0000208 void *opaque; \
209 \
aliguori7ba1e612008-11-05 16:04:33 +0000210 const char *cpu_model_str; \
211 struct KVMState *kvm_state; \
212 struct kvm_run *kvm_run; \
213 int kvm_fd;
bellarda316d332005-11-20 10:32:34 +0000214
bellardab93bbe2003-08-10 21:35:13 +0000215#endif