bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * common defines for all CPUs |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
aurel32 | fad6cb1 | 2009-01-04 22:05:52 +0000 | [diff] [blame] | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 19 | */ |
| 20 | #ifndef CPU_DEFS_H |
| 21 | #define CPU_DEFS_H |
| 22 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 23 | #ifndef NEED_CPU_H |
| 24 | #error cpu.h included from common code |
| 25 | #endif |
| 26 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 27 | #include "config.h" |
| 28 | #include <setjmp.h> |
bellard | ed1c0bc | 2004-02-16 22:17:43 +0000 | [diff] [blame] | 29 | #include <inttypes.h> |
| 30 | #include "osdep.h" |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 31 | #include "sys-queue.h" |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 32 | |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 33 | #ifndef TARGET_LONG_BITS |
| 34 | #error TARGET_LONG_BITS must be defined before including this header |
| 35 | #endif |
| 36 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 37 | #ifndef TARGET_PHYS_ADDR_BITS |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 38 | #if TARGET_LONG_BITS >= HOST_LONG_BITS |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 39 | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 40 | #else |
| 41 | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS |
| 42 | #endif |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 43 | #endif |
| 44 | |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 45 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
| 46 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 47 | /* target_ulong is the type of a virtual address */ |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 48 | #if TARGET_LONG_SIZE == 4 |
| 49 | typedef int32_t target_long; |
| 50 | typedef uint32_t target_ulong; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 51 | #define TARGET_FMT_lx "%08x" |
j_mayer | b62b461 | 2007-04-04 07:58:14 +0000 | [diff] [blame] | 52 | #define TARGET_FMT_ld "%d" |
j_mayer | 71c8b8f | 2007-09-19 05:46:03 +0000 | [diff] [blame] | 53 | #define TARGET_FMT_lu "%u" |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 54 | #elif TARGET_LONG_SIZE == 8 |
| 55 | typedef int64_t target_long; |
| 56 | typedef uint64_t target_ulong; |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 57 | #define TARGET_FMT_lx "%016" PRIx64 |
j_mayer | b62b461 | 2007-04-04 07:58:14 +0000 | [diff] [blame] | 58 | #define TARGET_FMT_ld "%" PRId64 |
j_mayer | 71c8b8f | 2007-09-19 05:46:03 +0000 | [diff] [blame] | 59 | #define TARGET_FMT_lu "%" PRIu64 |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 60 | #else |
| 61 | #error TARGET_LONG_SIZE undefined |
| 62 | #endif |
| 63 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 64 | /* target_phys_addr_t is the type of a physical address (its size can |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 65 | be different from 'target_ulong'). We have sizeof(target_phys_addr) |
| 66 | = max(sizeof(unsigned long), |
| 67 | sizeof(size_of_target_physical_address)) because we must pass a |
| 68 | host pointer to memory operations in some cases */ |
| 69 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 70 | #if TARGET_PHYS_ADDR_BITS == 32 |
| 71 | typedef uint32_t target_phys_addr_t; |
j_mayer | ba13c43 | 2007-04-14 12:15:36 +0000 | [diff] [blame] | 72 | #define TARGET_FMT_plx "%08x" |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 73 | #elif TARGET_PHYS_ADDR_BITS == 64 |
| 74 | typedef uint64_t target_phys_addr_t; |
j_mayer | ba13c43 | 2007-04-14 12:15:36 +0000 | [diff] [blame] | 75 | #define TARGET_FMT_plx "%016" PRIx64 |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 76 | #else |
| 77 | #error TARGET_PHYS_ADDR_BITS undefined |
| 78 | #endif |
| 79 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 80 | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
| 81 | |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 82 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
| 83 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
| 84 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 85 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 86 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 87 | #define TB_JMP_CACHE_BITS 12 |
| 88 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
| 89 | |
pbrook | b362e5e | 2006-11-12 20:40:55 +0000 | [diff] [blame] | 90 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
| 91 | addresses on the same page. The top bits are the same. This allows |
| 92 | TLB invalidation to quickly clear a subset of the hash table. */ |
| 93 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
| 94 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
| 95 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
| 96 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) |
| 97 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 98 | #define CPU_TLB_BITS 8 |
| 99 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 100 | |
bellard | d656469 | 2008-01-31 09:22:27 +0000 | [diff] [blame] | 101 | #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 |
| 102 | #define CPU_TLB_ENTRY_BITS 4 |
| 103 | #else |
| 104 | #define CPU_TLB_ENTRY_BITS 5 |
| 105 | #endif |
| 106 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 107 | typedef struct CPUTLBEntry { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 108 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
| 109 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not |
| 110 | go directly to ram. |
bellard | db8d746 | 2003-10-27 21:12:17 +0000 | [diff] [blame] | 111 | bit 3 : indicates that the entry is invalid |
| 112 | bit 2..0 : zero |
| 113 | */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 114 | target_ulong addr_read; |
| 115 | target_ulong addr_write; |
| 116 | target_ulong addr_code; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 117 | /* Addend to virtual address to get physical address. IO accesses |
pbrook | ee50add | 2008-11-29 13:33:23 +0000 | [diff] [blame] | 118 | use the corresponding iotlb value. */ |
bellard | d656469 | 2008-01-31 09:22:27 +0000 | [diff] [blame] | 119 | #if TARGET_PHYS_ADDR_BITS == 64 |
| 120 | /* on i386 Linux make sure it is aligned */ |
| 121 | target_phys_addr_t addend __attribute__((aligned(8))); |
| 122 | #else |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 123 | target_phys_addr_t addend; |
bellard | d656469 | 2008-01-31 09:22:27 +0000 | [diff] [blame] | 124 | #endif |
| 125 | /* padding to get a power of two size */ |
| 126 | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - |
| 127 | (sizeof(target_ulong) * 3 + |
| 128 | ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + |
| 129 | sizeof(target_phys_addr_t))]; |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 130 | } CPUTLBEntry; |
| 131 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 132 | #ifdef WORDS_BIGENDIAN |
| 133 | typedef struct icount_decr_u16 { |
| 134 | uint16_t high; |
| 135 | uint16_t low; |
| 136 | } icount_decr_u16; |
| 137 | #else |
| 138 | typedef struct icount_decr_u16 { |
| 139 | uint16_t low; |
| 140 | uint16_t high; |
| 141 | } icount_decr_u16; |
| 142 | #endif |
| 143 | |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 144 | struct kvm_run; |
| 145 | struct KVMState; |
| 146 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 147 | typedef struct CPUBreakpoint { |
| 148 | target_ulong pc; |
| 149 | int flags; /* BP_* */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 150 | TAILQ_ENTRY(CPUBreakpoint) entry; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 151 | } CPUBreakpoint; |
| 152 | |
| 153 | typedef struct CPUWatchpoint { |
| 154 | target_ulong vaddr; |
| 155 | target_ulong len_mask; |
| 156 | int flags; /* BP_* */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 157 | TAILQ_ENTRY(CPUWatchpoint) entry; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 158 | } CPUWatchpoint; |
| 159 | |
blueswir1 | a20e31d | 2008-04-08 19:29:54 +0000 | [diff] [blame] | 160 | #define CPU_TEMP_BUF_NLONGS 128 |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 161 | #define CPU_COMMON \ |
| 162 | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
| 163 | /* soft mmu support */ \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 164 | /* in order to avoid passing too many arguments to the MMIO \ |
| 165 | helpers, we store some rarely used information in the CPU \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 166 | context) */ \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 167 | unsigned long mem_io_pc; /* host pc at which the memory was \ |
| 168 | accessed */ \ |
| 169 | target_ulong mem_io_vaddr; /* target virtual addr at which the \ |
| 170 | memory was accessed */ \ |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 171 | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ |
| 172 | uint32_t interrupt_request; \ |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 173 | /* The meaning of the MMU modes is defined in the target code. */ \ |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 174 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 175 | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 176 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
blueswir1 | a20e31d | 2008-04-08 19:29:54 +0000 | [diff] [blame] | 177 | /* buffer for temporaries in the code generator */ \ |
| 178 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 179 | \ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 180 | int64_t icount_extra; /* Instructions until next timer event. */ \ |
| 181 | /* Number of cycles left, with interrupt flag in high bit. \ |
| 182 | This allows a single read-compare-cbranch-write sequence to test \ |
| 183 | for both decrementer underflow and exceptions. */ \ |
| 184 | union { \ |
| 185 | uint32_t u32; \ |
| 186 | icount_decr_u16 u16; \ |
| 187 | } icount_decr; \ |
| 188 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ |
| 189 | \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 190 | /* from this point: preserved by CPU reset */ \ |
| 191 | /* ice debug support */ \ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 192 | TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 193 | int singlestep_enabled; \ |
| 194 | \ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 195 | TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 196 | CPUWatchpoint *watchpoint_hit; \ |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 197 | \ |
pbrook | 56aebc8 | 2008-10-11 17:55:29 +0000 | [diff] [blame] | 198 | struct GDBRegisterState *gdb_regs; \ |
| 199 | \ |
bellard | 9133e39 | 2008-05-29 10:08:06 +0000 | [diff] [blame] | 200 | /* Core interrupt code */ \ |
| 201 | jmp_buf jmp_env; \ |
| 202 | int exception_index; \ |
| 203 | \ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 204 | void *next_cpu; /* next CPU sharing TB cache */ \ |
| 205 | int cpu_index; /* CPU index (informative) */ \ |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 206 | int running; /* Nonzero if cpu is currently running(usermode). */ \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 207 | /* user data */ \ |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 208 | void *opaque; \ |
| 209 | \ |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 210 | const char *cpu_model_str; \ |
| 211 | struct KVMState *kvm_state; \ |
| 212 | struct kvm_run *kvm_run; \ |
| 213 | int kvm_fd; |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 214 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 215 | #endif |