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bellard80cabfa2004-03-14 12:20:30 +00001/*
2 * QEMU PC keyboard emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard80cabfa2004-03-14 12:20:30 +00004 * Copyright (c) 2003 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard80cabfa2004-03-14 12:20:30 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
pbrook87ecb682007-11-17 17:14:51 +000024#include "hw.h"
25#include "isa.h"
26#include "pc.h"
27#include "ps2.h"
28#include "sysemu.h"
bellard80cabfa2004-03-14 12:20:30 +000029
30/* debug PC keyboard */
31//#define DEBUG_KBD
Blue Swirlc86d2c22010-05-22 07:59:06 +000032#ifdef DEBUG_KBD
33#define DPRINTF(fmt, ...) \
34 do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
35#else
36#define DPRINTF(fmt, ...)
37#endif
bellard80cabfa2004-03-14 12:20:30 +000038
bellard80cabfa2004-03-14 12:20:30 +000039/* Keyboard Controller Commands */
40#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
41#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
42#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
43#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
44#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
45#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
46#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
47#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
48#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
49#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
50#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
51#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
52#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
53#define KBD_CCMD_WRITE_OBUF 0xD2
54#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
55 initiated by the auxiliary device */
56#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
57#define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
58#define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
Bernhard Kohl5ccaa4c2010-08-19 14:52:12 +020059#define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */
60#define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */
61#define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */
bellard80cabfa2004-03-14 12:20:30 +000062
63/* Keyboard Commands */
64#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
65#define KBD_CMD_ECHO 0xEE
66#define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
67#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
68#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
69#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
70#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
71#define KBD_CMD_RESET 0xFF /* Reset */
72
73/* Keyboard Replies */
74#define KBD_REPLY_POR 0xAA /* Power on reset */
75#define KBD_REPLY_ACK 0xFA /* Command ACK */
76#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
77
78/* Status Register Bits */
79#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
80#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
81#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
82#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
83#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
84#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
85#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
86#define KBD_STAT_PERR 0x80 /* Parity error */
87
88/* Controller Mode Register Bits */
89#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
90#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
91#define KBD_MODE_SYS 0x04 /* The system flag (?) */
92#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
93#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
94#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
95#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
96#define KBD_MODE_RFU 0x80
97
Blue Swirl956a3e62010-05-22 07:59:01 +000098/* Output Port Bits */
99#define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */
100#define KBD_OUT_A20 0x02 /* x86 only */
101#define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */
102#define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */
103
bellard80cabfa2004-03-14 12:20:30 +0000104/* Mouse Commands */
105#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
106#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
107#define AUX_SET_RES 0xE8 /* Set resolution */
108#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
109#define AUX_SET_STREAM 0xEA /* Set stream mode */
110#define AUX_POLL 0xEB /* Poll */
111#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
112#define AUX_SET_WRAP 0xEE /* Set wrap mode */
113#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
114#define AUX_GET_TYPE 0xF2 /* Get type */
115#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
116#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
117#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
118#define AUX_SET_DEFAULT 0xF6
119#define AUX_RESET 0xFF /* Reset aux device */
120#define AUX_ACK 0xFA /* Command byte ACK. */
121
122#define MOUSE_STATUS_REMOTE 0x40
123#define MOUSE_STATUS_ENABLED 0x20
124#define MOUSE_STATUS_SCALE21 0x10
125
bellarddaa57962005-11-26 10:14:03 +0000126#define KBD_PENDING_KBD 1
127#define KBD_PENDING_AUX 2
bellard80cabfa2004-03-14 12:20:30 +0000128
129typedef struct KBDState {
bellard80cabfa2004-03-14 12:20:30 +0000130 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
131 uint8_t status;
132 uint8_t mode;
Blue Swirl956a3e62010-05-22 07:59:01 +0000133 uint8_t outport;
bellarddaa57962005-11-26 10:14:03 +0000134 /* Bitmask of devices with data available. */
pbrook7783e9f2006-04-08 14:12:31 +0000135 uint8_t pending;
bellarddaa57962005-11-26 10:14:03 +0000136 void *kbd;
137 void *mouse;
thsb7678d92007-02-18 00:08:44 +0000138
pbrookd537cf62007-04-07 18:14:41 +0000139 qemu_irq irq_kbd;
140 qemu_irq irq_mouse;
Blue Swirl956a3e62010-05-22 07:59:01 +0000141 qemu_irq *a20_out;
Anthony Liguoric227f092009-10-01 16:12:16 -0500142 target_phys_addr_t mask;
bellard80cabfa2004-03-14 12:20:30 +0000143} KBDState;
144
bellard80cabfa2004-03-14 12:20:30 +0000145/* update irq and KBD_STAT_[MOUSE_]OBF */
146/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
147 incorrect, but it avoids having to simulate exact delays */
148static void kbd_update_irq(KBDState *s)
149{
thsb7678d92007-02-18 00:08:44 +0000150 int irq_kbd_level, irq_mouse_level;
bellard80cabfa2004-03-14 12:20:30 +0000151
thsb7678d92007-02-18 00:08:44 +0000152 irq_kbd_level = 0;
153 irq_mouse_level = 0;
bellard80cabfa2004-03-14 12:20:30 +0000154 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
Blue Swirl956a3e62010-05-22 07:59:01 +0000155 s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF);
bellarddaa57962005-11-26 10:14:03 +0000156 if (s->pending) {
bellard80cabfa2004-03-14 12:20:30 +0000157 s->status |= KBD_STAT_OBF;
Blue Swirl956a3e62010-05-22 07:59:01 +0000158 s->outport |= KBD_OUT_OBF;
thsb92bb992007-04-16 17:20:48 +0000159 /* kbd data takes priority over aux data. */
bellarddaa57962005-11-26 10:14:03 +0000160 if (s->pending == KBD_PENDING_AUX) {
bellard80cabfa2004-03-14 12:20:30 +0000161 s->status |= KBD_STAT_MOUSE_OBF;
Blue Swirl956a3e62010-05-22 07:59:01 +0000162 s->outport |= KBD_OUT_MOUSE_OBF;
bellard80cabfa2004-03-14 12:20:30 +0000163 if (s->mode & KBD_MODE_MOUSE_INT)
thsb7678d92007-02-18 00:08:44 +0000164 irq_mouse_level = 1;
bellard80cabfa2004-03-14 12:20:30 +0000165 } else {
ths5fafdf22007-09-16 21:08:06 +0000166 if ((s->mode & KBD_MODE_KBD_INT) &&
bellard80cabfa2004-03-14 12:20:30 +0000167 !(s->mode & KBD_MODE_DISABLE_KBD))
thsb7678d92007-02-18 00:08:44 +0000168 irq_kbd_level = 1;
bellard80cabfa2004-03-14 12:20:30 +0000169 }
170 }
pbrookd537cf62007-04-07 18:14:41 +0000171 qemu_set_irq(s->irq_kbd, irq_kbd_level);
172 qemu_set_irq(s->irq_mouse, irq_mouse_level);
bellard80cabfa2004-03-14 12:20:30 +0000173}
174
bellarddaa57962005-11-26 10:14:03 +0000175static void kbd_update_kbd_irq(void *opaque, int level)
bellard80cabfa2004-03-14 12:20:30 +0000176{
bellarddaa57962005-11-26 10:14:03 +0000177 KBDState *s = (KBDState *)opaque;
bellard80cabfa2004-03-14 12:20:30 +0000178
bellarddaa57962005-11-26 10:14:03 +0000179 if (level)
180 s->pending |= KBD_PENDING_KBD;
bellard80cabfa2004-03-14 12:20:30 +0000181 else
bellarddaa57962005-11-26 10:14:03 +0000182 s->pending &= ~KBD_PENDING_KBD;
bellard80cabfa2004-03-14 12:20:30 +0000183 kbd_update_irq(s);
184}
185
bellarddaa57962005-11-26 10:14:03 +0000186static void kbd_update_aux_irq(void *opaque, int level)
bellard80cabfa2004-03-14 12:20:30 +0000187{
bellarddaa57962005-11-26 10:14:03 +0000188 KBDState *s = (KBDState *)opaque;
189
190 if (level)
191 s->pending |= KBD_PENDING_AUX;
192 else
193 s->pending &= ~KBD_PENDING_AUX;
194 kbd_update_irq(s);
bellard80cabfa2004-03-14 12:20:30 +0000195}
196
bellardb41a2cd2004-03-14 21:46:48 +0000197static uint32_t kbd_read_status(void *opaque, uint32_t addr)
bellard80cabfa2004-03-14 12:20:30 +0000198{
bellardb41a2cd2004-03-14 21:46:48 +0000199 KBDState *s = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000200 int val;
201 val = s->status;
Blue Swirlc86d2c22010-05-22 07:59:06 +0000202 DPRINTF("kbd: read status=0x%02x\n", val);
bellard80cabfa2004-03-14 12:20:30 +0000203 return val;
204}
205
bellarddaa57962005-11-26 10:14:03 +0000206static void kbd_queue(KBDState *s, int b, int aux)
207{
208 if (aux)
209 ps2_queue(s->mouse, b);
210 else
211 ps2_queue(s->kbd, b);
212}
213
Blue Swirl956a3e62010-05-22 07:59:01 +0000214static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
215{
216 KBDState *s = opaque;
217
Blue Swirlc86d2c22010-05-22 07:59:06 +0000218 DPRINTF("kbd: write outport=0x%02x\n", val);
Blue Swirl956a3e62010-05-22 07:59:01 +0000219 s->outport = val;
220 if (s->a20_out) {
221 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
222 }
223 if (!(val & 1)) {
224 qemu_system_reset_request();
225 }
226}
227
228static uint32_t ioport92_read(void *opaque, uint32_t addr)
229{
230 KBDState *s = opaque;
Blue Swirlc86d2c22010-05-22 07:59:06 +0000231 uint32_t ret;
Blue Swirl956a3e62010-05-22 07:59:01 +0000232
Blue Swirlc86d2c22010-05-22 07:59:06 +0000233 ret = s->outport;
234 DPRINTF("kbd: read outport=0x%02x\n", ret);
235 return ret;
Blue Swirl956a3e62010-05-22 07:59:01 +0000236}
237
bellardb41a2cd2004-03-14 21:46:48 +0000238static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
bellard80cabfa2004-03-14 12:20:30 +0000239{
bellardb41a2cd2004-03-14 21:46:48 +0000240 KBDState *s = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000241
Blue Swirlc86d2c22010-05-22 07:59:06 +0000242 DPRINTF("kbd: write cmd=0x%02x\n", val);
Bernhard Kohl5ccaa4c2010-08-19 14:52:12 +0200243
244 /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed
245 * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE
246 * command specify the output port bits to be pulsed.
247 * 0: Bit should be pulsed. 1: Bit should not be modified.
248 * The only useful version of this command is pulsing bit 0,
249 * which does a CPU reset.
250 */
251 if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) {
252 if(!(val & 1))
253 val = KBD_CCMD_RESET;
254 else
255 val = KBD_CCMD_NO_OP;
256 }
257
bellard80cabfa2004-03-14 12:20:30 +0000258 switch(val) {
259 case KBD_CCMD_READ_MODE:
balrog889bec62008-07-19 14:16:20 +0000260 kbd_queue(s, s->mode, 0);
bellard80cabfa2004-03-14 12:20:30 +0000261 break;
262 case KBD_CCMD_WRITE_MODE:
263 case KBD_CCMD_WRITE_OBUF:
264 case KBD_CCMD_WRITE_AUX_OBUF:
265 case KBD_CCMD_WRITE_MOUSE:
266 case KBD_CCMD_WRITE_OUTPORT:
267 s->write_cmd = val;
268 break;
269 case KBD_CCMD_MOUSE_DISABLE:
270 s->mode |= KBD_MODE_DISABLE_MOUSE;
271 break;
272 case KBD_CCMD_MOUSE_ENABLE:
273 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
274 break;
275 case KBD_CCMD_TEST_MOUSE:
276 kbd_queue(s, 0x00, 0);
277 break;
278 case KBD_CCMD_SELF_TEST:
279 s->status |= KBD_STAT_SELFTEST;
280 kbd_queue(s, 0x55, 0);
281 break;
282 case KBD_CCMD_KBD_TEST:
283 kbd_queue(s, 0x00, 0);
284 break;
285 case KBD_CCMD_KBD_DISABLE:
286 s->mode |= KBD_MODE_DISABLE_KBD;
287 kbd_update_irq(s);
288 break;
289 case KBD_CCMD_KBD_ENABLE:
290 s->mode &= ~KBD_MODE_DISABLE_KBD;
291 kbd_update_irq(s);
292 break;
293 case KBD_CCMD_READ_INPORT:
294 kbd_queue(s, 0x00, 0);
295 break;
296 case KBD_CCMD_READ_OUTPORT:
Blue Swirl956a3e62010-05-22 07:59:01 +0000297 kbd_queue(s, s->outport, 0);
bellard80cabfa2004-03-14 12:20:30 +0000298 break;
bellard80cabfa2004-03-14 12:20:30 +0000299 case KBD_CCMD_ENABLE_A20:
Blue Swirl956a3e62010-05-22 07:59:01 +0000300 if (s->a20_out) {
301 qemu_irq_raise(*s->a20_out);
302 }
303 s->outport |= KBD_OUT_A20;
bellard80cabfa2004-03-14 12:20:30 +0000304 break;
305 case KBD_CCMD_DISABLE_A20:
Blue Swirl956a3e62010-05-22 07:59:01 +0000306 if (s->a20_out) {
307 qemu_irq_lower(*s->a20_out);
308 }
309 s->outport &= ~KBD_OUT_A20;
bellard80cabfa2004-03-14 12:20:30 +0000310 break;
bellard80cabfa2004-03-14 12:20:30 +0000311 case KBD_CCMD_RESET:
bellardd7d02e32004-06-20 12:58:36 +0000312 qemu_system_reset_request();
bellard80cabfa2004-03-14 12:20:30 +0000313 break;
Bernhard Kohl5ccaa4c2010-08-19 14:52:12 +0200314 case KBD_CCMD_NO_OP:
315 /* ignore that */
bellard80cabfa2004-03-14 12:20:30 +0000316 break;
317 default:
318 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
319 break;
320 }
321}
322
bellardb41a2cd2004-03-14 21:46:48 +0000323static uint32_t kbd_read_data(void *opaque, uint32_t addr)
bellard80cabfa2004-03-14 12:20:30 +0000324{
bellardb41a2cd2004-03-14 21:46:48 +0000325 KBDState *s = opaque;
balroge41c0f22008-02-10 13:39:24 +0000326 uint32_t val;
bellard80cabfa2004-03-14 12:20:30 +0000327
bellarddaa57962005-11-26 10:14:03 +0000328 if (s->pending == KBD_PENDING_AUX)
balroge41c0f22008-02-10 13:39:24 +0000329 val = ps2_read_data(s->mouse);
330 else
331 val = ps2_read_data(s->kbd);
bellard80cabfa2004-03-14 12:20:30 +0000332
Blue Swirlc86d2c22010-05-22 07:59:06 +0000333 DPRINTF("kbd: read data=0x%02x\n", val);
balroge41c0f22008-02-10 13:39:24 +0000334 return val;
bellard80cabfa2004-03-14 12:20:30 +0000335}
336
pbrook9596ebb2007-11-18 01:44:38 +0000337static void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
bellard80cabfa2004-03-14 12:20:30 +0000338{
bellardb41a2cd2004-03-14 21:46:48 +0000339 KBDState *s = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000340
Blue Swirlc86d2c22010-05-22 07:59:06 +0000341 DPRINTF("kbd: write data=0x%02x\n", val);
bellard80cabfa2004-03-14 12:20:30 +0000342
343 switch(s->write_cmd) {
344 case 0:
bellarddaa57962005-11-26 10:14:03 +0000345 ps2_write_keyboard(s->kbd, val);
bellard80cabfa2004-03-14 12:20:30 +0000346 break;
347 case KBD_CCMD_WRITE_MODE:
348 s->mode = val;
pbrookf94f5d72006-02-08 04:42:17 +0000349 ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0);
bellarddaa57962005-11-26 10:14:03 +0000350 /* ??? */
bellard80cabfa2004-03-14 12:20:30 +0000351 kbd_update_irq(s);
352 break;
353 case KBD_CCMD_WRITE_OBUF:
354 kbd_queue(s, val, 0);
355 break;
356 case KBD_CCMD_WRITE_AUX_OBUF:
357 kbd_queue(s, val, 1);
358 break;
359 case KBD_CCMD_WRITE_OUTPORT:
Blue Swirl956a3e62010-05-22 07:59:01 +0000360 ioport92_write(s, 0, val);
bellard80cabfa2004-03-14 12:20:30 +0000361 break;
362 case KBD_CCMD_WRITE_MOUSE:
bellarddaa57962005-11-26 10:14:03 +0000363 ps2_write_mouse(s->mouse, val);
bellard80cabfa2004-03-14 12:20:30 +0000364 break;
365 default:
366 break;
367 }
368 s->write_cmd = 0;
369}
370
bellardd7d02e32004-06-20 12:58:36 +0000371static void kbd_reset(void *opaque)
bellard80cabfa2004-03-14 12:20:30 +0000372{
bellardd7d02e32004-06-20 12:58:36 +0000373 KBDState *s = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000374
bellard80cabfa2004-03-14 12:20:30 +0000375 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
376 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
Blue Swirl956a3e62010-05-22 07:59:01 +0000377 s->outport = KBD_OUT_RESET | KBD_OUT_A20;
bellard80cabfa2004-03-14 12:20:30 +0000378}
379
Juan Quintela3c619b52009-09-10 03:04:41 +0200380static const VMStateDescription vmstate_kbd = {
381 .name = "pckbd",
382 .version_id = 3,
383 .minimum_version_id = 3,
384 .minimum_version_id_old = 3,
385 .fields = (VMStateField []) {
386 VMSTATE_UINT8(write_cmd, KBDState),
387 VMSTATE_UINT8(status, KBDState),
388 VMSTATE_UINT8(mode, KBDState),
389 VMSTATE_UINT8(pending, KBDState),
390 VMSTATE_END_OF_LIST()
391 }
392};
bellard675376f2004-07-10 13:39:53 +0000393
thsb92bb992007-04-16 17:20:48 +0000394/* Memory mapped interface */
Anthony Liguoric227f092009-10-01 16:12:16 -0500395static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
thsb92bb992007-04-16 17:20:48 +0000396{
397 KBDState *s = opaque;
398
aurel324efbe582008-12-10 15:02:07 +0000399 if (addr & s->mask)
ths80355292007-04-16 22:47:54 +0000400 return kbd_read_status(s, 0) & 0xff;
aurel324efbe582008-12-10 15:02:07 +0000401 else
402 return kbd_read_data(s, 0) & 0xff;
thsb92bb992007-04-16 17:20:48 +0000403}
404
Anthony Liguoric227f092009-10-01 16:12:16 -0500405static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
thsb92bb992007-04-16 17:20:48 +0000406{
407 KBDState *s = opaque;
408
aurel324efbe582008-12-10 15:02:07 +0000409 if (addr & s->mask)
ths80355292007-04-16 22:47:54 +0000410 kbd_write_command(s, 0, value & 0xff);
aurel324efbe582008-12-10 15:02:07 +0000411 else
412 kbd_write_data(s, 0, value & 0xff);
thsb92bb992007-04-16 17:20:48 +0000413}
414
Blue Swirld60efc62009-08-25 18:29:31 +0000415static CPUReadMemoryFunc * const kbd_mm_read[] = {
thsb92bb992007-04-16 17:20:48 +0000416 &kbd_mm_readb,
417 &kbd_mm_readb,
418 &kbd_mm_readb,
419};
420
Blue Swirld60efc62009-08-25 18:29:31 +0000421static CPUWriteMemoryFunc * const kbd_mm_write[] = {
thsb92bb992007-04-16 17:20:48 +0000422 &kbd_mm_writeb,
423 &kbd_mm_writeb,
424 &kbd_mm_writeb,
425};
426
blueswir171db7102007-06-08 16:45:23 +0000427void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
Anthony Liguoric227f092009-10-01 16:12:16 -0500428 target_phys_addr_t base, ram_addr_t size,
429 target_phys_addr_t mask)
thsb92bb992007-04-16 17:20:48 +0000430{
Blue Swirl5acd0642010-05-12 19:27:23 +0000431 KBDState *s = qemu_mallocz(sizeof(KBDState));
thsb92bb992007-04-16 17:20:48 +0000432 int s_io_memory;
433
434 s->irq_kbd = kbd_irq;
435 s->irq_mouse = mouse_irq;
aurel324efbe582008-12-10 15:02:07 +0000436 s->mask = mask;
thsb92bb992007-04-16 17:20:48 +0000437
Alex Williamson0be71e32010-06-25 11:09:07 -0600438 vmstate_register(NULL, 0, &vmstate_kbd, s);
Avi Kivity1eed09c2009-06-14 11:38:51 +0300439 s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
aurel324efbe582008-12-10 15:02:07 +0000440 cpu_register_physical_memory(base, size, s_io_memory);
thsb92bb992007-04-16 17:20:48 +0000441
442 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
443 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200444 qemu_register_reset(kbd_reset, s);
thsb92bb992007-04-16 17:20:48 +0000445}
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200446
447typedef struct ISAKBDState {
448 ISADevice dev;
449 KBDState kbd;
450} ISAKBDState;
451
Blue Swirl956a3e62010-05-22 07:59:01 +0000452void i8042_isa_mouse_fake_event(void *opaque)
453{
454 ISADevice *dev = opaque;
455 KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
456
457 ps2_mouse_fake_event(s->mouse);
458}
459
460void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out)
461{
462 KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
463
464 s->a20_out = a20_out;
465}
466
Blue Swirld05ac8f2009-12-04 20:44:44 +0000467static const VMStateDescription vmstate_kbd_isa = {
Juan Quintelabe73cfe2009-12-02 12:36:46 +0100468 .name = "pckbd",
469 .version_id = 3,
470 .minimum_version_id = 3,
471 .minimum_version_id_old = 3,
472 .fields = (VMStateField []) {
473 VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState),
474 VMSTATE_END_OF_LIST()
475 }
476};
477
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200478static int i8042_initfn(ISADevice *dev)
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200479{
480 KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
481
Gerd Hoffmann2e15e232009-09-10 11:43:27 +0200482 isa_init_irq(dev, &s->irq_kbd, 1);
483 isa_init_irq(dev, &s->irq_mouse, 12);
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200484
Gerd Hoffmann86c86152009-09-10 11:43:26 +0200485 register_ioport_read(0x60, 1, 1, kbd_read_data, s);
486 register_ioport_write(0x60, 1, 1, kbd_write_data, s);
487 register_ioport_read(0x64, 1, 1, kbd_read_status, s);
488 register_ioport_write(0x64, 1, 1, kbd_write_command, s);
Blue Swirl956a3e62010-05-22 07:59:01 +0000489 register_ioport_read(0x92, 1, 1, ioport92_read, s);
490 register_ioport_write(0x92, 1, 1, ioport92_write, s);
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200491
492 s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
493 s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200494 qemu_register_reset(kbd_reset, s);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200495 return 0;
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200496}
497
498static ISADeviceInfo i8042_info = {
499 .qdev.name = "i8042",
500 .qdev.size = sizeof(ISAKBDState),
Juan Quintelabe73cfe2009-12-02 12:36:46 +0100501 .qdev.vmsd = &vmstate_kbd_isa,
Gerd Hoffmannda85ccf2009-07-31 12:30:15 +0200502 .qdev.no_user = 1,
503 .init = i8042_initfn,
504};
505
506static void i8042_register(void)
507{
508 isa_qdev_register(&i8042_info);
509}
510device_init(i8042_register)