blob: e692b9fdc1075167edb6f658881ea087c46d8dcd [file] [log] [blame]
Jason Baron4d006362012-11-14 15:54:05 -05001/*
Jason Baron6f918e42012-10-29 22:11:31 -04002 * QEMU ICH9 Emulation
3 *
Jason Baron4d006362012-11-14 15:54:05 -05004 * Copyright (c) 2006 Fabrice Bellard
Jason Baron6f918e42012-10-29 22:11:31 -04005 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
Gongleief9f7b52014-08-11 16:10:25 +080010 * This is based on piix.c, but heavily modified.
Jason Baron4d006362012-11-14 15:54:05 -050011 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
Peter Maydellb6a0aa02016-01-26 18:17:03 +000030#include "qemu/osdep.h"
Jason Baron4d006362012-11-14 15:54:05 -050031#include "qemu-common.h"
Paolo Bonzini4771d752016-01-19 21:51:44 +010032#include "cpu.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/hw.h"
Michael S. Tsirkin6f1426a2013-07-24 18:56:10 +030034#include "qapi/visitor.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010035#include "qemu/range.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010036#include "hw/isa/isa.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010037#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010038#include "hw/i386/pc.h"
39#include "hw/isa/apm.h"
40#include "hw/i386/ioapic.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010041#include "hw/pci/pci.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010042#include "hw/pci/pci_bridge.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010043#include "hw/i386/ich9.h"
44#include "hw/acpi/acpi.h"
45#include "hw/acpi/ich9.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010046#include "hw/pci/pci_bus.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010047#include "exec/address-spaces.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010048#include "sysemu/sysemu.h"
Paolo Bonzini7d0c99a2015-12-04 11:10:07 +010049#include "qom/cpu.h"
Laszlo Ersek50de9202017-01-26 02:44:14 +010050#include "hw/nvram/fw_cfg.h"
51#include "qemu/cutils.h"
Jason Baron4d006362012-11-14 15:54:05 -050052
Jason Baron4d006362012-11-14 15:54:05 -050053/*****************************************************************************/
54/* ICH9 LPC PCI to ISA bridge */
55
56static void ich9_lpc_reset(DeviceState *qdev);
57
58/* chipset configuration register
59 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
60 * are used.
61 * Although it's not pci configuration space, it's little endian as Intel.
62 */
63
64static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
65{
66 int intx;
67 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
68 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
69 }
70}
71
72static void ich9_cc_update(ICH9LPCState *lpc)
73{
74 int slot;
75 int pci_intx;
76
77 const int reg_offsets[] = {
78 ICH9_CC_D25IR,
79 ICH9_CC_D26IR,
80 ICH9_CC_D27IR,
81 ICH9_CC_D28IR,
82 ICH9_CC_D29IR,
83 ICH9_CC_D30IR,
84 ICH9_CC_D31IR,
85 };
86 const int *offset;
87
88 /* D{25 - 31}IR, but D30IR is read only to 0. */
89 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
90 if (slot == 30) {
91 continue;
92 }
93 ich9_cc_update_ir(lpc->irr[slot],
94 pci_get_word(lpc->chip_config + *offset));
95 }
96
97 /*
98 * D30: DMI2PCI bridge
Cao jin0668a062016-05-17 09:41:18 +080099 * It is arbitrarily decided how INTx lines of PCI devices behind
100 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
Jason Baron4d006362012-11-14 15:54:05 -0500101 * INT[A-D] are connected to PIRQ[E-H]
102 */
103 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
104 lpc->irr[30][pci_intx] = pci_intx + 4;
105 }
106}
107
108static void ich9_cc_init(ICH9LPCState *lpc)
109{
110 int slot;
111 int intx;
112
113 /* the default irq routing is arbitrary as long as it matches with
114 * acpi irq routing table.
115 * The one that is incompatible with piix_pci(= bochs) one is
116 * intentionally chosen to let the users know that the different
117 * board is used.
118 *
119 * int[A-D] -> pirq[E-F]
120 * avoid pirq A-D because they are used for pci express port
121 */
122 for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
123 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
124 lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
125 }
126 }
127 ich9_cc_update(lpc);
128}
129
130static void ich9_cc_reset(ICH9LPCState *lpc)
131{
132 uint8_t *c = lpc->chip_config;
133
134 memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
135
136 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
137 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
138 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
139 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
140 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
141 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
142 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
Paulo Alcantara92055792015-06-28 14:58:56 -0300143 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
Jason Baron4d006362012-11-14 15:54:05 -0500144
145 ich9_cc_update(lpc);
146}
147
148static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
149{
150 *addr &= ICH9_CC_ADDR_MASK;
151 if (*addr + *len >= ICH9_CC_SIZE) {
152 *len = ICH9_CC_SIZE - *addr;
153 }
154}
155
156/* val: little endian */
157static void ich9_cc_write(void *opaque, hwaddr addr,
158 uint64_t val, unsigned len)
159{
160 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
161
162 ich9_cc_addr_len(&addr, &len);
163 memcpy(lpc->chip_config + addr, &val, len);
David Gibsonfd56e062017-11-29 19:46:27 +1100164 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
Jason Baron4d006362012-11-14 15:54:05 -0500165 ich9_cc_update(lpc);
166}
167
168/* return value: little endian */
169static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
170 unsigned len)
171{
172 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
173
174 uint32_t val = 0;
175 ich9_cc_addr_len(&addr, &len);
176 memcpy(&val, lpc->chip_config + addr, len);
177 return val;
178}
179
180/* IRQ routing */
181/* */
182static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
183{
184 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
185 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
186}
187
188static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
189 int *pic_irq, int *pic_dis)
190{
191 switch (pirq_num) {
192 case 0 ... 3: /* A-D */
193 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
194 pic_irq, pic_dis);
195 return;
196 case 4 ... 7: /* E-H */
197 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
198 pic_irq, pic_dis);
199 return;
200 default:
201 break;
202 }
203 abort();
204}
205
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200206/* gsi: i8259+ioapic irq 0-15, otherwise assert */
207static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
Jason Baron4d006362012-11-14 15:54:05 -0500208{
209 int i, pic_level;
210
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200211 assert(gsi < ICH9_LPC_PIC_NUM_PINS);
212
Jason Baron4d006362012-11-14 15:54:05 -0500213 /* The pic level is the logical OR of all the PCI irqs mapped to it */
214 pic_level = 0;
215 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
216 int tmp_irq;
217 int tmp_dis;
218 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200219 if (!tmp_dis && tmp_irq == gsi) {
David Gibsonfd56e062017-11-29 19:46:27 +1100220 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
Jason Baron4d006362012-11-14 15:54:05 -0500221 }
222 }
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200223 if (gsi == lpc->sci_gsi) {
Jason Baron4d006362012-11-14 15:54:05 -0500224 pic_level |= lpc->sci_level;
225 }
226
Paolo Bonzini35a6b232016-06-17 17:12:09 +0200227 qemu_set_irq(lpc->gsi[gsi], pic_level);
Jason Baron4d006362012-11-14 15:54:05 -0500228}
229
230/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
231static int ich9_pirq_to_gsi(int pirq)
232{
233 return pirq + ICH9_LPC_PIC_NUM_PINS;
234}
235
236static int ich9_gsi_to_pirq(int gsi)
237{
238 return gsi - ICH9_LPC_PIC_NUM_PINS;
239}
240
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200241/* gsi: ioapic irq 16-23, otherwise assert */
Jason Baron4d006362012-11-14 15:54:05 -0500242static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
243{
Jan Kiszka243b9512012-11-14 15:54:08 -0500244 int level = 0;
Jason Baron4d006362012-11-14 15:54:05 -0500245
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200246 assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
247
David Gibsonfd56e062017-11-29 19:46:27 +1100248 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200249 if (gsi == lpc->sci_gsi) {
Jason Baron4d006362012-11-14 15:54:05 -0500250 level |= lpc->sci_level;
251 }
252
Paolo Bonzini35a6b232016-06-17 17:12:09 +0200253 qemu_set_irq(lpc->gsi[gsi], level);
Jason Baron4d006362012-11-14 15:54:05 -0500254}
255
256void ich9_lpc_set_irq(void *opaque, int pirq, int level)
257{
258 ICH9LPCState *lpc = opaque;
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200259 int pic_irq, pic_dis;
Jason Baron4d006362012-11-14 15:54:05 -0500260
261 assert(0 <= pirq);
262 assert(pirq < ICH9_LPC_NB_PIRQS);
263
264 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200265 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
266 ich9_lpc_update_pic(lpc, pic_irq);
Jason Baron4d006362012-11-14 15:54:05 -0500267}
268
269/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
270 * a given device irq pin.
271 */
272int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
273{
274 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
275 PCIBus *pci_bus = PCI_BUS(bus);
276 PCIDevice *lpc_pdev =
277 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
278 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
279
280 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
281}
282
Jason Baron91c3f2f2013-01-22 19:11:37 -0700283PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
284{
285 ICH9LPCState *lpc = opaque;
286 PCIINTxRoute route;
287 int pic_irq;
288 int pic_dis;
289
290 assert(0 <= pirq_pin);
291 assert(pirq_pin < ICH9_LPC_NB_PIRQS);
292
293 route.mode = PCI_INTX_ENABLED;
294 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
295 if (!pic_dis) {
296 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
297 route.irq = pic_irq;
298 } else {
299 route.mode = PCI_INTX_DISABLED;
300 route.irq = -1;
301 }
302 } else {
303 route.irq = ich9_pirq_to_gsi(pirq_pin);
304 }
305
306 return route;
307}
308
Paulo Alcantara92055792015-06-28 14:58:56 -0300309void ich9_generate_smi(void)
310{
311 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
312}
313
Jason Baron4d006362012-11-14 15:54:05 -0500314static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
315{
316 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
317 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
318 case ICH9_LPC_ACPI_CTRL_9:
319 return 9;
320 case ICH9_LPC_ACPI_CTRL_10:
321 return 10;
322 case ICH9_LPC_ACPI_CTRL_11:
323 return 11;
324 case ICH9_LPC_ACPI_CTRL_20:
325 return 20;
326 case ICH9_LPC_ACPI_CTRL_21:
327 return 21;
328 default:
329 /* reserved */
330 break;
331 }
332 return -1;
333}
334
335static void ich9_set_sci(void *opaque, int irq_num, int level)
336{
337 ICH9LPCState *lpc = opaque;
338 int irq;
339
340 assert(irq_num == 0);
341 level = !!level;
342 if (level == lpc->sci_level) {
343 return;
344 }
345 lpc->sci_level = level;
346
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200347 irq = lpc->sci_gsi;
Jason Baron4d006362012-11-14 15:54:05 -0500348 if (irq < 0) {
349 return;
350 }
351
Paolo Bonzinia94dd6a2016-06-17 17:07:31 +0200352 if (irq >= ICH9_LPC_PIC_NUM_PINS) {
353 ich9_lpc_update_apic(lpc, irq);
354 } else {
Jason Baron4d006362012-11-14 15:54:05 -0500355 ich9_lpc_update_pic(lpc, irq);
356 }
357}
358
Laszlo Ersek50de9202017-01-26 02:44:14 +0100359static void smi_features_ok_callback(void *opaque)
360{
361 ICH9LPCState *lpc = opaque;
362 uint64_t guest_features;
363
364 if (lpc->smi_features_ok) {
365 /* negotiation already complete, features locked */
366 return;
367 }
368
369 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
370 le64_to_cpus(&guest_features);
371 if (guest_features & ~lpc->smi_host_features) {
372 /* guest requests invalid features, leave @features_ok at zero */
373 return;
374 }
375
376 /* valid feature subset requested, lock it down, report success */
377 lpc->smi_negotiated_features = guest_features;
378 lpc->smi_features_ok = 1;
379}
380
Eduardo Habkost18d6aba2016-01-23 14:02:11 -0200381void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
Jason Baron4d006362012-11-14 15:54:05 -0500382{
383 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
Paolo Bonzinifba72472015-06-18 18:30:51 +0200384 qemu_irq sci_irq;
Laszlo Ersek50de9202017-01-26 02:44:14 +0100385 FWCfgState *fw_cfg = fw_cfg_find();
Jason Baron4d006362012-11-14 15:54:05 -0500386
Paolo Bonzinifba72472015-06-18 18:30:51 +0200387 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
Eduardo Habkost18d6aba2016-01-23 14:02:11 -0200388 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
Laszlo Ersek50de9202017-01-26 02:44:14 +0100389
390 if (lpc->smi_host_features && fw_cfg) {
391 uint64_t host_features_le;
392
393 host_features_le = cpu_to_le64(lpc->smi_host_features);
394 memcpy(lpc->smi_host_features_le, &host_features_le,
395 sizeof host_features_le);
396 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
397 lpc->smi_host_features_le,
398 sizeof lpc->smi_host_features_le);
399
400 /* The other two guest-visible fields are cleared on device reset, we
401 * just link them into fw_cfg here.
402 */
403 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
Marc-André Lureau5f9252f2017-09-11 18:59:23 +0200404 NULL, NULL, NULL,
Laszlo Ersek50de9202017-01-26 02:44:14 +0100405 lpc->smi_guest_features_le,
406 sizeof lpc->smi_guest_features_le,
407 false);
408 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
Marc-André Lureau5f9252f2017-09-11 18:59:23 +0200409 smi_features_ok_callback, NULL, lpc,
Laszlo Ersek50de9202017-01-26 02:44:14 +0100410 &lpc->smi_features_ok,
411 sizeof lpc->smi_features_ok,
412 true);
413 }
414
Jason Baron4d006362012-11-14 15:54:05 -0500415 ich9_lpc_reset(&lpc->d.qdev);
416}
417
418/* APM */
419
420static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
421{
422 ICH9LPCState *lpc = arg;
423
424 /* ACPI specs 3.0, 4.7.2.5 */
425 acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
426 val == ICH9_APM_ACPI_ENABLE,
427 val == ICH9_APM_ACPI_DISABLE);
Paolo Bonziniafd68952015-06-18 18:28:41 +0200428 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
429 return;
430 }
Jason Baron4d006362012-11-14 15:54:05 -0500431
432 /* SMI_EN = PMBASE + 30. SMI control and enable register */
433 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
Laszlo Ersek5ce45c72017-01-26 02:44:15 +0100434 if (lpc->smi_negotiated_features &
435 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
436 CPUState *cs;
437 CPU_FOREACH(cs) {
438 cpu_interrupt(cs, CPU_INTERRUPT_SMI);
439 }
440 } else {
441 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
442 }
Jason Baron4d006362012-11-14 15:54:05 -0500443 }
444}
445
446/* config:PMBASE */
447static void
Paolo Bonzini6d356c82016-06-23 07:49:16 +0200448ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
Jason Baron4d006362012-11-14 15:54:05 -0500449{
450 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
Paolo Bonzini6d356c82016-06-23 07:49:16 +0200451 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200452 uint8_t new_gsi;
Paolo Bonzini6d356c82016-06-23 07:49:16 +0200453
454 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
455 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
456 } else {
457 pm_io_base = 0;
458 }
Jason Baron4d006362012-11-14 15:54:05 -0500459
460 ich9_pm_iospace_update(&lpc->pm, pm_io_base);
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200461
462 new_gsi = ich9_lpc_sci_irq(lpc);
463 if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
464 qemu_set_irq(lpc->pm.irq, 0);
465 lpc->sci_gsi = new_gsi;
466 qemu_set_irq(lpc->pm.irq, 1);
467 }
468 lpc->sci_gsi = new_gsi;
Jason Baron4d006362012-11-14 15:54:05 -0500469}
470
Cao jin7335a952016-03-07 20:38:58 +0800471/* config:RCBA */
472static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
Jason Baron4d006362012-11-14 15:54:05 -0500473{
Cao jin7335a952016-03-07 20:38:58 +0800474 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
Jason Baron4d006362012-11-14 15:54:05 -0500475
Cao jin7335a952016-03-07 20:38:58 +0800476 if (rcba_old & ICH9_LPC_RCBA_EN) {
477 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
Jason Baron4d006362012-11-14 15:54:05 -0500478 }
Cao jin7335a952016-03-07 20:38:58 +0800479 if (rcba & ICH9_LPC_RCBA_EN) {
480 memory_region_add_subregion_overlap(get_system_memory(),
481 rcba & ICH9_LPC_RCBA_BA_MASK,
482 &lpc->rcrb_mem, 1);
Jason Baron4d006362012-11-14 15:54:05 -0500483 }
484}
485
Gerd Hoffmann11e66a12015-05-06 10:58:30 +0200486/* config:GEN_PMCON* */
487static void
488ich9_lpc_pmcon_update(ICH9LPCState *lpc)
489{
490 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
491 uint16_t wmask;
492
493 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
494 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
495 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
496 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
497 lpc->pm.smi_en_wmask &= ~1;
498 }
499}
500
Jason Baron4d006362012-11-14 15:54:05 -0500501static int ich9_lpc_post_load(void *opaque, int version_id)
502{
503 ICH9LPCState *lpc = opaque;
504
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200505 ich9_lpc_pmbase_sci_update(lpc);
Cao jin7335a952016-03-07 20:38:58 +0800506 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
Gerd Hoffmann11e66a12015-05-06 10:58:30 +0200507 ich9_lpc_pmcon_update(lpc);
Jason Baron4d006362012-11-14 15:54:05 -0500508 return 0;
509}
510
511static void ich9_lpc_config_write(PCIDevice *d,
512 uint32_t addr, uint32_t val, int len)
513{
514 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
Cao jin7335a952016-03-07 20:38:58 +0800515 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
Jason Baron4d006362012-11-14 15:54:05 -0500516
517 pci_default_write_config(d, addr, val, len);
Paolo Bonzini6d356c82016-06-23 07:49:16 +0200518 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
519 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200520 ich9_lpc_pmbase_sci_update(lpc);
Jason Baron4d006362012-11-14 15:54:05 -0500521 }
522 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
Cao jin7335a952016-03-07 20:38:58 +0800523 ich9_lpc_rcba_update(lpc, rcba_old);
Jason Baron4d006362012-11-14 15:54:05 -0500524 }
Jason Baron91c3f2f2013-01-22 19:11:37 -0700525 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
David Gibsonfd56e062017-11-29 19:46:27 +1100526 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
Jason Baron91c3f2f2013-01-22 19:11:37 -0700527 }
528 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
David Gibsonfd56e062017-11-29 19:46:27 +1100529 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
Jason Baron91c3f2f2013-01-22 19:11:37 -0700530 }
Gerd Hoffmann11e66a12015-05-06 10:58:30 +0200531 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
532 ich9_lpc_pmcon_update(lpc);
533 }
Jason Baron4d006362012-11-14 15:54:05 -0500534}
535
536static void ich9_lpc_reset(DeviceState *qdev)
537{
538 PCIDevice *d = PCI_DEVICE(qdev);
539 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
Cao jin7335a952016-03-07 20:38:58 +0800540 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
Jason Baron4d006362012-11-14 15:54:05 -0500541 int i;
542
543 for (i = 0; i < 4; i++) {
544 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
545 ICH9_LPC_PIRQ_ROUT_DEFAULT);
546 }
547 for (i = 0; i < 4; i++) {
548 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
549 ICH9_LPC_PIRQ_ROUT_DEFAULT);
550 }
551 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
552
553 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
554 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
555
556 ich9_cc_reset(lpc);
557
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200558 ich9_lpc_pmbase_sci_update(lpc);
Cao jin7335a952016-03-07 20:38:58 +0800559 ich9_lpc_rcba_update(lpc, rcba_old);
Jason Baron4d006362012-11-14 15:54:05 -0500560
561 lpc->sci_level = 0;
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100562 lpc->rst_cnt = 0;
Laszlo Ersek50de9202017-01-26 02:44:14 +0100563
564 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
565 lpc->smi_features_ok = 0;
566 lpc->smi_negotiated_features = 0;
Jason Baron4d006362012-11-14 15:54:05 -0500567}
568
Cao jin7335a952016-03-07 20:38:58 +0800569/* root complex register block is mapped into memory space */
570static const MemoryRegionOps rcrb_mmio_ops = {
Jason Baron4d006362012-11-14 15:54:05 -0500571 .read = ich9_cc_read,
572 .write = ich9_cc_write,
573 .endianness = DEVICE_LITTLE_ENDIAN,
574};
575
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100576static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
577{
578 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
Jan Kiszkab6f32962013-06-22 08:07:01 +0200579 MemoryRegion *io_as = pci_address_space_io(&s->d);
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100580 uint8_t *pci_conf;
581
582 pci_conf = s->d.config;
Paolo Bonzini3ce10902013-07-02 13:40:48 +0200583 if (memory_region_present(io_as, 0x3f8)) {
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100584 /* com1 */
585 pci_conf[0x82] |= 0x01;
586 }
Paolo Bonzini3ce10902013-07-02 13:40:48 +0200587 if (memory_region_present(io_as, 0x2f8)) {
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100588 /* com2 */
589 pci_conf[0x82] |= 0x02;
590 }
Paolo Bonzini3ce10902013-07-02 13:40:48 +0200591 if (memory_region_present(io_as, 0x378)) {
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100592 /* lpt */
593 pci_conf[0x82] |= 0x04;
594 }
Marcel Apfelbaum557772f2015-06-01 17:09:12 +0300595 if (memory_region_present(io_as, 0x3f2)) {
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100596 /* floppy */
597 pci_conf[0x82] |= 0x08;
598 }
599}
600
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100601/* reset control */
602static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
603 unsigned len)
604{
605 ICH9LPCState *lpc = opaque;
606
607 if (val & 4) {
Eric Blakecf83f142017-05-15 16:41:13 -0500608 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100609 return;
610 }
611 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
612}
613
614static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
615{
616 ICH9LPCState *lpc = opaque;
617
618 return lpc->rst_cnt;
619}
620
621static const MemoryRegionOps ich9_rst_cnt_ops = {
622 .read = ich9_rst_cnt_read,
623 .write = ich9_rst_cnt_write,
624 .endianness = DEVICE_LITTLE_ENDIAN
625};
626
Michael S. Tsirkin6f1426a2013-07-24 18:56:10 +0300627Object *ich9_lpc_find(void)
628{
629 bool ambig;
630 Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
631
632 if (ambig) {
633 return NULL;
634 }
635 return o;
636}
637
Eric Blaked7bce992016-01-29 06:48:55 -0700638static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name,
639 void *opaque, Error **errp)
Michael S. Tsirkin6f1426a2013-07-24 18:56:10 +0300640{
641 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200642 uint32_t value = lpc->sci_gsi;
Michael S. Tsirkin6f1426a2013-07-24 18:56:10 +0300643
Eric Blake51e72bc2016-01-29 06:48:54 -0700644 visit_type_uint32(v, name, &value, errp);
Michael S. Tsirkin6f1426a2013-07-24 18:56:10 +0300645}
646
647static void ich9_lpc_add_properties(ICH9LPCState *lpc)
648{
649 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
650 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
651
652 object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
653 ich9_lpc_get_sci_int,
654 NULL, NULL, NULL, NULL);
655 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
656 &acpi_enable_cmd, NULL);
657 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
658 &acpi_disable_cmd, NULL);
659
660 ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
661}
662
Igor Mammedovd6b38b62014-06-02 15:25:21 +0200663static void ich9_lpc_initfn(Object *obj)
664{
665 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
666
667 ich9_lpc_add_properties(lpc);
668}
669
Markus Armbruster3a80cea2015-12-17 17:35:17 +0100670static void ich9_lpc_realize(PCIDevice *d, Error **errp)
Jason Baron4d006362012-11-14 15:54:05 -0500671{
672 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
Efimov Vasilyf999c0d2016-06-22 15:24:54 +0300673 DeviceState *dev = DEVICE(d);
Jason Baron4d006362012-11-14 15:54:05 -0500674 ISABus *isa_bus;
675
Markus Armbrusterd10e5432015-12-17 17:35:18 +0100676 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
677 errp);
678 if (!isa_bus) {
679 return;
680 }
Jason Baron4d006362012-11-14 15:54:05 -0500681
682 pci_set_long(d->wmask + ICH9_LPC_PMBASE,
683 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
Paolo Bonzini6d356c82016-06-23 07:49:16 +0200684 pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
Paolo Bonzini8f242cb2016-06-23 07:54:22 +0200685 ICH9_LPC_ACPI_CTRL_ACPI_EN |
686 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
Jason Baron4d006362012-11-14 15:54:05 -0500687
Cao jin7335a952016-03-07 20:38:58 +0800688 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
689 "lpc-rcrb-mmio", ICH9_CC_SIZE);
Jason Baron4d006362012-11-14 15:54:05 -0500690
691 lpc->isa_bus = isa_bus;
692
693 ich9_cc_init(lpc);
Julien Grall42d8a3c2012-09-19 12:50:03 +0100694 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
Gerd Hoffmann3f5bc9e2012-11-23 15:02:18 +0100695
696 lpc->machine_ready.notify = ich9_lpc_machine_ready;
697 qemu_add_machine_init_done_notifier(&lpc->machine_ready);
698
Paolo Bonzini1437c942013-06-06 21:25:08 -0400699 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100700 "lpc-reset-control", 1);
701 memory_region_add_subregion_overlap(pci_address_space_io(d),
702 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
703 1);
Efimov Vasilyf999c0d2016-06-22 15:24:54 +0300704
705 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
Efimov Vasilyea5d4252016-06-22 15:24:55 +0300706
707 isa_bus_irqs(isa_bus, lpc->gsi);
Jason Baron4d006362012-11-14 15:54:05 -0500708}
709
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100710static bool ich9_rst_cnt_needed(void *opaque)
711{
712 ICH9LPCState *lpc = opaque;
713
714 return (lpc->rst_cnt != 0);
715}
716
717static const VMStateDescription vmstate_ich9_rst_cnt = {
718 .name = "ICH9LPC/rst_cnt",
719 .version_id = 1,
720 .minimum_version_id = 1,
Juan Quintela5cd8cad2014-09-23 14:09:54 +0200721 .needed = ich9_rst_cnt_needed,
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100722 .fields = (VMStateField[]) {
723 VMSTATE_UINT8(rst_cnt, ICH9LPCState),
724 VMSTATE_END_OF_LIST()
725 }
726};
727
Laszlo Ersek50de9202017-01-26 02:44:14 +0100728static bool ich9_smi_feat_needed(void *opaque)
729{
730 ICH9LPCState *lpc = opaque;
731
732 return !buffer_is_zero(lpc->smi_guest_features_le,
733 sizeof lpc->smi_guest_features_le) ||
734 lpc->smi_features_ok;
735}
736
737static const VMStateDescription vmstate_ich9_smi_feat = {
738 .name = "ICH9LPC/smi_feat",
739 .version_id = 1,
740 .minimum_version_id = 1,
741 .needed = ich9_smi_feat_needed,
742 .fields = (VMStateField[]) {
743 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
744 sizeof(uint64_t)),
745 VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
746 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
747 VMSTATE_END_OF_LIST()
748 }
749};
750
Jason Baron4d006362012-11-14 15:54:05 -0500751static const VMStateDescription vmstate_ich9_lpc = {
752 .name = "ICH9LPC",
753 .version_id = 1,
754 .minimum_version_id = 1,
Jason Baron4d006362012-11-14 15:54:05 -0500755 .post_load = ich9_lpc_post_load,
756 .fields = (VMStateField[]) {
757 VMSTATE_PCI_DEVICE(d, ICH9LPCState),
758 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
759 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
760 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
761 VMSTATE_UINT32(sci_level, ICH9LPCState),
762 VMSTATE_END_OF_LIST()
Laszlo Ersek0e98b432013-02-20 02:51:24 +0100763 },
Juan Quintela5cd8cad2014-09-23 14:09:54 +0200764 .subsections = (const VMStateDescription*[]) {
765 &vmstate_ich9_rst_cnt,
Laszlo Ersek50de9202017-01-26 02:44:14 +0100766 &vmstate_ich9_smi_feat,
Juan Quintela5cd8cad2014-09-23 14:09:54 +0200767 NULL
Jason Baron4d006362012-11-14 15:54:05 -0500768 }
769};
770
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300771static Property ich9_lpc_properties[] = {
772 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
Laszlo Ersekb8bab8e2017-01-26 02:44:16 +0100773 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
774 ICH9_LPC_SMI_F_BROADCAST_BIT, true),
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300775 DEFINE_PROP_END_OF_LIST(),
776};
777
Igor Mammedoveaf23bf2016-05-31 11:57:57 +0200778static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
779{
780 ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
781
782 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
783}
784
Jason Baron4d006362012-11-14 15:54:05 -0500785static void ich9_lpc_class_init(ObjectClass *klass, void *data)
786{
787 DeviceClass *dc = DEVICE_CLASS(klass);
788 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Igor Mammedov1f862182014-06-02 15:25:22 +0200789 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
Igor Mammedov43f50412014-06-16 19:12:27 +0200790 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
Jason Baron4d006362012-11-14 15:54:05 -0500791
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300792 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
Jason Baron4d006362012-11-14 15:54:05 -0500793 dc->reset = ich9_lpc_reset;
Markus Armbruster3a80cea2015-12-17 17:35:17 +0100794 k->realize = ich9_lpc_realize;
Jason Baron4d006362012-11-14 15:54:05 -0500795 dc->vmsd = &vmstate_ich9_lpc;
Paulo Alcantara5add35b2015-06-28 14:58:58 -0300796 dc->props = ich9_lpc_properties;
Jason Baron4d006362012-11-14 15:54:05 -0500797 k->config_write = ich9_lpc_config_write;
798 dc->desc = "ICH9 LPC bridge";
799 k->vendor_id = PCI_VENDOR_ID_INTEL;
800 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
801 k->revision = ICH9_A2_LPC_REVISION;
802 k->class_id = PCI_CLASS_BRIDGE_ISA;
Markus Armbrusterbfa6dfd2013-11-28 17:26:59 +0100803 /*
804 * Reason: part of ICH9 southbridge, needs to be wired up by
805 * pc_q35_init()
806 */
Eduardo Habkoste90f2a82017-05-03 17:35:44 -0300807 dc->user_creatable = false;
Igor Mammedov0058c082016-05-31 12:01:17 +0200808 hc->plug = ich9_pm_device_plug_cb;
809 hc->unplug_request = ich9_pm_device_unplug_request_cb;
810 hc->unplug = ich9_pm_device_unplug_cb;
Igor Mammedov43f50412014-06-16 19:12:27 +0200811 adevc->ospm_status = ich9_pm_ospm_status;
Igor Mammedoveaf23bf2016-05-31 11:57:57 +0200812 adevc->send_event = ich9_send_gpe;
Igor Mammedovac35f132016-04-20 11:28:57 +0200813 adevc->madt_cpu = pc_madt_cpu_entry;
Jason Baron4d006362012-11-14 15:54:05 -0500814}
815
816static const TypeInfo ich9_lpc_info = {
817 .name = TYPE_ICH9_LPC_DEVICE,
818 .parent = TYPE_PCI_DEVICE,
819 .instance_size = sizeof(struct ICH9LPCState),
Igor Mammedovd6b38b62014-06-02 15:25:21 +0200820 .instance_init = ich9_lpc_initfn,
Jason Baron4d006362012-11-14 15:54:05 -0500821 .class_init = ich9_lpc_class_init,
Igor Mammedov1f862182014-06-02 15:25:22 +0200822 .interfaces = (InterfaceInfo[]) {
823 { TYPE_HOTPLUG_HANDLER },
Igor Mammedov43f50412014-06-16 19:12:27 +0200824 { TYPE_ACPI_DEVICE_IF },
Eduardo Habkostfd3b02c2017-09-27 16:56:34 -0300825 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
Igor Mammedov1f862182014-06-02 15:25:22 +0200826 { }
827 }
Jason Baron4d006362012-11-14 15:54:05 -0500828};
829
830static void ich9_lpc_register(void)
831{
832 type_register_static(&ich9_lpc_info);
833}
834
835type_init(ich9_lpc_register);