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aurel32d76d1652008-12-16 10:43:58 +00001/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
Scott Wood90dc8812011-04-29 17:10:23 -05005 * Copyright (C) 2011 Freescale Semiconductor, Inc.
aurel32d76d1652008-12-16 10:43:58 +00006 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
Peter Maydell0d755902016-01-26 18:16:58 +000017#include "qemu/osdep.h"
Alexander Grafeadaada2011-07-21 02:29:15 +020018#include <dirent.h>
aurel32d76d1652008-12-16 10:43:58 +000019#include <sys/ioctl.h>
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +000020#include <sys/vfs.h>
aurel32d76d1652008-12-16 10:43:58 +000021
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
David Gibson30f4b052017-05-12 15:46:11 +100025#include "qapi/error.h"
Thomas Huth072ed5f2016-02-18 22:01:38 +010026#include "qemu/error-report.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010027#include "cpu.h"
Thomas Huth715d4b92017-01-31 14:11:58 +010028#include "cpu-models.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010029#include "qemu/timer.h"
Vincent Palatinb3946622017-01-10 11:59:55 +010030#include "sysemu/hw_accel.h"
aurel32d76d1652008-12-16 10:43:58 +000031#include "kvm_ppc.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010032#include "sysemu/cpus.h"
33#include "sysemu/device_tree.h"
David Gibsond5aea6f2013-03-12 00:31:18 +000034#include "mmu-hash64.h"
aurel32d76d1652008-12-16 10:43:58 +000035
Alexander Graff61b4be2011-08-09 17:57:37 +020036#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010037#include "hw/ppc/spapr.h"
Bharata B Rao7ebaf792016-09-12 13:27:20 +053038#include "hw/ppc/spapr_cpu_core.h"
Markus Armbruster650d1032019-08-12 07:23:48 +020039#include "hw/hw.h"
Alexey Kardashevskiy98a8b522014-05-01 20:37:09 +100040#include "hw/ppc/ppc.h"
Markus Armbrusterca77ee22019-08-12 07:23:39 +020041#include "migration/qemu-file-types.h"
Bharat Bhushan31f2cb82013-02-24 18:16:21 +000042#include "sysemu/watchdog.h"
Alexey Kardashevskiyb36f1002014-02-04 15:12:34 +110043#include "trace.h"
Bharat Bhushan88365d12014-07-14 14:45:37 +053044#include "exec/gdbstub.h"
Paolo Bonzini4c663752015-04-08 13:30:58 +020045#include "exec/memattrs.h"
Alexey Kardashevskiy9c607662017-03-02 13:36:11 +110046#include "exec/ram_addr.h"
Michael Roth2d103aa2015-07-02 15:46:14 -050047#include "sysemu/hostmem.h"
Veronia Bahaaf348b6d2016-03-20 19:16:19 +020048#include "qemu/cutils.h"
Markus Armbrusterdb725812019-08-12 07:23:50 +020049#include "qemu/main-loop.h"
Alexey Kardashevskiy9c607662017-03-02 13:36:11 +110050#include "qemu/mmap-alloc.h"
Sam Bobrofff3d9f302017-03-29 16:01:28 +110051#include "elf.h"
Sam Bobroffc64abd12017-03-20 10:46:43 +110052#include "sysemu/kvm_int.h"
Alexander Graff61b4be2011-08-09 17:57:37 +020053
Alexander Grafeadaada2011-07-21 02:29:15 +020054#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
55
Fabiano Rosas6e0552a2020-01-10 12:13:42 -030056#define DEBUG_RETURN_GUEST 0
57#define DEBUG_RETURN_GDB 1
58
Jan Kiszka94a8d392011-01-21 21:48:17 +010059const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
60 KVM_CAP_LAST_INFO
61};
62
David Gibsonc995e942019-03-21 21:47:25 +110063static int cap_interrupt_unset;
Scott Wood90dc8812011-04-29 17:10:23 -050064static int cap_segstate;
Scott Wood90dc8812011-04-29 17:10:23 -050065static int cap_booke_sregs;
David Gibsone97c3632011-09-29 21:39:10 +000066static int cap_ppc_smt;
Sam Bobrofffa98fbf2017-08-18 15:50:22 +100067static int cap_ppc_smt_possible;
David Gibson0f5cb292011-09-29 21:39:12 +000068static int cap_spapr_tce;
Alexey Kardashevskiyd6ee2a72017-03-10 12:41:13 +110069static int cap_spapr_tce_64;
Alexey Kardashevskiyda953242014-05-27 15:36:30 +100070static int cap_spapr_multitce;
Alexey Kardashevskiy9bb62a02014-06-10 15:39:21 +100071static int cap_spapr_vfio;
David Gibsonf1af19d2012-09-12 16:57:09 +000072static int cap_hior;
David Gibsond67d40e2013-02-20 16:41:50 +000073static int cap_one_reg;
Stuart Yoder3b961122013-03-30 06:40:49 +000074static int cap_epr;
Bharat Bhushan31f2cb82013-02-24 18:16:21 +000075static int cap_ppc_watchdog;
David Gibson9b00ea42013-04-07 19:08:22 +000076static int cap_papr;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -050077static int cap_htab_fd;
Alexander Graf87a91de2014-06-04 12:14:08 +020078static int cap_fixup_hcalls;
Thomas Huthbac3bf22016-09-28 13:16:30 +020079static int cap_htm; /* Hardware transactional memory support */
Sam Bobroffcf1c4cc2017-03-20 10:46:44 +110080static int cap_mmu_radix;
81static int cap_mmu_hash_v3;
Cédric Le Goater38afd772019-05-13 10:42:33 +020082static int cap_xive;
David Gibsonb55d2952017-07-12 17:56:55 +100083static int cap_resize_hpt;
Daniel Henrique Barbozac363a372017-08-09 17:43:46 -030084static int cap_ppc_pvr_compat;
Suraj Jitindar Singh8acc2ae2018-01-19 15:59:59 +110085static int cap_ppc_safe_cache;
86static int cap_ppc_safe_bounds_check;
87static int cap_ppc_safe_indirect_branch;
Suraj Jitindar Singh8ff43ee2019-03-01 14:19:12 +110088static int cap_ppc_count_cache_flush_assist;
Suraj Jitindar Singhb9a477b2018-10-08 14:25:39 +110089static int cap_ppc_nested_kvm_hv;
Suraj Jitindar Singh7d050522019-03-01 13:43:16 +110090static int cap_large_decr;
Nicholas Pigginec010c02020-03-26 00:29:03 +100091static int cap_fwnmi;
Bharata B Rao82123b72021-07-06 16:54:40 +053092static int cap_rpt_invalidate;
Alexander Graffc87e182010-08-30 13:49:15 +020093
Bharat Bhushan3c902d42014-07-14 14:45:35 +053094static uint32_t debug_inst_opcode;
95
David Gibsonc995e942019-03-21 21:47:25 +110096/*
David Gibsonc995e942019-03-21 21:47:25 +110097 * Check whether we are running with KVM-PR (instead of KVM-HV). This
Thomas Huth96c9cff2016-09-29 12:48:06 +020098 * should only be used for fallback tests - generally we should use
99 * explicit capabilities for the features we want, rather than
David Gibsonc995e942019-03-21 21:47:25 +1100100 * assuming what is/isn't available depending on the KVM variant.
101 */
Thomas Huth96c9cff2016-09-29 12:48:06 +0200102static bool kvmppc_is_pr(KVMState *ks)
103{
104 /* Assume KVM-PR if the GET_PVINFO capability is available */
Greg Kurz70a0c192017-09-14 12:48:04 +0200105 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
Thomas Huth96c9cff2016-09-29 12:48:06 +0200106}
107
David Gibson165dc3e2019-10-30 17:20:35 +0100108static int kvm_ppc_register_host_cpu_type(void);
Suraj Jitindar Singh8acc2ae2018-01-19 15:59:59 +1100109static void kvmppc_get_cpu_characteristics(KVMState *s);
Suraj Jitindar Singh7d050522019-03-01 13:43:16 +1100110static int kvmppc_get_dec_bits(void);
Andreas Färber5ba45762013-02-23 11:22:12 +0000111
Marcel Apfelbaumb16565b2015-02-04 17:43:51 +0200112int kvm_arch_init(MachineState *ms, KVMState *s)
aurel32d76d1652008-12-16 10:43:58 +0000113{
Alexander Graffc87e182010-08-30 13:49:15 +0200114 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
Scott Wood90dc8812011-04-29 17:10:23 -0500115 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
Scott Wood90dc8812011-04-29 17:10:23 -0500116 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
Greg Kurz6977afd2017-09-14 21:25:43 +0200117 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
David Gibson0f5cb292011-09-29 21:39:12 +0000118 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
Alexey Kardashevskiyd6ee2a72017-03-10 12:41:13 +1100119 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
Alexey Kardashevskiyda953242014-05-27 15:36:30 +1000120 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
Alexey Kardashevskiy9ded7802018-02-06 11:08:24 -0700121 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
David Gibsond67d40e2013-02-20 16:41:50 +0000122 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
David Gibsonf1af19d2012-09-12 16:57:09 +0000123 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
Stuart Yoder3b961122013-03-30 06:40:49 +0000124 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000125 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
David Gibsonc995e942019-03-21 21:47:25 +1100126 /*
127 * Note: we don't set cap_papr here, because this capability is
128 * only activated after this by kvmppc_set_papr()
129 */
Greg Kurz6977afd2017-09-14 21:25:43 +0200130 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
Alexander Graf87a91de2014-06-04 12:14:08 +0200131 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
Sam Bobrofffa98fbf2017-08-18 15:50:22 +1000132 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
Thomas Huthbac3bf22016-09-28 13:16:30 +0200133 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
Sam Bobroffcf1c4cc2017-03-20 10:46:44 +1100134 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
135 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
Cédric Le Goater38afd772019-05-13 10:42:33 +0200136 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
David Gibsonb55d2952017-07-12 17:56:55 +1000137 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
Suraj Jitindar Singh8acc2ae2018-01-19 15:59:59 +1100138 kvmppc_get_cpu_characteristics(s);
Suraj Jitindar Singhb9a477b2018-10-08 14:25:39 +1100139 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
Suraj Jitindar Singh7d050522019-03-01 13:43:16 +1100140 cap_large_decr = kvmppc_get_dec_bits();
Nicholas Pigginec010c02020-03-26 00:29:03 +1000141 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
Daniel Henrique Barbozac363a372017-08-09 17:43:46 -0300142 /*
143 * Note: setting it to false because there is not such capability
144 * in KVM at this moment.
145 *
146 * TODO: call kvm_vm_check_extension() with the right capability
David Gibsonc995e942019-03-21 21:47:25 +1100147 * after the kernel starts implementing it.
148 */
Daniel Henrique Barbozac363a372017-08-09 17:43:46 -0300149 cap_ppc_pvr_compat = false;
Alexander Graffc87e182010-08-30 13:49:15 +0200150
Shivaprasad G Bhat1e8f51e2019-07-25 09:15:08 -0500151 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
152 error_report("KVM: Host kernel doesn't have level irq capability");
153 exit(1);
Alexander Graffc87e182010-08-30 13:49:15 +0200154 }
155
Bharata B Rao82123b72021-07-06 16:54:40 +0530156 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
David Gibson165dc3e2019-10-30 17:20:35 +0100157 kvm_ppc_register_host_cpu_type();
Andreas Färber5ba45762013-02-23 11:22:12 +0000158
aurel32d76d1652008-12-16 10:43:58 +0000159 return 0;
160}
161
Paolo Bonzini4376c402019-11-13 11:17:12 +0100162int kvm_arch_irqchip_create(KVMState *s)
Paolo Bonzinid525ffa2016-12-22 16:41:42 +0100163{
164 return 0;
165}
166
Andreas Färber1bc22652012-10-31 06:06:49 +0100167static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
aurel32d76d1652008-12-16 10:43:58 +0000168{
Andreas Färber1bc22652012-10-31 06:06:49 +0100169 CPUPPCState *cenv = &cpu->env;
170 CPUState *cs = CPU(cpu);
Alexander Graf861bbc802009-07-17 13:51:43 +0200171 struct kvm_sregs sregs;
Scott Wood5666ca42011-04-11 18:34:34 -0500172 int ret;
173
174 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
David Gibsonc995e942019-03-21 21:47:25 +1100175 /*
176 * What we're really trying to say is "if we're on BookE, we
177 * use the native PVR for now". This is the only sane way to
178 * check it though, so we potentially confuse users that they
179 * can run BookE guests on BookS. Let's hope nobody dares
180 * enough :)
181 */
Scott Wood5666ca42011-04-11 18:34:34 -0500182 return 0;
183 } else {
Scott Wood90dc8812011-04-29 17:10:23 -0500184 if (!cap_segstate) {
Alexander Graf64e07be2011-04-16 02:00:36 +0200185 fprintf(stderr, "kvm error: missing PVR setting capability\n");
186 return -ENOSYS;
Scott Wood5666ca42011-04-11 18:34:34 -0500187 }
Scott Wood5666ca42011-04-11 18:34:34 -0500188 }
189
Andreas Färber1bc22652012-10-31 06:06:49 +0100190 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
Scott Wood5666ca42011-04-11 18:34:34 -0500191 if (ret) {
192 return ret;
193 }
Alexander Graf861bbc802009-07-17 13:51:43 +0200194
195 sregs.pvr = cenv->spr[SPR_PVR];
Andreas Färber1bc22652012-10-31 06:06:49 +0100196 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
Scott Wood5666ca42011-04-11 18:34:34 -0500197}
198
Scott Wood93dd5e82011-08-31 11:26:56 +0000199/* Set up a shared TLB array with KVM */
Andreas Färber1bc22652012-10-31 06:06:49 +0100200static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
Scott Wood93dd5e82011-08-31 11:26:56 +0000201{
Andreas Färber1bc22652012-10-31 06:06:49 +0100202 CPUPPCState *env = &cpu->env;
203 CPUState *cs = CPU(cpu);
Scott Wood93dd5e82011-08-31 11:26:56 +0000204 struct kvm_book3e_206_tlb_params params = {};
205 struct kvm_config_tlb cfg = {};
Scott Wood93dd5e82011-08-31 11:26:56 +0000206 unsigned int entries = 0;
207 int ret, i;
208
209 if (!kvm_enabled() ||
Andreas Färbera60f24b2012-12-01 05:35:08 +0100210 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
Scott Wood93dd5e82011-08-31 11:26:56 +0000211 return 0;
212 }
213
214 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
215
216 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
217 params.tlb_sizes[i] = booke206_tlb_size(env, i);
218 params.tlb_ways[i] = booke206_tlb_ways(env, i);
219 entries += params.tlb_sizes[i];
220 }
221
222 assert(entries == env->nb_tlb);
223 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
224
225 env->tlb_dirty = true;
226
227 cfg.array = (uintptr_t)env->tlb.tlbm;
228 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
229 cfg.params = (uintptr_t)&params;
230 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
231
Cornelia Huck48add812014-04-09 17:21:57 +0200232 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
Scott Wood93dd5e82011-08-31 11:26:56 +0000233 if (ret < 0) {
234 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
235 __func__, strerror(-ret));
236 return ret;
237 }
238
239 env->kvm_sw_tlb = true;
240 return 0;
241}
242
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000243
244#if defined(TARGET_PPC64)
Greg Kurzab256962018-06-29 11:48:32 +0200245static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000246{
247 int ret;
248
Greg Kurzab256962018-06-29 11:48:32 +0200249 assert(kvm_state != NULL);
250
251 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
Greg Kurz71d0f1e2018-06-29 11:48:16 +0200252 error_setg(errp, "KVM doesn't expose the MMU features it supports");
253 error_append_hint(errp, "Consider switching to a newer KVM\n");
254 return;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000255 }
256
Greg Kurzab256962018-06-29 11:48:32 +0200257 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
Greg Kurz71d0f1e2018-06-29 11:48:16 +0200258 if (ret == 0) {
259 return;
260 }
261
262 error_setg_errno(errp, -ret,
263 "KVM failed to provide the MMU features it supports");
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000264}
265
Sam Bobroffc64abd12017-03-20 10:46:43 +1100266struct ppc_radix_page_info *kvm_get_radix_page_info(void)
267{
Philippe Mathieu-Daudé4f7f5892020-01-21 12:03:48 +0100268 KVMState *s = KVM_STATE(current_accel());
Sam Bobroffc64abd12017-03-20 10:46:43 +1100269 struct ppc_radix_page_info *radix_page_info;
270 struct kvm_ppc_rmmu_info rmmu_info;
271 int i;
272
273 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
274 return NULL;
275 }
276 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
277 return NULL;
278 }
279 radix_page_info = g_malloc0(sizeof(*radix_page_info));
280 radix_page_info->count = 0;
281 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
282 if (rmmu_info.ap_encodings[i]) {
283 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
284 radix_page_info->count++;
285 }
286 }
287 return radix_page_info;
288}
289
Suraj Jitindar Singhb4db5412017-03-20 10:46:46 +1100290target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
291 bool radix, bool gtse,
292 uint64_t proc_tbl)
293{
294 CPUState *cs = CPU(cpu);
295 int ret;
296 uint64_t flags = 0;
297 struct kvm_ppc_mmuv3_cfg cfg = {
298 .process_table = proc_tbl,
299 };
300
301 if (radix) {
302 flags |= KVM_PPC_MMUV3_RADIX;
303 }
304 if (gtse) {
305 flags |= KVM_PPC_MMUV3_GTSE;
306 }
307 cfg.flags = flags;
308 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
309 switch (ret) {
310 case 0:
311 return H_SUCCESS;
312 case -EINVAL:
313 return H_PARAMETER;
314 case -ENODEV:
315 return H_NOT_AVAILABLE;
316 default:
317 return H_HARDWARE;
318 }
319}
320
David Gibson24c68632018-06-14 12:11:08 +1000321bool kvmppc_hpt_needs_host_contiguous_pages(void)
322{
David Gibson24c68632018-06-14 12:11:08 +1000323 static struct kvm_ppc_smmu_info smmu_info;
324
325 if (!kvm_enabled()) {
326 return false;
327 }
328
Greg Kurzab256962018-06-29 11:48:32 +0200329 kvm_get_smmu_info(&smmu_info, &error_fatal);
David Gibson24c68632018-06-14 12:11:08 +1000330 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
331}
332
David Gibsone5ca28e2018-04-16 16:19:52 +1000333void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000334{
David Gibsone5ca28e2018-04-16 16:19:52 +1000335 struct kvm_ppc_smmu_info smmu_info;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000336 int iq, ik, jq, jk;
Greg Kurz71d0f1e2018-06-29 11:48:16 +0200337 Error *local_err = NULL;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000338
David Gibsone5ca28e2018-04-16 16:19:52 +1000339 /* For now, we only have anything to check on hash64 MMUs */
340 if (!cpu->hash64_opts || !kvm_enabled()) {
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000341 return;
342 }
343
Greg Kurzab256962018-06-29 11:48:32 +0200344 kvm_get_smmu_info(&smmu_info, &local_err);
Greg Kurz71d0f1e2018-06-29 11:48:16 +0200345 if (local_err) {
346 error_propagate(errp, local_err);
347 return;
348 }
David Gibsone5ca28e2018-04-16 16:19:52 +1000349
350 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
351 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
352 error_setg(errp,
353 "KVM does not support 1TiB segments which guest expects");
354 return;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000355 }
356
David Gibsone5ca28e2018-04-16 16:19:52 +1000357 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
358 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
359 smmu_info.slb_size, cpu->hash64_opts->slb_size);
360 return;
Benjamin Herrenschmidt90da0d52015-10-22 18:30:59 +1100361 }
362
Alexander Graf08215d82014-05-11 18:37:00 +0200363 /*
David Gibsone5ca28e2018-04-16 16:19:52 +1000364 * Verify that every pagesize supported by the cpu model is
365 * supported by KVM with the same encodings
Alexander Graf08215d82014-05-11 18:37:00 +0200366 */
David Gibsone5ca28e2018-04-16 16:19:52 +1000367 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
David Gibsonb07c59f2018-03-23 13:31:52 +1100368 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
David Gibsone5ca28e2018-04-16 16:19:52 +1000369 struct kvm_ppc_one_seg_page_size *ksps;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000370
David Gibsone5ca28e2018-04-16 16:19:52 +1000371 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
372 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000373 break;
374 }
375 }
David Gibsone5ca28e2018-04-16 16:19:52 +1000376 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
377 error_setg(errp, "KVM doesn't support for base page shift %u",
378 qsps->page_shift);
379 return;
380 }
381
382 ksps = &smmu_info.sps[ik];
383 if (ksps->slb_enc != qsps->slb_enc) {
384 error_setg(errp,
385"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
386 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
387 return;
388 }
389
390 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
391 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
392 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
393 break;
394 }
395 }
396
397 if (jk >= ARRAY_SIZE(ksps->enc)) {
398 error_setg(errp, "KVM doesn't support page shift %u/%u",
399 qsps->enc[jq].page_shift, qsps->page_shift);
400 return;
401 }
402 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
403 error_setg(errp,
404"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
405 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
406 qsps->page_shift, qsps->enc[jq].pte_enc);
407 return;
408 }
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000409 }
410 }
David Gibsone5ca28e2018-04-16 16:19:52 +1000411
412 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
David Gibsonc995e942019-03-21 21:47:25 +1100413 /*
414 * Mostly what guest pagesizes we can use are related to the
David Gibsone5ca28e2018-04-16 16:19:52 +1000415 * host pages used to map guest RAM, which is handled in the
416 * platform code. Cache-Inhibited largepages (64k) however are
417 * used for I/O, so if they're mapped to the host at all it
418 * will be a normal mapping, not a special hugepage one used
David Gibsonc995e942019-03-21 21:47:25 +1100419 * for RAM.
420 */
Wei Yang038adc22019-10-13 10:11:45 +0800421 if (qemu_real_host_page_size < 0x10000) {
David Gibsone5ca28e2018-04-16 16:19:52 +1000422 error_setg(errp,
423 "KVM can't supply 64kiB CI pages, which guest expects");
424 }
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000425 }
426}
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000427#endif /* !defined (TARGET_PPC64) */
428
Eduardo Habkostb164e482013-01-22 18:25:01 -0200429unsigned long kvm_arch_vcpu_id(CPUState *cpu)
430{
Sam Bobroff2e886fb2017-08-09 15:38:56 +1000431 return POWERPC_CPU(cpu)->vcpu_id;
Eduardo Habkostb164e482013-01-22 18:25:01 -0200432}
433
David Gibsonc995e942019-03-21 21:47:25 +1100434/*
435 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
436 * only 1 watchpoint, so array size of 4 is sufficient for now.
Bharat Bhushan88365d12014-07-14 14:45:37 +0530437 */
438#define MAX_HW_BKPTS 4
439
440static struct HWBreakpoint {
441 target_ulong addr;
442 int type;
443} hw_debug_points[MAX_HW_BKPTS];
444
445static CPUWatchpoint hw_watchpoint;
446
447/* Default there is no breakpoint and watchpoint supported */
448static int max_hw_breakpoint;
449static int max_hw_watchpoint;
450static int nb_hw_breakpoint;
451static int nb_hw_watchpoint;
452
453static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
454{
455 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
456 max_hw_breakpoint = 2;
457 max_hw_watchpoint = 2;
458 }
459
460 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
461 fprintf(stderr, "Error initializing h/w breakpoints\n");
462 return;
463 }
464}
465
Andreas Färber20d695a2012-10-31 06:57:49 +0100466int kvm_arch_init_vcpu(CPUState *cs)
Scott Wood5666ca42011-04-11 18:34:34 -0500467{
Andreas Färber20d695a2012-10-31 06:57:49 +0100468 PowerPCCPU *cpu = POWERPC_CPU(cs);
469 CPUPPCState *cenv = &cpu->env;
Scott Wood5666ca42011-04-11 18:34:34 -0500470 int ret;
471
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000472 /* Synchronize sregs with kvm */
Andreas Färber1bc22652012-10-31 06:06:49 +0100473 ret = kvm_arch_sync_sregs(cpu);
Scott Wood5666ca42011-04-11 18:34:34 -0500474 if (ret) {
Thomas Huth388e47c2016-02-18 22:01:56 +0100475 if (ret == -EINVAL) {
476 error_report("Register sync failed... If you're using kvm-hv.ko,"
477 " only \"-cpu host\" is possible");
478 }
Scott Wood5666ca42011-04-11 18:34:34 -0500479 return ret;
480 }
Alexander Graf861bbc802009-07-17 13:51:43 +0200481
Scott Wood93dd5e82011-08-31 11:26:56 +0000482 switch (cenv->mmu_model) {
483 case POWERPC_MMU_BOOKE206:
Thomas Huth7f516c92016-09-29 12:48:07 +0200484 /* This target supports access to KVM's guest TLB */
Andreas Färber1bc22652012-10-31 06:06:49 +0100485 ret = kvm_booke206_tlb_init(cpu);
Scott Wood93dd5e82011-08-31 11:26:56 +0000486 break;
Thomas Huth7f516c92016-09-29 12:48:07 +0200487 case POWERPC_MMU_2_07:
488 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
David Gibsonc995e942019-03-21 21:47:25 +1100489 /*
490 * KVM-HV has transactional memory on POWER8 also without
491 * the KVM_CAP_PPC_HTM extension, so enable it here
zhaolichang136fbf62020-10-09 14:44:37 +0800492 * instead as long as it's available to userspace on the
David Gibsonc995e942019-03-21 21:47:25 +1100493 * host.
494 */
Sam Bobrofff3d9f302017-03-29 16:01:28 +1100495 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
496 cap_htm = true;
497 }
Thomas Huth7f516c92016-09-29 12:48:07 +0200498 }
499 break;
Scott Wood93dd5e82011-08-31 11:26:56 +0000500 default:
501 break;
502 }
503
Bharat Bhushan3c902d42014-07-14 14:45:35 +0530504 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
Bharat Bhushan88365d12014-07-14 14:45:37 +0530505 kvmppc_hw_debug_points_init(cenv);
Bharat Bhushan3c902d42014-07-14 14:45:35 +0530506
Alexander Graf861bbc802009-07-17 13:51:43 +0200507 return ret;
aurel32d76d1652008-12-16 10:43:58 +0000508}
509
Liran Alonb1115c92019-06-19 19:21:32 +0300510int kvm_arch_destroy_vcpu(CPUState *cs)
511{
512 return 0;
513}
514
Andreas Färber1bc22652012-10-31 06:06:49 +0100515static void kvm_sw_tlb_put(PowerPCCPU *cpu)
Scott Wood93dd5e82011-08-31 11:26:56 +0000516{
Andreas Färber1bc22652012-10-31 06:06:49 +0100517 CPUPPCState *env = &cpu->env;
518 CPUState *cs = CPU(cpu);
Scott Wood93dd5e82011-08-31 11:26:56 +0000519 struct kvm_dirty_tlb dirty_tlb;
520 unsigned char *bitmap;
521 int ret;
522
523 if (!env->kvm_sw_tlb) {
524 return;
525 }
526
527 bitmap = g_malloc((env->nb_tlb + 7) / 8);
528 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
529
530 dirty_tlb.bitmap = (uintptr_t)bitmap;
531 dirty_tlb.num_dirty = env->nb_tlb;
532
Andreas Färber1bc22652012-10-31 06:06:49 +0100533 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
Scott Wood93dd5e82011-08-31 11:26:56 +0000534 if (ret) {
535 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
536 __func__, strerror(-ret));
537 }
538
539 g_free(bitmap);
540}
541
David Gibsond67d40e2013-02-20 16:41:50 +0000542static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
543{
544 PowerPCCPU *cpu = POWERPC_CPU(cs);
545 CPUPPCState *env = &cpu->env;
546 union {
547 uint32_t u32;
548 uint64_t u64;
549 } val;
550 struct kvm_one_reg reg = {
551 .id = id,
552 .addr = (uintptr_t) &val,
553 };
554 int ret;
555
556 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
557 if (ret != 0) {
Alexey Kardashevskiyb36f1002014-02-04 15:12:34 +1100558 trace_kvm_failed_spr_get(spr, strerror(errno));
David Gibsond67d40e2013-02-20 16:41:50 +0000559 } else {
560 switch (id & KVM_REG_SIZE_MASK) {
561 case KVM_REG_SIZE_U32:
562 env->spr[spr] = val.u32;
563 break;
564
565 case KVM_REG_SIZE_U64:
566 env->spr[spr] = val.u64;
567 break;
568
569 default:
570 /* Don't handle this size yet */
571 abort();
572 }
573 }
574}
575
576static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
577{
578 PowerPCCPU *cpu = POWERPC_CPU(cs);
579 CPUPPCState *env = &cpu->env;
580 union {
581 uint32_t u32;
582 uint64_t u64;
583 } val;
584 struct kvm_one_reg reg = {
585 .id = id,
586 .addr = (uintptr_t) &val,
587 };
588 int ret;
589
590 switch (id & KVM_REG_SIZE_MASK) {
591 case KVM_REG_SIZE_U32:
592 val.u32 = env->spr[spr];
593 break;
594
595 case KVM_REG_SIZE_U64:
596 val.u64 = env->spr[spr];
597 break;
598
599 default:
600 /* Don't handle this size yet */
601 abort();
602 }
603
604 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
605 if (ret != 0) {
Alexey Kardashevskiyb36f1002014-02-04 15:12:34 +1100606 trace_kvm_failed_spr_set(spr, strerror(errno));
David Gibsond67d40e2013-02-20 16:41:50 +0000607 }
608}
609
David Gibson70b79842013-02-20 16:41:51 +0000610static int kvm_put_fp(CPUState *cs)
611{
612 PowerPCCPU *cpu = POWERPC_CPU(cs);
613 CPUPPCState *env = &cpu->env;
614 struct kvm_one_reg reg;
615 int i;
616 int ret;
617
618 if (env->insns_flags & PPC_FLOAT) {
619 uint64_t fpscr = env->fpscr;
620 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
621
622 reg.id = KVM_REG_PPC_FPSCR;
623 reg.addr = (uintptr_t)&fpscr;
624 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
625 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200626 trace_kvm_failed_fpscr_set(strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000627 return ret;
628 }
629
630 for (i = 0; i < 32; i++) {
631 uint64_t vsr[2];
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000632 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
633 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
David Gibson70b79842013-02-20 16:41:51 +0000634
Greg Kurz3a4b7912016-01-15 16:00:12 +0100635#ifdef HOST_WORDS_BIGENDIAN
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000636 vsr[0] = float64_val(*fpr);
637 vsr[1] = *vsrl;
Greg Kurz3a4b7912016-01-15 16:00:12 +0100638#else
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000639 vsr[0] = *vsrl;
640 vsr[1] = float64_val(*fpr);
Greg Kurz3a4b7912016-01-15 16:00:12 +0100641#endif
David Gibson70b79842013-02-20 16:41:51 +0000642 reg.addr = (uintptr_t) &vsr;
643 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
644
645 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
646 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200647 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
648 strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000649 return ret;
650 }
651 }
652 }
653
654 if (env->insns_flags & PPC_ALTIVEC) {
655 reg.id = KVM_REG_PPC_VSCR;
656 reg.addr = (uintptr_t)&env->vscr;
657 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
658 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200659 trace_kvm_failed_vscr_set(strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000660 return ret;
661 }
662
663 for (i = 0; i < 32; i++) {
664 reg.id = KVM_REG_PPC_VR(i);
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000665 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
David Gibson70b79842013-02-20 16:41:51 +0000666 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
667 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200668 trace_kvm_failed_vr_set(i, strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000669 return ret;
670 }
671 }
672 }
673
674 return 0;
675}
676
677static int kvm_get_fp(CPUState *cs)
678{
679 PowerPCCPU *cpu = POWERPC_CPU(cs);
680 CPUPPCState *env = &cpu->env;
681 struct kvm_one_reg reg;
682 int i;
683 int ret;
684
685 if (env->insns_flags & PPC_FLOAT) {
686 uint64_t fpscr;
687 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
688
689 reg.id = KVM_REG_PPC_FPSCR;
690 reg.addr = (uintptr_t)&fpscr;
691 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
692 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200693 trace_kvm_failed_fpscr_get(strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000694 return ret;
695 } else {
696 env->fpscr = fpscr;
697 }
698
699 for (i = 0; i < 32; i++) {
700 uint64_t vsr[2];
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000701 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
702 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
David Gibson70b79842013-02-20 16:41:51 +0000703
704 reg.addr = (uintptr_t) &vsr;
705 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
706
707 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
708 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200709 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
710 strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000711 return ret;
712 } else {
Greg Kurz3a4b7912016-01-15 16:00:12 +0100713#ifdef HOST_WORDS_BIGENDIAN
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000714 *fpr = vsr[0];
David Gibson70b79842013-02-20 16:41:51 +0000715 if (vsx) {
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000716 *vsrl = vsr[1];
David Gibson70b79842013-02-20 16:41:51 +0000717 }
Greg Kurz3a4b7912016-01-15 16:00:12 +0100718#else
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000719 *fpr = vsr[1];
Greg Kurz3a4b7912016-01-15 16:00:12 +0100720 if (vsx) {
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000721 *vsrl = vsr[0];
Greg Kurz3a4b7912016-01-15 16:00:12 +0100722 }
723#endif
David Gibson70b79842013-02-20 16:41:51 +0000724 }
725 }
726 }
727
728 if (env->insns_flags & PPC_ALTIVEC) {
729 reg.id = KVM_REG_PPC_VSCR;
730 reg.addr = (uintptr_t)&env->vscr;
731 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
732 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200733 trace_kvm_failed_vscr_get(strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000734 return ret;
735 }
736
737 for (i = 0; i < 32; i++) {
738 reg.id = KVM_REG_PPC_VR(i);
Mark Cave-Aylandef96e3a2019-01-02 09:14:22 +0000739 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
David Gibson70b79842013-02-20 16:41:51 +0000740 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
741 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200742 trace_kvm_failed_vr_get(i, strerror(errno));
David Gibson70b79842013-02-20 16:41:51 +0000743 return ret;
744 }
745 }
746 }
747
748 return 0;
749}
750
David Gibson9b00ea42013-04-07 19:08:22 +0000751#if defined(TARGET_PPC64)
752static int kvm_get_vpa(CPUState *cs)
753{
754 PowerPCCPU *cpu = POWERPC_CPU(cs);
David Gibsonce2918c2019-03-06 15:35:37 +1100755 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
David Gibson9b00ea42013-04-07 19:08:22 +0000756 struct kvm_one_reg reg;
757 int ret;
758
759 reg.id = KVM_REG_PPC_VPA_ADDR;
David Gibson7388efa2018-06-13 16:22:18 +1000760 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000761 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
762 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200763 trace_kvm_failed_vpa_addr_get(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000764 return ret;
765 }
766
David Gibson7388efa2018-06-13 16:22:18 +1000767 assert((uintptr_t)&spapr_cpu->slb_shadow_size
768 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
David Gibson9b00ea42013-04-07 19:08:22 +0000769 reg.id = KVM_REG_PPC_VPA_SLB;
David Gibson7388efa2018-06-13 16:22:18 +1000770 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000771 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
772 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200773 trace_kvm_failed_slb_get(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000774 return ret;
775 }
776
David Gibson7388efa2018-06-13 16:22:18 +1000777 assert((uintptr_t)&spapr_cpu->dtl_size
778 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
David Gibson9b00ea42013-04-07 19:08:22 +0000779 reg.id = KVM_REG_PPC_VPA_DTL;
David Gibson7388efa2018-06-13 16:22:18 +1000780 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000781 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
782 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200783 trace_kvm_failed_dtl_get(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000784 return ret;
785 }
786
787 return 0;
788}
789
790static int kvm_put_vpa(CPUState *cs)
791{
792 PowerPCCPU *cpu = POWERPC_CPU(cs);
David Gibsonce2918c2019-03-06 15:35:37 +1100793 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
David Gibson9b00ea42013-04-07 19:08:22 +0000794 struct kvm_one_reg reg;
795 int ret;
796
David Gibsonc995e942019-03-21 21:47:25 +1100797 /*
798 * SLB shadow or DTL can't be registered unless a master VPA is
David Gibson9b00ea42013-04-07 19:08:22 +0000799 * registered. That means when restoring state, if a VPA *is*
800 * registered, we need to set that up first. If not, we need to
David Gibsonc995e942019-03-21 21:47:25 +1100801 * deregister the others before deregistering the master VPA
802 */
David Gibson7388efa2018-06-13 16:22:18 +1000803 assert(spapr_cpu->vpa_addr
804 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
David Gibson9b00ea42013-04-07 19:08:22 +0000805
David Gibson7388efa2018-06-13 16:22:18 +1000806 if (spapr_cpu->vpa_addr) {
David Gibson9b00ea42013-04-07 19:08:22 +0000807 reg.id = KVM_REG_PPC_VPA_ADDR;
David Gibson7388efa2018-06-13 16:22:18 +1000808 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000809 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
810 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200811 trace_kvm_failed_vpa_addr_set(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000812 return ret;
813 }
814 }
815
David Gibson7388efa2018-06-13 16:22:18 +1000816 assert((uintptr_t)&spapr_cpu->slb_shadow_size
817 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
David Gibson9b00ea42013-04-07 19:08:22 +0000818 reg.id = KVM_REG_PPC_VPA_SLB;
David Gibson7388efa2018-06-13 16:22:18 +1000819 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000820 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
821 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200822 trace_kvm_failed_slb_set(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000823 return ret;
824 }
825
David Gibson7388efa2018-06-13 16:22:18 +1000826 assert((uintptr_t)&spapr_cpu->dtl_size
827 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
David Gibson9b00ea42013-04-07 19:08:22 +0000828 reg.id = KVM_REG_PPC_VPA_DTL;
David Gibson7388efa2018-06-13 16:22:18 +1000829 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000830 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
831 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200832 trace_kvm_failed_dtl_set(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000833 return ret;
834 }
835
David Gibson7388efa2018-06-13 16:22:18 +1000836 if (!spapr_cpu->vpa_addr) {
David Gibson9b00ea42013-04-07 19:08:22 +0000837 reg.id = KVM_REG_PPC_VPA_ADDR;
David Gibson7388efa2018-06-13 16:22:18 +1000838 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
David Gibson9b00ea42013-04-07 19:08:22 +0000839 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
840 if (ret < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200841 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
David Gibson9b00ea42013-04-07 19:08:22 +0000842 return ret;
843 }
844 }
845
846 return 0;
847}
848#endif /* TARGET_PPC64 */
849
David Gibsone5c0d3c2016-03-08 11:33:46 +1100850int kvmppc_put_books_sregs(PowerPCCPU *cpu)
David Gibsona7a00a72016-03-09 11:58:33 +1100851{
852 CPUPPCState *env = &cpu->env;
853 struct kvm_sregs sregs;
854 int i;
855
856 sregs.pvr = env->spr[SPR_PVR];
857
Greg Kurz1ec26c72017-09-25 13:00:02 +0200858 if (cpu->vhyp) {
859 PPCVirtualHypervisorClass *vhc =
860 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
861 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
862 } else {
863 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
864 }
David Gibsona7a00a72016-03-09 11:58:33 +1100865
866 /* Sync SLB */
867#ifdef TARGET_PPC64
868 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
869 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
870 if (env->slb[i].esid & SLB_ESID_V) {
871 sregs.u.s.ppc64.slb[i].slbe |= i;
872 }
873 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
874 }
875#endif
876
877 /* Sync SRs */
878 for (i = 0; i < 16; i++) {
879 sregs.u.s.ppc32.sr[i] = env->sr[i];
880 }
881
882 /* Sync BATs */
883 for (i = 0; i < 8; i++) {
884 /* Beware. We have to swap upper and lower bits here */
885 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
886 | env->DBAT[1][i];
887 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
888 | env->IBAT[1][i];
889 }
890
891 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
892}
893
Andreas Färber20d695a2012-10-31 06:57:49 +0100894int kvm_arch_put_registers(CPUState *cs, int level)
aurel32d76d1652008-12-16 10:43:58 +0000895{
Andreas Färber20d695a2012-10-31 06:57:49 +0100896 PowerPCCPU *cpu = POWERPC_CPU(cs);
897 CPUPPCState *env = &cpu->env;
aurel32d76d1652008-12-16 10:43:58 +0000898 struct kvm_regs regs;
899 int ret;
900 int i;
901
Andreas Färber1bc22652012-10-31 06:06:49 +0100902 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
903 if (ret < 0) {
aurel32d76d1652008-12-16 10:43:58 +0000904 return ret;
Andreas Färber1bc22652012-10-31 06:06:49 +0100905 }
aurel32d76d1652008-12-16 10:43:58 +0000906
907 regs.ctr = env->ctr;
908 regs.lr = env->lr;
Richard Hendersonda91a002013-02-19 23:52:13 -0800909 regs.xer = cpu_read_xer(env);
aurel32d76d1652008-12-16 10:43:58 +0000910 regs.msr = env->msr;
911 regs.pc = env->nip;
912
913 regs.srr0 = env->spr[SPR_SRR0];
914 regs.srr1 = env->spr[SPR_SRR1];
915
916 regs.sprg0 = env->spr[SPR_SPRG0];
917 regs.sprg1 = env->spr[SPR_SPRG1];
918 regs.sprg2 = env->spr[SPR_SPRG2];
919 regs.sprg3 = env->spr[SPR_SPRG3];
920 regs.sprg4 = env->spr[SPR_SPRG4];
921 regs.sprg5 = env->spr[SPR_SPRG5];
922 regs.sprg6 = env->spr[SPR_SPRG6];
923 regs.sprg7 = env->spr[SPR_SPRG7];
924
Scott Wood90dc8812011-04-29 17:10:23 -0500925 regs.pid = env->spr[SPR_BOOKE_PID];
926
David Gibsonc995e942019-03-21 21:47:25 +1100927 for (i = 0; i < 32; i++) {
aurel32d76d1652008-12-16 10:43:58 +0000928 regs.gpr[i] = env->gpr[i];
David Gibsonc995e942019-03-21 21:47:25 +1100929 }
aurel32d76d1652008-12-16 10:43:58 +0000930
Alexey Kardashevskiy4bddaf52013-06-15 11:51:51 +1000931 regs.cr = 0;
932 for (i = 0; i < 8; i++) {
933 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
934 }
935
Andreas Färber1bc22652012-10-31 06:06:49 +0100936 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
David Gibsonc995e942019-03-21 21:47:25 +1100937 if (ret < 0) {
aurel32d76d1652008-12-16 10:43:58 +0000938 return ret;
David Gibsonc995e942019-03-21 21:47:25 +1100939 }
aurel32d76d1652008-12-16 10:43:58 +0000940
David Gibson70b79842013-02-20 16:41:51 +0000941 kvm_put_fp(cs);
942
Scott Wood93dd5e82011-08-31 11:26:56 +0000943 if (env->tlb_dirty) {
Andreas Färber1bc22652012-10-31 06:06:49 +0100944 kvm_sw_tlb_put(cpu);
Scott Wood93dd5e82011-08-31 11:26:56 +0000945 env->tlb_dirty = false;
946 }
947
David Gibsonf1af19d2012-09-12 16:57:09 +0000948 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
David Gibsona7a00a72016-03-09 11:58:33 +1100949 ret = kvmppc_put_books_sregs(cpu);
950 if (ret < 0) {
David Gibsonf1af19d2012-09-12 16:57:09 +0000951 return ret;
952 }
953 }
954
955 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
David Gibsond67d40e2013-02-20 16:41:50 +0000956 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
957 }
David Gibsonf1af19d2012-09-12 16:57:09 +0000958
David Gibsond67d40e2013-02-20 16:41:50 +0000959 if (cap_one_reg) {
960 int i;
961
David Gibsonc995e942019-03-21 21:47:25 +1100962 /*
963 * We deliberately ignore errors here, for kernels which have
David Gibsond67d40e2013-02-20 16:41:50 +0000964 * the ONE_REG calls, but don't support the specific
965 * registers, there's a reasonable chance things will still
David Gibsonc995e942019-03-21 21:47:25 +1100966 * work, at least until we try to migrate.
967 */
David Gibsond67d40e2013-02-20 16:41:50 +0000968 for (i = 0; i < 1024; i++) {
969 uint64_t id = env->spr_cb[i].one_reg_id;
970
971 if (id != 0) {
972 kvm_put_one_spr(cs, id, i);
973 }
David Gibsonf1af19d2012-09-12 16:57:09 +0000974 }
David Gibson9b00ea42013-04-07 19:08:22 +0000975
976#ifdef TARGET_PPC64
Alexey Kardashevskiy80b3f792014-06-04 22:51:00 +1000977 if (msr_ts) {
978 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
980 }
981 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
983 }
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
994 }
995
David Gibson9b00ea42013-04-07 19:08:22 +0000996 if (cap_papr) {
997 if (kvm_put_vpa(cs) < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +0200998 trace_kvm_failed_put_vpa();
David Gibson9b00ea42013-04-07 19:08:22 +0000999 }
1000 }
Alexey Kardashevskiy98a8b522014-05-01 20:37:09 +10001001
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
Alexey Kardashevskiy972bd572019-09-23 18:41:10 +10001003
1004 if (level > KVM_PUT_RUNTIME_STATE) {
1005 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1006 }
David Gibson9b00ea42013-04-07 19:08:22 +00001007#endif /* TARGET_PPC64 */
David Gibsonf1af19d2012-09-12 16:57:09 +00001008 }
1009
aurel32d76d1652008-12-16 10:43:58 +00001010 return ret;
1011}
1012
Bharat Bhushanc371c2e2014-07-14 14:45:36 +05301013static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1014{
1015 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1016}
1017
David Gibsona7a00a72016-03-09 11:58:33 +11001018static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1019{
1020 CPUPPCState *env = &cpu->env;
1021 struct kvm_sregs sregs;
1022 int ret;
1023
1024 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1025 if (ret < 0) {
1026 return ret;
1027 }
1028
1029 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1030 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1031 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1032 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1033 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1034 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1035 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1036 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1037 env->spr[SPR_DECR] = sregs.u.e.dec;
1038 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1039 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1040 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1041 }
1042
1043 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1044 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1045 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1046 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1047 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1048 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1049 }
1050
1051 if (sregs.u.e.features & KVM_SREGS_E_64) {
1052 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1053 }
1054
1055 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1056 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1057 }
1058
1059 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1060 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1061 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1062 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1063 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1064 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1065 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1066 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1067 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1068 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1069 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1070 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1071 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1072 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1073 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1074 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1075 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1076 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1077 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1078 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1079 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1080 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1081 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1082 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1083 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1084 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1085 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1086 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1087 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1088 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1089 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1090 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1091 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1092
1093 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1094 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1095 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1096 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1097 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1098 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1099 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1100 }
1101
1102 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1103 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1104 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1105 }
1106
1107 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1108 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1109 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1110 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1111 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1112 }
1113 }
1114
1115 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1116 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1117 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1118 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1119 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1120 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1121 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1122 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1123 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1124 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1125 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1126 }
1127
1128 if (sregs.u.e.features & KVM_SREGS_EXP) {
1129 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1130 }
1131
1132 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1133 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1134 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1135 }
1136
1137 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1138 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1139 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1140 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1141
1142 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1143 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1144 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1145 }
1146 }
1147
1148 return 0;
1149}
1150
1151static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1152{
1153 CPUPPCState *env = &cpu->env;
1154 struct kvm_sregs sregs;
1155 int ret;
1156 int i;
1157
1158 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1159 if (ret < 0) {
1160 return ret;
1161 }
1162
David Gibsone57ca752017-02-23 11:39:18 +11001163 if (!cpu->vhyp) {
David Gibsona7a00a72016-03-09 11:58:33 +11001164 ppc_store_sdr1(env, sregs.u.s.sdr1);
1165 }
1166
1167 /* Sync SLB */
1168#ifdef TARGET_PPC64
1169 /*
1170 * The packed SLB array we get from KVM_GET_SREGS only contains
1171 * information about valid entries. So we flush our internal copy
1172 * to get rid of stale ones, then put all valid SLB entries back
1173 * in.
1174 */
1175 memset(env->slb, 0, sizeof(env->slb));
1176 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1177 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1178 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1179 /*
1180 * Only restore valid entries
1181 */
1182 if (rb & SLB_ESID_V) {
1183 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1184 }
1185 }
1186#endif
1187
1188 /* Sync SRs */
1189 for (i = 0; i < 16; i++) {
1190 env->sr[i] = sregs.u.s.ppc32.sr[i];
1191 }
1192
1193 /* Sync BATs */
1194 for (i = 0; i < 8; i++) {
1195 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1196 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1197 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1198 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1199 }
1200
1201 return 0;
1202}
1203
Andreas Färber20d695a2012-10-31 06:57:49 +01001204int kvm_arch_get_registers(CPUState *cs)
aurel32d76d1652008-12-16 10:43:58 +00001205{
Andreas Färber20d695a2012-10-31 06:57:49 +01001206 PowerPCCPU *cpu = POWERPC_CPU(cs);
1207 CPUPPCState *env = &cpu->env;
aurel32d76d1652008-12-16 10:43:58 +00001208 struct kvm_regs regs;
Scott Wood90dc8812011-04-29 17:10:23 -05001209 uint32_t cr;
Alexander Graf138b38b2010-11-25 08:20:46 +01001210 int i, ret;
aurel32d76d1652008-12-16 10:43:58 +00001211
Andreas Färber1bc22652012-10-31 06:06:49 +01001212 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
David Gibsonc995e942019-03-21 21:47:25 +11001213 if (ret < 0) {
aurel32d76d1652008-12-16 10:43:58 +00001214 return ret;
David Gibsonc995e942019-03-21 21:47:25 +11001215 }
aurel32d76d1652008-12-16 10:43:58 +00001216
Scott Wood90dc8812011-04-29 17:10:23 -05001217 cr = regs.cr;
1218 for (i = 7; i >= 0; i--) {
1219 env->crf[i] = cr & 15;
1220 cr >>= 4;
1221 }
Alexander Grafba5e5092009-12-02 23:19:47 +01001222
aurel32d76d1652008-12-16 10:43:58 +00001223 env->ctr = regs.ctr;
1224 env->lr = regs.lr;
Richard Hendersonda91a002013-02-19 23:52:13 -08001225 cpu_write_xer(env, regs.xer);
aurel32d76d1652008-12-16 10:43:58 +00001226 env->msr = regs.msr;
1227 env->nip = regs.pc;
1228
1229 env->spr[SPR_SRR0] = regs.srr0;
1230 env->spr[SPR_SRR1] = regs.srr1;
1231
1232 env->spr[SPR_SPRG0] = regs.sprg0;
1233 env->spr[SPR_SPRG1] = regs.sprg1;
1234 env->spr[SPR_SPRG2] = regs.sprg2;
1235 env->spr[SPR_SPRG3] = regs.sprg3;
1236 env->spr[SPR_SPRG4] = regs.sprg4;
1237 env->spr[SPR_SPRG5] = regs.sprg5;
1238 env->spr[SPR_SPRG6] = regs.sprg6;
1239 env->spr[SPR_SPRG7] = regs.sprg7;
1240
Scott Wood90dc8812011-04-29 17:10:23 -05001241 env->spr[SPR_BOOKE_PID] = regs.pid;
1242
David Gibsonc995e942019-03-21 21:47:25 +11001243 for (i = 0; i < 32; i++) {
aurel32d76d1652008-12-16 10:43:58 +00001244 env->gpr[i] = regs.gpr[i];
David Gibsonc995e942019-03-21 21:47:25 +11001245 }
aurel32d76d1652008-12-16 10:43:58 +00001246
David Gibson70b79842013-02-20 16:41:51 +00001247 kvm_get_fp(cs);
1248
Scott Wood90dc8812011-04-29 17:10:23 -05001249 if (cap_booke_sregs) {
David Gibsona7a00a72016-03-09 11:58:33 +11001250 ret = kvmppc_get_booke_sregs(cpu);
Scott Wood90dc8812011-04-29 17:10:23 -05001251 if (ret < 0) {
1252 return ret;
1253 }
Alexander Graffafc0b62011-05-25 15:04:42 +02001254 }
Scott Wood90dc8812011-04-29 17:10:23 -05001255
Scott Wood90dc8812011-04-29 17:10:23 -05001256 if (cap_segstate) {
David Gibsona7a00a72016-03-09 11:58:33 +11001257 ret = kvmppc_get_books_sregs(cpu);
Scott Wood90dc8812011-04-29 17:10:23 -05001258 if (ret < 0) {
1259 return ret;
1260 }
Alexander Graffafc0b62011-05-25 15:04:42 +02001261 }
Alexander Grafba5e5092009-12-02 23:19:47 +01001262
David Gibsond67d40e2013-02-20 16:41:50 +00001263 if (cap_hior) {
1264 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1265 }
1266
1267 if (cap_one_reg) {
1268 int i;
1269
David Gibsonc995e942019-03-21 21:47:25 +11001270 /*
1271 * We deliberately ignore errors here, for kernels which have
David Gibsond67d40e2013-02-20 16:41:50 +00001272 * the ONE_REG calls, but don't support the specific
1273 * registers, there's a reasonable chance things will still
David Gibsonc995e942019-03-21 21:47:25 +11001274 * work, at least until we try to migrate.
1275 */
David Gibsond67d40e2013-02-20 16:41:50 +00001276 for (i = 0; i < 1024; i++) {
1277 uint64_t id = env->spr_cb[i].one_reg_id;
1278
1279 if (id != 0) {
1280 kvm_get_one_spr(cs, id, i);
1281 }
1282 }
David Gibson9b00ea42013-04-07 19:08:22 +00001283
1284#ifdef TARGET_PPC64
Alexey Kardashevskiy80b3f792014-06-04 22:51:00 +10001285 if (msr_ts) {
1286 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1288 }
1289 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1291 }
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1301 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1302 }
1303
David Gibson9b00ea42013-04-07 19:08:22 +00001304 if (cap_papr) {
1305 if (kvm_get_vpa(cs) < 0) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001306 trace_kvm_failed_get_vpa();
David Gibson9b00ea42013-04-07 19:08:22 +00001307 }
1308 }
Alexey Kardashevskiy98a8b522014-05-01 20:37:09 +10001309
1310 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
Alexey Kardashevskiy972bd572019-09-23 18:41:10 +10001311 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
David Gibson9b00ea42013-04-07 19:08:22 +00001312#endif
David Gibsond67d40e2013-02-20 16:41:50 +00001313 }
1314
aurel32d76d1652008-12-16 10:43:58 +00001315 return 0;
1316}
1317
Andreas Färber1bc22652012-10-31 06:06:49 +01001318int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
Alexander Graffc87e182010-08-30 13:49:15 +02001319{
1320 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1321
1322 if (irq != PPC_INTERRUPT_EXT) {
1323 return 0;
1324 }
1325
Shivaprasad G Bhat1e8f51e2019-07-25 09:15:08 -05001326 if (!kvm_enabled() || !cap_interrupt_unset) {
Alexander Graffc87e182010-08-30 13:49:15 +02001327 return 0;
1328 }
1329
Andreas Färber1bc22652012-10-31 06:06:49 +01001330 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
Alexander Graffc87e182010-08-30 13:49:15 +02001331
1332 return 0;
1333}
1334
Andreas Färber20d695a2012-10-31 06:57:49 +01001335void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
aurel32d76d1652008-12-16 10:43:58 +00001336{
Shivaprasad G Bhat1e8f51e2019-07-25 09:15:08 -05001337 return;
aurel32d76d1652008-12-16 10:43:58 +00001338}
1339
Paolo Bonzini4c663752015-04-08 13:30:58 +02001340MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
aurel32d76d1652008-12-16 10:43:58 +00001341{
Paolo Bonzini4c663752015-04-08 13:30:58 +02001342 return MEMTXATTRS_UNSPECIFIED;
aurel32d76d1652008-12-16 10:43:58 +00001343}
1344
Andreas Färber20d695a2012-10-31 06:57:49 +01001345int kvm_arch_process_async_events(CPUState *cs)
Marcelo Tosatti0af691d2010-05-04 09:45:27 -03001346{
Andreas Färber259186a2013-01-17 18:51:17 +01001347 return cs->halted;
Marcelo Tosatti0af691d2010-05-04 09:45:27 -03001348}
1349
Andreas Färber259186a2013-01-17 18:51:17 +01001350static int kvmppc_handle_halt(PowerPCCPU *cpu)
aurel32d76d1652008-12-16 10:43:58 +00001351{
Andreas Färber259186a2013-01-17 18:51:17 +01001352 CPUState *cs = CPU(cpu);
1353 CPUPPCState *env = &cpu->env;
1354
1355 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1356 cs->halted = 1;
Andreas Färber27103422013-08-26 08:31:06 +02001357 cs->exception_index = EXCP_HLT;
aurel32d76d1652008-12-16 10:43:58 +00001358 }
1359
Jan Kiszkabb4ea392011-03-15 12:26:28 +01001360 return 0;
aurel32d76d1652008-12-16 10:43:58 +00001361}
1362
1363/* map dcr access to existing qemu dcr emulation */
David Gibsonc995e942019-03-21 21:47:25 +11001364static int kvmppc_handle_dcr_read(CPUPPCState *env,
1365 uint32_t dcrn, uint32_t *data)
aurel32d76d1652008-12-16 10:43:58 +00001366{
David Gibsonc995e942019-03-21 21:47:25 +11001367 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
aurel32d76d1652008-12-16 10:43:58 +00001368 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
David Gibsonc995e942019-03-21 21:47:25 +11001369 }
aurel32d76d1652008-12-16 10:43:58 +00001370
Jan Kiszkabb4ea392011-03-15 12:26:28 +01001371 return 0;
aurel32d76d1652008-12-16 10:43:58 +00001372}
1373
David Gibsonc995e942019-03-21 21:47:25 +11001374static int kvmppc_handle_dcr_write(CPUPPCState *env,
1375 uint32_t dcrn, uint32_t data)
aurel32d76d1652008-12-16 10:43:58 +00001376{
David Gibsonc995e942019-03-21 21:47:25 +11001377 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
aurel32d76d1652008-12-16 10:43:58 +00001378 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
David Gibsonc995e942019-03-21 21:47:25 +11001379 }
aurel32d76d1652008-12-16 10:43:58 +00001380
Jan Kiszkabb4ea392011-03-15 12:26:28 +01001381 return 0;
aurel32d76d1652008-12-16 10:43:58 +00001382}
1383
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301384int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1385{
1386 /* Mixed endian case is not handled */
1387 uint32_t sc = debug_inst_opcode;
1388
1389 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1390 sizeof(sc), 0) ||
1391 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1392 return -EINVAL;
1393 }
1394
1395 return 0;
1396}
1397
1398int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1399{
1400 uint32_t sc;
1401
1402 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1403 sc != debug_inst_opcode ||
1404 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1405 sizeof(sc), 1)) {
1406 return -EINVAL;
1407 }
1408
1409 return 0;
1410}
1411
Bharat Bhushan88365d12014-07-14 14:45:37 +05301412static int find_hw_breakpoint(target_ulong addr, int type)
1413{
1414 int n;
1415
1416 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1417 <= ARRAY_SIZE(hw_debug_points));
1418
1419 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1420 if (hw_debug_points[n].addr == addr &&
1421 hw_debug_points[n].type == type) {
1422 return n;
1423 }
1424 }
1425
1426 return -1;
1427}
1428
1429static int find_hw_watchpoint(target_ulong addr, int *flag)
1430{
1431 int n;
1432
1433 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1434 if (n >= 0) {
1435 *flag = BP_MEM_ACCESS;
1436 return n;
1437 }
1438
1439 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1440 if (n >= 0) {
1441 *flag = BP_MEM_WRITE;
1442 return n;
1443 }
1444
1445 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1446 if (n >= 0) {
1447 *flag = BP_MEM_READ;
1448 return n;
1449 }
1450
1451 return -1;
1452}
1453
1454int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1455 target_ulong len, int type)
1456{
1457 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1458 return -ENOBUFS;
1459 }
1460
1461 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1462 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1463
1464 switch (type) {
1465 case GDB_BREAKPOINT_HW:
1466 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1467 return -ENOBUFS;
1468 }
1469
1470 if (find_hw_breakpoint(addr, type) >= 0) {
1471 return -EEXIST;
1472 }
1473
1474 nb_hw_breakpoint++;
1475 break;
1476
1477 case GDB_WATCHPOINT_WRITE:
1478 case GDB_WATCHPOINT_READ:
1479 case GDB_WATCHPOINT_ACCESS:
1480 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1481 return -ENOBUFS;
1482 }
1483
1484 if (find_hw_breakpoint(addr, type) >= 0) {
1485 return -EEXIST;
1486 }
1487
1488 nb_hw_watchpoint++;
1489 break;
1490
1491 default:
1492 return -ENOSYS;
1493 }
1494
1495 return 0;
1496}
1497
1498int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1499 target_ulong len, int type)
1500{
1501 int n;
1502
1503 n = find_hw_breakpoint(addr, type);
1504 if (n < 0) {
1505 return -ENOENT;
1506 }
1507
1508 switch (type) {
1509 case GDB_BREAKPOINT_HW:
1510 nb_hw_breakpoint--;
1511 break;
1512
1513 case GDB_WATCHPOINT_WRITE:
1514 case GDB_WATCHPOINT_READ:
1515 case GDB_WATCHPOINT_ACCESS:
1516 nb_hw_watchpoint--;
1517 break;
1518
1519 default:
1520 return -ENOSYS;
1521 }
1522 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1523
1524 return 0;
1525}
1526
1527void kvm_arch_remove_all_hw_breakpoints(void)
1528{
1529 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1530}
1531
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301532void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1533{
Bharat Bhushan88365d12014-07-14 14:45:37 +05301534 int n;
1535
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301536 /* Software Breakpoint updates */
1537 if (kvm_sw_breakpoints_active(cs)) {
1538 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1539 }
Bharat Bhushan88365d12014-07-14 14:45:37 +05301540
1541 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1542 <= ARRAY_SIZE(hw_debug_points));
1543 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1544
1545 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1546 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1547 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1548 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1549 switch (hw_debug_points[n].type) {
1550 case GDB_BREAKPOINT_HW:
1551 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1552 break;
1553 case GDB_WATCHPOINT_WRITE:
1554 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1555 break;
1556 case GDB_WATCHPOINT_READ:
1557 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1558 break;
1559 case GDB_WATCHPOINT_ACCESS:
1560 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1561 KVMPPC_DEBUG_WATCH_READ;
1562 break;
1563 default:
1564 cpu_abort(cs, "Unsupported breakpoint type\n");
1565 }
1566 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1567 }
1568 }
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301569}
1570
Fabiano Rosas2cbd1582019-02-28 19:57:57 -03001571static int kvm_handle_hw_breakpoint(CPUState *cs,
1572 struct kvm_debug_exit_arch *arch_info)
1573{
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001574 int handle = DEBUG_RETURN_GUEST;
Fabiano Rosas2cbd1582019-02-28 19:57:57 -03001575 int n;
1576 int flag = 0;
1577
1578 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1579 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1580 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1581 if (n >= 0) {
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001582 handle = DEBUG_RETURN_GDB;
Fabiano Rosas2cbd1582019-02-28 19:57:57 -03001583 }
1584 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1585 KVMPPC_DEBUG_WATCH_WRITE)) {
1586 n = find_hw_watchpoint(arch_info->address, &flag);
1587 if (n >= 0) {
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001588 handle = DEBUG_RETURN_GDB;
Fabiano Rosas2cbd1582019-02-28 19:57:57 -03001589 cs->watchpoint_hit = &hw_watchpoint;
1590 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1591 hw_watchpoint.flags = flag;
1592 }
1593 }
1594 }
1595 return handle;
1596}
1597
Fabiano Rosas468e3a12019-02-28 19:57:58 -03001598static int kvm_handle_singlestep(void)
1599{
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001600 return DEBUG_RETURN_GDB;
Fabiano Rosas468e3a12019-02-28 19:57:58 -03001601}
1602
1603static int kvm_handle_sw_breakpoint(void)
1604{
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001605 return DEBUG_RETURN_GDB;
Fabiano Rosas468e3a12019-02-28 19:57:58 -03001606}
1607
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301608static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1609{
1610 CPUState *cs = CPU(cpu);
1611 CPUPPCState *env = &cpu->env;
1612 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301613
Bharat Bhushan88365d12014-07-14 14:45:37 +05301614 if (cs->singlestep_enabled) {
Fabiano Rosas468e3a12019-02-28 19:57:58 -03001615 return kvm_handle_singlestep();
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301616 }
1617
Fabiano Rosas468e3a12019-02-28 19:57:58 -03001618 if (arch_info->status) {
1619 return kvm_handle_hw_breakpoint(cs, arch_info);
1620 }
1621
1622 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1623 return kvm_handle_sw_breakpoint();
1624 }
1625
1626 /*
1627 * QEMU is not able to handle debug exception, so inject
1628 * program exception to guest;
1629 * Yes program exception NOT debug exception !!
1630 * When QEMU is using debug resources then debug exception must
1631 * be always set. To achieve this we set MSR_DE and also set
1632 * MSRP_DEP so guest cannot change MSR_DE.
1633 * When emulating debug resource for guest we want guest
1634 * to control MSR_DE (enable/disable debug interrupt on need).
1635 * Supporting both configurations are NOT possible.
1636 * So the result is that we cannot share debug resources
1637 * between QEMU and Guest on BOOKE architecture.
1638 * In the current design QEMU gets the priority over guest,
1639 * this means that if QEMU is using debug resources then guest
1640 * cannot use them;
1641 * For software breakpoint QEMU uses a privileged instruction;
1642 * So there cannot be any reason that we are here for guest
1643 * set debug exception, only possibility is guest executed a
1644 * privileged / illegal instruction and that's why we are
1645 * injecting a program interrupt.
1646 */
1647 cpu_synchronize_state(cs);
1648 /*
1649 * env->nip is PC, so increment this by 4 to use
1650 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1651 */
1652 env->nip += 4;
1653 cs->exception_index = POWERPC_EXCP_PROGRAM;
1654 env->error_code = POWERPC_EXCP_INVAL;
1655 ppc_cpu_do_interrupt(cs);
1656
Fabiano Rosas6e0552a2020-01-10 12:13:42 -03001657 return DEBUG_RETURN_GUEST;
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301658}
1659
Andreas Färber20d695a2012-10-31 06:57:49 +01001660int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
aurel32d76d1652008-12-16 10:43:58 +00001661{
Andreas Färber20d695a2012-10-31 06:57:49 +01001662 PowerPCCPU *cpu = POWERPC_CPU(cs);
1663 CPUPPCState *env = &cpu->env;
Jan Kiszkabb4ea392011-03-15 12:26:28 +01001664 int ret;
aurel32d76d1652008-12-16 10:43:58 +00001665
Jan Kiszka4b8523e2015-06-18 18:47:23 +02001666 qemu_mutex_lock_iothread();
1667
aurel32d76d1652008-12-16 10:43:58 +00001668 switch (run->exit_reason) {
1669 case KVM_EXIT_DCR:
1670 if (run->dcr.is_write) {
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001671 trace_kvm_handle_dcr_write();
aurel32d76d1652008-12-16 10:43:58 +00001672 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1673 } else {
Boxuan Li228152c22019-05-01 01:28:42 +08001674 trace_kvm_handle_dcr_read();
aurel32d76d1652008-12-16 10:43:58 +00001675 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1676 }
1677 break;
1678 case KVM_EXIT_HLT:
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001679 trace_kvm_handle_halt();
Andreas Färber259186a2013-01-17 18:51:17 +01001680 ret = kvmppc_handle_halt(cpu);
aurel32d76d1652008-12-16 10:43:58 +00001681 break;
David Gibsonc6304a42013-03-13 15:53:27 +00001682#if defined(TARGET_PPC64)
Alexander Graff61b4be2011-08-09 17:57:37 +02001683 case KVM_EXIT_PAPR_HCALL:
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001684 trace_kvm_handle_papr_hcall();
Andreas Färber20d695a2012-10-31 06:57:49 +01001685 run->papr_hcall.ret = spapr_hypercall(cpu,
Andreas Färberaa100fa2012-05-03 06:13:14 +02001686 run->papr_hcall.nr,
Alexander Graff61b4be2011-08-09 17:57:37 +02001687 run->papr_hcall.args);
David Gibson78e8fde2012-08-06 18:44:45 +00001688 ret = 0;
Alexander Graff61b4be2011-08-09 17:57:37 +02001689 break;
1690#endif
Alexander Graf5b95b8b2013-01-17 11:54:38 +01001691 case KVM_EXIT_EPR:
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001692 trace_kvm_handle_epr();
Alexander Graf933b19e2014-02-14 09:15:21 +01001693 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
Alexander Graf5b95b8b2013-01-17 11:54:38 +01001694 ret = 0;
1695 break;
Bharat Bhushan31f2cb82013-02-24 18:16:21 +00001696 case KVM_EXIT_WATCHDOG:
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001697 trace_kvm_handle_watchdog_expiry();
Bharat Bhushan31f2cb82013-02-24 18:16:21 +00001698 watchdog_perform_action();
1699 ret = 0;
1700 break;
1701
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301702 case KVM_EXIT_DEBUG:
Greg Kurz8d83cbf2019-04-05 10:05:24 +02001703 trace_kvm_handle_debug_exception();
Bharat Bhushan8a0548f2014-07-14 14:45:38 +05301704 if (kvm_handle_debug(cpu, run)) {
1705 ret = EXCP_DEBUG;
1706 break;
1707 }
1708 /* re-enter, this exception was guest-internal */
1709 ret = 0;
1710 break;
1711
Aravinda Prasad9ac703a2020-01-31 00:14:19 +05301712#if defined(TARGET_PPC64)
1713 case KVM_EXIT_NMI:
1714 trace_kvm_handle_nmi_exception();
1715 ret = kvm_handle_nmi(cpu, run);
1716 break;
1717#endif
1718
Jan Kiszka73aaec42011-01-21 21:48:06 +01001719 default:
1720 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1721 ret = -1;
1722 break;
aurel32d76d1652008-12-16 10:43:58 +00001723 }
1724
Jan Kiszka4b8523e2015-06-18 18:47:23 +02001725 qemu_mutex_unlock_iothread();
aurel32d76d1652008-12-16 10:43:58 +00001726 return ret;
1727}
1728
Bharat Bhushan31f2cb82013-02-24 18:16:21 +00001729int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1730{
1731 CPUState *cs = CPU(cpu);
1732 uint32_t bits = tsr_bits;
1733 struct kvm_one_reg reg = {
1734 .id = KVM_REG_PPC_OR_TSR,
1735 .addr = (uintptr_t) &bits,
1736 };
1737
1738 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1739}
1740
1741int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1742{
1743
1744 CPUState *cs = CPU(cpu);
1745 uint32_t bits = tsr_bits;
1746 struct kvm_one_reg reg = {
1747 .id = KVM_REG_PPC_CLEAR_TSR,
1748 .addr = (uintptr_t) &bits,
1749 };
1750
1751 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1752}
1753
1754int kvmppc_set_tcr(PowerPCCPU *cpu)
1755{
1756 CPUState *cs = CPU(cpu);
1757 CPUPPCState *env = &cpu->env;
1758 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1759
1760 struct kvm_one_reg reg = {
1761 .id = KVM_REG_PPC_TCR,
1762 .addr = (uintptr_t) &tcr,
1763 };
1764
1765 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1766}
1767
1768int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1769{
1770 CPUState *cs = CPU(cpu);
Bharat Bhushan31f2cb82013-02-24 18:16:21 +00001771 int ret;
1772
1773 if (!kvm_enabled()) {
1774 return -1;
1775 }
1776
1777 if (!cap_ppc_watchdog) {
1778 printf("warning: KVM does not support watchdog");
1779 return -1;
1780 }
1781
Cornelia Huck48add812014-04-09 17:21:57 +02001782 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
Bharat Bhushan31f2cb82013-02-24 18:16:21 +00001783 if (ret < 0) {
1784 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1785 __func__, strerror(-ret));
1786 return ret;
1787 }
1788
1789 return ret;
1790}
1791
Alexander Grafdc333cd2010-02-09 17:37:05 +01001792static int read_cpuinfo(const char *field, char *value, int len)
1793{
1794 FILE *f;
1795 int ret = -1;
1796 int field_len = strlen(field);
1797 char line[512];
1798
1799 f = fopen("/proc/cpuinfo", "r");
1800 if (!f) {
1801 return -1;
1802 }
1803
1804 do {
Nikunj A Dadhaniaef951442014-07-09 16:08:37 +05301805 if (!fgets(line, sizeof(line), f)) {
Alexander Grafdc333cd2010-02-09 17:37:05 +01001806 break;
1807 }
1808 if (!strncmp(line, field, field_len)) {
Jim Meyeringae215062012-10-04 13:09:52 +02001809 pstrcpy(value, len, line);
Alexander Grafdc333cd2010-02-09 17:37:05 +01001810 ret = 0;
1811 break;
1812 }
David Gibsonc995e942019-03-21 21:47:25 +11001813 } while (*line);
Alexander Grafdc333cd2010-02-09 17:37:05 +01001814
1815 fclose(f);
1816
1817 return ret;
1818}
1819
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001820static uint32_t kvmppc_get_tbfreq_procfs(void)
Alexander Grafdc333cd2010-02-09 17:37:05 +01001821{
1822 char line[512];
1823 char *ns;
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001824 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1825 uint32_t tbfreq_procfs;
Alexander Grafdc333cd2010-02-09 17:37:05 +01001826
1827 if (read_cpuinfo("timebase", line, sizeof(line))) {
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001828 return tbfreq_fallback;
Alexander Grafdc333cd2010-02-09 17:37:05 +01001829 }
1830
David Gibsonc995e942019-03-21 21:47:25 +11001831 ns = strchr(line, ':');
1832 if (!ns) {
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001833 return tbfreq_fallback;
Alexander Grafdc333cd2010-02-09 17:37:05 +01001834 }
1835
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001836 tbfreq_procfs = atoi(++ns);
Alexander Grafdc333cd2010-02-09 17:37:05 +01001837
Greg Kurz9cbcfb52021-03-17 18:57:07 +01001838 /* 0 is certainly not acceptable by the guest, return fallback value */
1839 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1840}
1841
1842uint32_t kvmppc_get_tbfreq(void)
1843{
1844 static uint32_t cached_tbfreq;
1845
1846 if (!cached_tbfreq) {
1847 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1848 }
1849
1850 return cached_tbfreq;
Alexander Grafdc333cd2010-02-09 17:37:05 +01001851}
Gleb Natapov4513d922010-05-10 11:21:34 +03001852
Nikunj A Dadhaniaef951442014-07-09 16:08:37 +05301853bool kvmppc_get_host_serial(char **value)
1854{
1855 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1856 NULL);
1857}
1858
1859bool kvmppc_get_host_model(char **value)
1860{
1861 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1862}
1863
Alexander Grafeadaada2011-07-21 02:29:15 +02001864/* Try to find a device tree node for a CPU with clock-frequency property */
1865static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1866{
1867 struct dirent *dirp;
1868 DIR *dp;
1869
David Gibsonc995e942019-03-21 21:47:25 +11001870 dp = opendir(PROC_DEVTREE_CPU);
1871 if (!dp) {
Alexander Grafeadaada2011-07-21 02:29:15 +02001872 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1873 return -1;
1874 }
1875
1876 buf[0] = '\0';
1877 while ((dirp = readdir(dp)) != NULL) {
1878 FILE *f;
1879 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1880 dirp->d_name);
1881 f = fopen(buf, "r");
1882 if (f) {
1883 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1884 fclose(f);
1885 break;
1886 }
1887 buf[0] = '\0';
1888 }
1889 closedir(dp);
1890 if (buf[0] == '\0') {
1891 printf("Unknown host!\n");
1892 return -1;
1893 }
1894
1895 return 0;
1896}
1897
Sukadev Bhattiprolu7d94a302015-11-13 18:13:07 -08001898static uint64_t kvmppc_read_int_dt(const char *filename)
Alexander Grafeadaada2011-07-21 02:29:15 +02001899{
David Gibson9bc884b2011-10-10 18:31:00 +00001900 union {
1901 uint32_t v32;
1902 uint64_t v64;
1903 } u;
Alexander Grafeadaada2011-07-21 02:29:15 +02001904 FILE *f;
1905 int len;
1906
Sukadev Bhattiprolu7d94a302015-11-13 18:13:07 -08001907 f = fopen(filename, "rb");
Alexander Grafeadaada2011-07-21 02:29:15 +02001908 if (!f) {
1909 return -1;
1910 }
1911
David Gibson9bc884b2011-10-10 18:31:00 +00001912 len = fread(&u, 1, sizeof(u), f);
Alexander Grafeadaada2011-07-21 02:29:15 +02001913 fclose(f);
1914 switch (len) {
David Gibson9bc884b2011-10-10 18:31:00 +00001915 case 4:
1916 /* property is a 32-bit quantity */
1917 return be32_to_cpu(u.v32);
1918 case 8:
1919 return be64_to_cpu(u.v64);
Alexander Grafeadaada2011-07-21 02:29:15 +02001920 }
1921
1922 return 0;
1923}
1924
David Gibsonc995e942019-03-21 21:47:25 +11001925/*
1926 * Read a CPU node property from the host device tree that's a single
Sukadev Bhattiprolu7d94a302015-11-13 18:13:07 -08001927 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
David Gibsonc995e942019-03-21 21:47:25 +11001928 * (can't find or open the property, or doesn't understand the format)
1929 */
Sukadev Bhattiprolu7d94a302015-11-13 18:13:07 -08001930static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1931{
1932 char buf[PATH_MAX], *tmp;
1933 uint64_t val;
1934
1935 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1936 return -1;
1937 }
1938
1939 tmp = g_strdup_printf("%s/%s", buf, propname);
1940 val = kvmppc_read_int_dt(tmp);
1941 g_free(tmp);
1942
1943 return val;
1944}
1945
David Gibson9bc884b2011-10-10 18:31:00 +00001946uint64_t kvmppc_get_clockfreq(void)
1947{
1948 return kvmppc_read_int_cpu_dt("clock-frequency");
1949}
1950
Suraj Jitindar Singh7d050522019-03-01 13:43:16 +11001951static int kvmppc_get_dec_bits(void)
1952{
1953 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1954
1955 if (nr_bits > 0) {
1956 return nr_bits;
1957 }
1958 return 0;
1959}
1960
Stuart Yoder1a61a9a2013-01-03 12:37:02 +00001961static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
Richard Hendersondb70b312019-03-22 19:07:57 -07001962{
1963 CPUState *cs = env_cpu(env);
Alexander Graf45024f02010-08-03 15:22:42 +02001964
Alexander Graf6fd33a72014-07-14 19:17:35 +02001965 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
Stuart Yoder1a61a9a2013-01-03 12:37:02 +00001966 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1967 return 0;
1968 }
Alexander Graf45024f02010-08-03 15:22:42 +02001969
Stuart Yoder1a61a9a2013-01-03 12:37:02 +00001970 return 1;
1971}
1972
1973int kvmppc_get_hasidle(CPUPPCState *env)
1974{
1975 struct kvm_ppc_pvinfo pvinfo;
1976
1977 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1978 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1979 return 1;
1980 }
1981
1982 return 0;
1983}
1984
1985int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
1986{
David Gibsonc995e942019-03-21 21:47:25 +11001987 uint32_t *hc = (uint32_t *)buf;
Stuart Yoder1a61a9a2013-01-03 12:37:02 +00001988 struct kvm_ppc_pvinfo pvinfo;
1989
1990 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
1991 memcpy(buf, pvinfo.hcall, buf_len);
Alexander Graf45024f02010-08-03 15:22:42 +02001992 return 0;
1993 }
Alexander Graf45024f02010-08-03 15:22:42 +02001994
1995 /*
Alexander Grafd13fc322014-06-11 12:19:03 +02001996 * Fallback to always fail hypercalls regardless of endianness:
Alexander Graf45024f02010-08-03 15:22:42 +02001997 *
Alexander Grafd13fc322014-06-11 12:19:03 +02001998 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
Alexander Graf45024f02010-08-03 15:22:42 +02001999 * li r3, -1
Alexander Grafd13fc322014-06-11 12:19:03 +02002000 * b .+8 (becomes nop in wrong endian)
2001 * bswap32(li r3, -1)
Alexander Graf45024f02010-08-03 15:22:42 +02002002 */
2003
Alexander Grafd13fc322014-06-11 12:19:03 +02002004 hc[0] = cpu_to_be32(0x08000048);
2005 hc[1] = cpu_to_be32(0x3860ffff);
2006 hc[2] = cpu_to_be32(0x48000008);
2007 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
Alexander Graf45024f02010-08-03 15:22:42 +02002008
Alexey Kardashevskiy0ddbd052016-03-21 13:14:02 +11002009 return 1;
Alexander Graf45024f02010-08-03 15:22:42 +02002010}
2011
David Gibson026bfd82015-05-07 15:33:59 +10002012static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2013{
2014 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2015}
2016
2017void kvmppc_enable_logical_ci_hcalls(void)
2018{
2019 /*
2020 * FIXME: it would be nice if we could detect the cases where
2021 * we're using a device which requires the in kernel
2022 * implementation of these hcalls, but the kernel lacks them and
2023 * produce a warning.
2024 */
2025 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2026 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2027}
2028
Alexey Kardashevskiyef9971d2015-09-08 11:25:13 +10002029void kvmppc_enable_set_mode_hcall(void)
2030{
2031 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2032}
2033
Nathan Whitehorn5145ad42016-08-30 01:02:47 +00002034void kvmppc_enable_clear_ref_mod_hcalls(void)
2035{
2036 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2037 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2038}
2039
Suraj Jitindar Singh68f9f702019-03-06 17:06:08 +11002040void kvmppc_enable_h_page_init(void)
2041{
2042 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2043}
2044
Bharata B Rao82123b72021-07-06 16:54:40 +05302045void kvmppc_enable_h_rpt_invalidate(void)
2046{
2047 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2048}
2049
Andreas Färber1bc22652012-10-31 06:06:49 +01002050void kvmppc_set_papr(PowerPCCPU *cpu)
Alexander Graff61b4be2011-08-09 17:57:37 +02002051{
Andreas Färber1bc22652012-10-31 06:06:49 +01002052 CPUState *cs = CPU(cpu);
Alexander Graff61b4be2011-08-09 17:57:37 +02002053 int ret;
2054
David Gibsonda20aed2018-04-05 16:02:51 +10002055 if (!kvm_enabled()) {
2056 return;
2057 }
2058
Cornelia Huck48add812014-04-09 17:21:57 +02002059 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
Alexander Graff61b4be2011-08-09 17:57:37 +02002060 if (ret) {
Thomas Huth072ed5f2016-02-18 22:01:38 +01002061 error_report("This vCPU type or KVM version does not support PAPR");
2062 exit(1);
Alexander Graff61b4be2011-08-09 17:57:37 +02002063 }
David Gibson9b00ea42013-04-07 19:08:22 +00002064
David Gibsonc995e942019-03-21 21:47:25 +11002065 /*
2066 * Update the capability flag so we sync the right information
2067 * with kvm
2068 */
David Gibson9b00ea42013-04-07 19:08:22 +00002069 cap_papr = 1;
Alexander Graff61b4be2011-08-09 17:57:37 +02002070}
2071
David Gibsond6e166c2016-10-28 22:09:37 +11002072int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
Alexey Kardashevskiy6db5bb02014-05-23 12:26:58 +10002073{
David Gibsond6e166c2016-10-28 22:09:37 +11002074 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
Alexey Kardashevskiy6db5bb02014-05-23 12:26:58 +10002075}
2076
Alexander Graf5b95b8b2013-01-17 11:54:38 +01002077void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2078{
Alexander Graf5b95b8b2013-01-17 11:54:38 +01002079 CPUState *cs = CPU(cpu);
Alexander Graf5b95b8b2013-01-17 11:54:38 +01002080 int ret;
2081
Cornelia Huck48add812014-04-09 17:21:57 +02002082 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
Alexander Graf5b95b8b2013-01-17 11:54:38 +01002083 if (ret && mpic_proxy) {
Thomas Huth072ed5f2016-02-18 22:01:38 +01002084 error_report("This KVM version does not support EPR");
2085 exit(1);
Alexander Graf5b95b8b2013-01-17 11:54:38 +01002086 }
2087}
2088
Nicholas Pigginec010c02020-03-26 00:29:03 +10002089bool kvmppc_get_fwnmi(void)
2090{
2091 return cap_fwnmi;
2092}
2093
Laurent Vivieraef92d82020-07-24 10:35:33 +02002094int kvmppc_set_fwnmi(PowerPCCPU *cpu)
Aravinda Prasad9d953ce2020-01-31 00:14:18 +05302095{
Aravinda Prasad9d953ce2020-01-31 00:14:18 +05302096 CPUState *cs = CPU(cpu);
2097
2098 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2099}
2100
David Gibsone97c3632011-09-29 21:39:10 +00002101int kvmppc_smt_threads(void)
2102{
2103 return cap_ppc_smt ? cap_ppc_smt : 1;
2104}
2105
Sam Bobrofffa98fbf2017-08-18 15:50:22 +10002106int kvmppc_set_smt_threads(int smt)
2107{
2108 int ret;
2109
2110 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2111 if (!ret) {
2112 cap_ppc_smt = smt;
2113 }
2114 return ret;
2115}
2116
Vladimir Sementsov-Ogievskiy0c115682019-12-05 20:46:21 +03002117void kvmppc_error_append_smt_possible_hint(Error *const *errp)
Sam Bobrofffa98fbf2017-08-18 15:50:22 +10002118{
2119 int i;
2120 GString *g;
2121 char *s;
2122
2123 assert(kvm_enabled());
2124 if (cap_ppc_smt_possible) {
2125 g = g_string_new("Available VSMT modes:");
2126 for (i = 63; i >= 0; i--) {
2127 if ((1UL << i) & cap_ppc_smt_possible) {
2128 g_string_append_printf(g, " %lu", (1UL << i));
2129 }
2130 }
2131 s = g_string_free(g, false);
Markus Armbruster1a639fd2019-12-18 08:36:27 +01002132 error_append_hint(errp, "%s.\n", s);
Sam Bobrofffa98fbf2017-08-18 15:50:22 +10002133 g_free(s);
2134 } else {
Markus Armbruster1a639fd2019-12-18 08:36:27 +01002135 error_append_hint(errp,
Sam Bobrofffa98fbf2017-08-18 15:50:22 +10002136 "This KVM seems to be too old to support VSMT.\n");
2137 }
2138}
2139
2140
David Gibson7f763a52012-09-12 16:57:12 +00002141#ifdef TARGET_PPC64
David Gibson6a847372019-11-28 16:12:06 +11002142uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
David Gibson7f763a52012-09-12 16:57:12 +00002143{
David Gibsonf36951c2013-04-07 19:08:18 +00002144 struct kvm_ppc_smmu_info info;
2145 long rampagesize, best_page_shift;
2146 int i;
2147
David Gibsonc995e942019-03-21 21:47:25 +11002148 /*
2149 * Find the largest hardware supported page size that's less than
2150 * or equal to the (logical) backing page size of guest RAM
2151 */
Greg Kurzab256962018-06-29 11:48:32 +02002152 kvm_get_smmu_info(&info, &error_fatal);
David Hildenbrand905b7ee2019-04-17 13:31:43 +02002153 rampagesize = qemu_minrampagesize();
David Gibsonf36951c2013-04-07 19:08:18 +00002154 best_page_shift = 0;
2155
2156 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2157 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2158
2159 if (!sps->page_shift) {
2160 continue;
2161 }
2162
2163 if ((sps->page_shift > best_page_shift)
2164 && ((1UL << sps->page_shift) <= rampagesize)) {
2165 best_page_shift = sps->page_shift;
2166 }
2167 }
2168
David Gibson6a847372019-11-28 16:12:06 +11002169 return 1ULL << (best_page_shift + hash_shift - 7);
David Gibson7f763a52012-09-12 16:57:12 +00002170}
2171#endif
2172
Alexey Kardashevskiyda953242014-05-27 15:36:30 +10002173bool kvmppc_spapr_use_multitce(void)
2174{
2175 return cap_spapr_multitce;
2176}
2177
Alexey Kardashevskiy3dc410a2017-03-27 16:22:19 +11002178int kvmppc_spapr_enable_inkernel_multitce(void)
2179{
2180 int ret;
2181
2182 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2183 H_PUT_TCE_INDIRECT, 1);
2184 if (!ret) {
2185 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2186 H_STUFF_TCE, 1);
2187 }
2188
2189 return ret;
2190}
2191
Alexey Kardashevskiyd6ee2a72017-03-10 12:41:13 +11002192void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2193 uint64_t bus_offset, uint32_t nb_table,
2194 int *pfd, bool need_vfio)
David Gibson0f5cb292011-09-29 21:39:12 +00002195{
David Gibson0f5cb292011-09-29 21:39:12 +00002196 long len;
2197 int fd;
2198 void *table;
2199
David Gibsonc995e942019-03-21 21:47:25 +11002200 /*
2201 * Must set fd to -1 so we don't try to munmap when called for
David Gibsonb5aec392012-02-27 17:18:07 +00002202 * destroying the table, which the upper layers -will- do
2203 */
2204 *pfd = -1;
David Gibson6a81dd12015-09-30 13:42:55 +10002205 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
David Gibson0f5cb292011-09-29 21:39:12 +00002206 return NULL;
2207 }
2208
Alexey Kardashevskiyd6ee2a72017-03-10 12:41:13 +11002209 if (cap_spapr_tce_64) {
2210 struct kvm_create_spapr_tce_64 args = {
2211 .liobn = liobn,
2212 .page_shift = page_shift,
2213 .offset = bus_offset >> page_shift,
2214 .size = nb_table,
2215 .flags = 0
2216 };
2217 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2218 if (fd < 0) {
2219 fprintf(stderr,
2220 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2221 liobn);
2222 return NULL;
2223 }
2224 } else if (cap_spapr_tce) {
2225 uint64_t window_size = (uint64_t) nb_table << page_shift;
2226 struct kvm_create_spapr_tce args = {
2227 .liobn = liobn,
2228 .window_size = window_size,
2229 };
2230 if ((window_size != args.window_size) || bus_offset) {
2231 return NULL;
2232 }
2233 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2234 if (fd < 0) {
2235 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2236 liobn);
2237 return NULL;
2238 }
2239 } else {
David Gibson0f5cb292011-09-29 21:39:12 +00002240 return NULL;
2241 }
2242
Alexey Kardashevskiyd6ee2a72017-03-10 12:41:13 +11002243 len = nb_table * sizeof(uint64_t);
David Gibson0f5cb292011-09-29 21:39:12 +00002244 /* FIXME: round this up to page size */
2245
David Gibsonc995e942019-03-21 21:47:25 +11002246 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
David Gibson0f5cb292011-09-29 21:39:12 +00002247 if (table == MAP_FAILED) {
David Gibsonb5aec392012-02-27 17:18:07 +00002248 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2249 liobn);
David Gibson0f5cb292011-09-29 21:39:12 +00002250 close(fd);
2251 return NULL;
2252 }
2253
2254 *pfd = fd;
2255 return table;
2256}
2257
Alexey Kardashevskiy523e7b82014-05-27 15:36:35 +10002258int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
David Gibson0f5cb292011-09-29 21:39:12 +00002259{
2260 long len;
2261
2262 if (fd < 0) {
2263 return -1;
2264 }
2265
Alexey Kardashevskiy523e7b82014-05-27 15:36:35 +10002266 len = nb_table * sizeof(uint64_t);
David Gibson0f5cb292011-09-29 21:39:12 +00002267 if ((munmap(table, len) < 0) ||
2268 (close(fd) < 0)) {
David Gibsonb5aec392012-02-27 17:18:07 +00002269 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2270 strerror(errno));
David Gibson0f5cb292011-09-29 21:39:12 +00002271 /* Leak the table */
2272 }
2273
2274 return 0;
2275}
2276
David Gibson7f763a52012-09-12 16:57:12 +00002277int kvmppc_reset_htab(int shift_hint)
2278{
2279 uint32_t shift = shift_hint;
2280
David Gibsonace9a2c2012-09-19 21:08:42 +00002281 if (!kvm_enabled()) {
2282 /* Full emulation, tell caller to allocate htab itself */
2283 return 0;
2284 }
Greg Kurz6977afd2017-09-14 21:25:43 +02002285 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
David Gibson7f763a52012-09-12 16:57:12 +00002286 int ret;
2287 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
David Gibsonace9a2c2012-09-19 21:08:42 +00002288 if (ret == -ENOTTY) {
David Gibsonc995e942019-03-21 21:47:25 +11002289 /*
2290 * At least some versions of PR KVM advertise the
David Gibsonace9a2c2012-09-19 21:08:42 +00002291 * capability, but don't implement the ioctl(). Oops.
2292 * Return 0 so that we allocate the htab in qemu, as is
David Gibsonc995e942019-03-21 21:47:25 +11002293 * correct for PR.
2294 */
David Gibsonace9a2c2012-09-19 21:08:42 +00002295 return 0;
2296 } else if (ret < 0) {
David Gibson7f763a52012-09-12 16:57:12 +00002297 return ret;
2298 }
2299 return shift;
2300 }
2301
David Gibsonc995e942019-03-21 21:47:25 +11002302 /*
2303 * We have a kernel that predates the htab reset calls. For PR
David Gibsonace9a2c2012-09-19 21:08:42 +00002304 * KVM, we need to allocate the htab ourselves, for an HV KVM of
David Gibsonc995e942019-03-21 21:47:25 +11002305 * this era, it has allocated a 16MB fixed size hash table
2306 * already.
2307 */
Thomas Huth96c9cff2016-09-29 12:48:06 +02002308 if (kvmppc_is_pr(kvm_state)) {
David Gibsonace9a2c2012-09-19 21:08:42 +00002309 /* PR - tell caller to allocate htab */
2310 return 0;
2311 } else {
2312 /* HV - assume 16MB kernel allocated htab */
2313 return 24;
2314 }
David Gibson7f763a52012-09-12 16:57:12 +00002315}
2316
David Gibsona1e98582011-10-12 22:40:32 +00002317static inline uint32_t mfpvr(void)
2318{
2319 uint32_t pvr;
2320
2321 asm ("mfpvr %0"
2322 : "=r"(pvr));
2323 return pvr;
2324}
2325
David Gibsona7342582011-10-17 18:15:41 +00002326static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2327{
2328 if (on) {
2329 *word |= flags;
2330 } else {
2331 *word &= ~flags;
2332 }
2333}
2334
Andreas Färber2985b862013-01-06 08:31:30 +00002335static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2336{
2337 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
David Gibson0cbad812013-04-07 19:08:19 +00002338 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2339 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
David Gibsona1e98582011-10-12 22:40:32 +00002340
Andreas Färbercfe34f42013-02-17 23:16:41 +00002341 /* Now fix up the class with information we can query from the host */
Alexey Kardashevskiy3bc9ccc2013-09-27 18:05:03 +10002342 pcc->pvr = mfpvr();
David Gibsona7342582011-10-17 18:15:41 +00002343
David Gibson3f2ca482017-12-11 17:41:34 +11002344 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2345 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2346 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2347 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2348 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2349 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
David Gibson0cbad812013-04-07 19:08:19 +00002350
2351 if (dcache_size != -1) {
2352 pcc->l1_dcache_size = dcache_size;
2353 }
2354
2355 if (icache_size != -1) {
2356 pcc->l1_icache_size = icache_size;
2357 }
Sam Bobroffc64abd12017-03-20 10:46:43 +11002358
2359#if defined(TARGET_PPC64)
2360 pcc->radix_page_info = kvm_get_radix_page_info();
David Gibson5f3066d2017-05-10 11:19:16 +10002361
2362 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2363 /*
2364 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2365 * compliant. More importantly, advertising ISA 3.00
2366 * architected mode may prevent guests from activating
2367 * necessary DD1 workarounds.
2368 */
2369 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2370 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2371 }
Sam Bobroffc64abd12017-03-20 10:46:43 +11002372#endif /* defined(TARGET_PPC64) */
David Gibsona1e98582011-10-12 22:40:32 +00002373}
2374
Stuart Yoder3b961122013-03-30 06:40:49 +00002375bool kvmppc_has_cap_epr(void)
2376{
2377 return cap_epr;
2378}
2379
Alexander Graf87a91de2014-06-04 12:14:08 +02002380bool kvmppc_has_cap_fixup_hcalls(void)
2381{
2382 return cap_fixup_hcalls;
2383}
2384
Thomas Huthbac3bf22016-09-28 13:16:30 +02002385bool kvmppc_has_cap_htm(void)
2386{
2387 return cap_htm;
2388}
2389
Sam Bobroffcf1c4cc2017-03-20 10:46:44 +11002390bool kvmppc_has_cap_mmu_radix(void)
2391{
2392 return cap_mmu_radix;
2393}
2394
2395bool kvmppc_has_cap_mmu_hash_v3(void)
2396{
2397 return cap_mmu_hash_v3;
2398}
2399
Suraj Jitindar Singh072f4162018-06-12 15:16:29 +10002400static bool kvmppc_power8_host(void)
2401{
2402 bool ret = false;
2403#ifdef TARGET_PPC64
2404 {
2405 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2406 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2407 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2408 (base_pvr == CPU_POWERPC_POWER8_BASE);
2409 }
2410#endif /* TARGET_PPC64 */
2411 return ret;
2412}
2413
Suraj Jitindar Singh8fea7042018-05-11 16:25:07 +10002414static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2415{
Suraj Jitindar Singh072f4162018-06-12 15:16:29 +10002416 bool l1d_thread_priv_req = !kvmppc_power8_host();
2417
Suraj Jitindar Singh8fea7042018-05-11 16:25:07 +10002418 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2419 return 2;
Suraj Jitindar Singh072f4162018-06-12 15:16:29 +10002420 } else if ((!l1d_thread_priv_req ||
2421 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
Suraj Jitindar Singh8fea7042018-05-11 16:25:07 +10002422 (c.character & c.character_mask
2423 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2424 return 1;
2425 }
2426
2427 return 0;
2428}
2429
2430static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2431{
2432 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2433 return 2;
2434 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2435 return 1;
2436 }
2437
2438 return 0;
2439}
2440
2441static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2442{
Suraj Jitindar Singh399b2892019-03-01 14:19:11 +11002443 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2444 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2445 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2446 return SPAPR_CAP_FIXED_NA;
2447 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2448 return SPAPR_CAP_WORKAROUND;
2449 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
Suraj Jitindar Singh8fea7042018-05-11 16:25:07 +10002450 return SPAPR_CAP_FIXED_CCD;
2451 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2452 return SPAPR_CAP_FIXED_IBS;
2453 }
2454
2455 return 0;
2456}
2457
Suraj Jitindar Singh8ff43ee2019-03-01 14:19:12 +11002458static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2459{
2460 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2461 return 1;
2462 }
2463 return 0;
2464}
2465
Cédric Le Goater38afd772019-05-13 10:42:33 +02002466bool kvmppc_has_cap_xive(void)
2467{
2468 return cap_xive;
2469}
2470
Suraj Jitindar Singh8acc2ae2018-01-19 15:59:59 +11002471static void kvmppc_get_cpu_characteristics(KVMState *s)
2472{
2473 struct kvm_ppc_cpu_char c;
2474 int ret;
2475
2476 /* Assume broken */
2477 cap_ppc_safe_cache = 0;
2478 cap_ppc_safe_bounds_check = 0;
2479 cap_ppc_safe_indirect_branch = 0;
2480
2481 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2482 if (!ret) {
2483 return;
2484 }
2485 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2486 if (ret < 0) {
2487 return;
2488 }
Suraj Jitindar Singh8fea7042018-05-11 16:25:07 +10002489
2490 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2491 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2492 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
Suraj Jitindar Singh8ff43ee2019-03-01 14:19:12 +11002493 cap_ppc_count_cache_flush_assist =
2494 parse_cap_ppc_count_cache_flush_assist(c);
Suraj Jitindar Singh8acc2ae2018-01-19 15:59:59 +11002495}
2496
2497int kvmppc_get_cap_safe_cache(void)
2498{
2499 return cap_ppc_safe_cache;
2500}
2501
2502int kvmppc_get_cap_safe_bounds_check(void)
2503{
2504 return cap_ppc_safe_bounds_check;
2505}
2506
2507int kvmppc_get_cap_safe_indirect_branch(void)
2508{
2509 return cap_ppc_safe_indirect_branch;
2510}
2511
Suraj Jitindar Singh8ff43ee2019-03-01 14:19:12 +11002512int kvmppc_get_cap_count_cache_flush_assist(void)
2513{
2514 return cap_ppc_count_cache_flush_assist;
2515}
2516
Suraj Jitindar Singhb9a477b2018-10-08 14:25:39 +11002517bool kvmppc_has_cap_nested_kvm_hv(void)
2518{
2519 return !!cap_ppc_nested_kvm_hv;
2520}
2521
2522int kvmppc_set_cap_nested_kvm_hv(int enable)
2523{
2524 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2525}
2526
Alexey Kardashevskiy9ded7802018-02-06 11:08:24 -07002527bool kvmppc_has_cap_spapr_vfio(void)
2528{
2529 return cap_spapr_vfio;
2530}
2531
Suraj Jitindar Singh7d050522019-03-01 13:43:16 +11002532int kvmppc_get_cap_large_decr(void)
2533{
2534 return cap_large_decr;
2535}
2536
2537int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2538{
2539 CPUState *cs = CPU(cpu);
2540 uint64_t lpcr;
2541
2542 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2543 /* Do we need to modify the LPCR? */
2544 if (!!(lpcr & LPCR_LD) != !!enable) {
2545 if (enable) {
2546 lpcr |= LPCR_LD;
2547 } else {
2548 lpcr &= ~LPCR_LD;
2549 }
2550 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2551 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2552
2553 if (!!(lpcr & LPCR_LD) != !!enable) {
2554 return -1;
2555 }
2556 }
2557
2558 return 0;
2559}
2560
Bharata B Rao82123b72021-07-06 16:54:40 +05302561int kvmppc_has_cap_rpt_invalidate(void)
2562{
2563 return cap_rpt_invalidate;
2564}
2565
Thomas Huth52b25192016-06-07 17:39:38 +02002566PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2567{
2568 uint32_t host_pvr = mfpvr();
2569 PowerPCCPUClass *pvr_pcc;
2570
2571 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2572 if (pvr_pcc == NULL) {
2573 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2574 }
2575
2576 return pvr_pcc;
2577}
2578
David Gibson165dc3e2019-10-30 17:20:35 +01002579static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2580{
2581 MachineClass *mc = MACHINE_CLASS(oc);
2582
2583 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2584}
2585
2586static int kvm_ppc_register_host_cpu_type(void)
Andreas Färber5ba45762013-02-23 11:22:12 +00002587{
2588 TypeInfo type_info = {
2589 .name = TYPE_HOST_POWERPC_CPU,
Andreas Färber5ba45762013-02-23 11:22:12 +00002590 .class_init = kvmppc_host_cpu_class_init,
2591 };
Andreas Färber5ba45762013-02-23 11:22:12 +00002592 PowerPCCPUClass *pvr_pcc;
Greg Kurz92e926e2017-07-05 10:49:52 +02002593 ObjectClass *oc;
Alexey Kardashevskiy5b79b1c2014-04-12 03:34:25 +10002594 DeviceClass *dc;
Thomas Huth715d4b92017-01-31 14:11:58 +01002595 int i;
Andreas Färber5ba45762013-02-23 11:22:12 +00002596
Thomas Huth52b25192016-06-07 17:39:38 +02002597 pvr_pcc = kvm_ppc_get_host_cpu_class();
Alexey Kardashevskiy3bc9ccc2013-09-27 18:05:03 +10002598 if (pvr_pcc == NULL) {
Andreas Färber5ba45762013-02-23 11:22:12 +00002599 return -1;
2600 }
2601 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2602 type_register(&type_info);
David Gibson165dc3e2019-10-30 17:20:35 +01002603 /* override TCG default cpu type with 'host' cpu model */
2604 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2605 false, NULL);
Alexey Kardashevskiy5b79b1c2014-04-12 03:34:25 +10002606
Greg Kurz92e926e2017-07-05 10:49:52 +02002607 oc = object_class_by_name(type_info.name);
2608 g_assert(oc);
2609
Thomas Huth715d4b92017-01-31 14:11:58 +01002610 /*
2611 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2612 * we want "POWER8" to be a "family" alias that points to the current
2613 * host CPU type, too)
2614 */
2615 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2616 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
Igor Mammedovc5354f52017-08-30 15:24:30 +02002617 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
Thomas Huth715d4b92017-01-31 14:11:58 +01002618 char *suffix;
2619
2620 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
Igor Mammedovc9137062017-08-30 15:24:29 +02002621 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
Thomas Huth715d4b92017-01-31 14:11:58 +01002622 if (suffix) {
2623 *suffix = 0;
2624 }
Thomas Huth715d4b92017-01-31 14:11:58 +01002625 break;
2626 }
2627 }
2628
Andreas Färber5ba45762013-02-23 11:22:12 +00002629 return 0;
2630}
2631
David Gibsonfeaa64c2013-09-26 16:18:35 +10002632int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2633{
2634 struct kvm_rtas_token_args args = {
2635 .token = token,
2636 };
2637
2638 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2639 return -ENOENT;
2640 }
2641
Cédric Le Goater7701aee2019-06-15 10:12:52 +02002642 strncpy(args.name, function, sizeof(args.name) - 1);
David Gibsonfeaa64c2013-09-26 16:18:35 +10002643
2644 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2645}
David Gibson12b11432012-04-04 15:02:05 +10002646
Greg Kurz14b0d742017-09-15 15:16:20 +02002647int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002648{
2649 struct kvm_get_htab_fd s = {
2650 .flags = write ? KVM_GET_HTAB_WRITE : 0,
Greg Kurz14b0d742017-09-15 15:16:20 +02002651 .start_index = index,
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002652 };
Greg Kurz82be8e72017-09-15 15:16:10 +02002653 int ret;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002654
2655 if (!cap_htab_fd) {
Greg Kurz14b0d742017-09-15 15:16:20 +02002656 error_setg(errp, "KVM version doesn't support %s the HPT",
2657 write ? "writing" : "reading");
Greg Kurz82be8e72017-09-15 15:16:10 +02002658 return -ENOTSUP;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002659 }
2660
Greg Kurz82be8e72017-09-15 15:16:10 +02002661 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2662 if (ret < 0) {
Greg Kurz14b0d742017-09-15 15:16:20 +02002663 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2664 write ? "writing" : "reading", write ? "to" : "from",
2665 strerror(errno));
Greg Kurz82be8e72017-09-15 15:16:10 +02002666 return -errno;
2667 }
2668
2669 return ret;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002670}
2671
2672int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2673{
Alex Blighbc72ad62013-08-21 16:03:08 +01002674 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002675 uint8_t buf[bufsize];
2676 ssize_t rc;
2677
2678 do {
2679 rc = read(fd, buf, bufsize);
2680 if (rc < 0) {
2681 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2682 strerror(errno));
2683 return rc;
2684 } else if (rc) {
Cédric Le Goatere094c4c2014-11-03 16:14:50 +01002685 uint8_t *buffer = buf;
2686 ssize_t n = rc;
2687 while (n) {
2688 struct kvm_get_htab_header *head =
2689 (struct kvm_get_htab_header *) buffer;
2690 size_t chunksize = sizeof(*head) +
2691 HASH_PTE_SIZE_64 * head->n_valid;
2692
2693 qemu_put_be32(f, head->index);
2694 qemu_put_be16(f, head->n_valid);
2695 qemu_put_be16(f, head->n_invalid);
2696 qemu_put_buffer(f, (void *)(head + 1),
2697 HASH_PTE_SIZE_64 * head->n_valid);
2698
2699 buffer += chunksize;
2700 n -= chunksize;
2701 }
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002702 }
2703 } while ((rc != 0)
David Gibsonc995e942019-03-21 21:47:25 +11002704 && ((max_ns < 0) ||
2705 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002706
2707 return (rc == 0) ? 1 : 0;
2708}
2709
2710int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
Greg Kurz0a06e4d2020-10-26 13:40:47 +01002711 uint16_t n_valid, uint16_t n_invalid, Error **errp)
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002712{
2713 struct kvm_get_htab_header *buf;
David Gibsonc995e942019-03-21 21:47:25 +11002714 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002715 ssize_t rc;
2716
2717 buf = alloca(chunksize);
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002718 buf->index = index;
2719 buf->n_valid = n_valid;
2720 buf->n_invalid = n_invalid;
2721
David Gibsonc995e942019-03-21 21:47:25 +11002722 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002723
2724 rc = write(fd, buf, chunksize);
2725 if (rc < 0) {
Greg Kurz0a06e4d2020-10-26 13:40:47 +01002726 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2727 return -errno;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002728 }
2729 if (rc != chunksize) {
2730 /* We should never get a short write on a single chunk */
Greg Kurz0a06e4d2020-10-26 13:40:47 +01002731 error_setg(errp, "Short write while restoring the KVM hash table");
2732 return -ENOSPC;
Alexey Kardashevskiye68cb8b2013-07-18 14:33:03 -05002733 }
2734 return 0;
2735}
2736
Andreas Färber20d695a2012-10-31 06:57:49 +01002737bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
Gleb Natapov4513d922010-05-10 11:21:34 +03002738{
2739 return true;
2740}
Jan Kiszkaa1b87fe2011-02-01 22:15:51 +01002741
Scott Wood82169662013-06-12 17:26:54 +10002742void kvm_arch_init_irq_routing(KVMState *s)
2743{
2744}
Greg Kurzc65f9a02013-12-11 14:15:34 +01002745
David Gibson1ad9f0a2017-02-27 15:34:19 +11002746void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002747{
David Gibson1ad9f0a2017-02-27 15:34:19 +11002748 int fd, rc;
2749 int i;
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002750
Greg Kurz14b0d742017-09-15 15:16:20 +02002751 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002752
David Gibson1ad9f0a2017-02-27 15:34:19 +11002753 i = 0;
2754 while (i < n) {
2755 struct kvm_get_htab_header *hdr;
2756 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2757 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
2758
2759 rc = read(fd, buf, sizeof(buf));
2760 if (rc < 0) {
2761 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2762 }
2763
2764 hdr = (struct kvm_get_htab_header *)buf;
2765 while ((i < n) && ((char *)hdr < (buf + rc))) {
Alexey Kardashevskiya36593e2018-01-11 15:08:32 +11002766 int invalid = hdr->n_invalid, valid = hdr->n_valid;
David Gibson1ad9f0a2017-02-27 15:34:19 +11002767
2768 if (hdr->index != (ptex + i)) {
2769 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2770 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2771 }
2772
Alexey Kardashevskiya36593e2018-01-11 15:08:32 +11002773 if (n - i < valid) {
2774 valid = n - i;
2775 }
2776 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2777 i += valid;
David Gibson1ad9f0a2017-02-27 15:34:19 +11002778
2779 if ((n - i) < invalid) {
2780 invalid = n - i;
2781 }
2782 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
Alexey Kardashevskiya36593e2018-01-11 15:08:32 +11002783 i += invalid;
David Gibson1ad9f0a2017-02-27 15:34:19 +11002784
2785 hdr = (struct kvm_get_htab_header *)
2786 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2787 }
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002788 }
2789
David Gibson1ad9f0a2017-02-27 15:34:19 +11002790 close(fd);
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002791}
2792
David Gibson1ad9f0a2017-02-27 15:34:19 +11002793void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
Aneesh Kumar K.V7c43bca2014-02-20 18:52:24 +01002794{
David Gibson1ad9f0a2017-02-27 15:34:19 +11002795 int fd, rc;
David Gibson1ad9f0a2017-02-27 15:34:19 +11002796 struct {
2797 struct kvm_get_htab_header hdr;
2798 uint64_t pte0;
2799 uint64_t pte1;
2800 } buf;
Aneesh Kumar K.Vc1385932014-02-20 18:52:38 +01002801
Greg Kurz14b0d742017-09-15 15:16:20 +02002802 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
Aneesh Kumar K.Vc1385932014-02-20 18:52:38 +01002803
David Gibson1ad9f0a2017-02-27 15:34:19 +11002804 buf.hdr.n_valid = 1;
2805 buf.hdr.n_invalid = 0;
2806 buf.hdr.index = ptex;
2807 buf.pte0 = cpu_to_be64(pte0);
2808 buf.pte1 = cpu_to_be64(pte1);
2809
2810 rc = write(fd, &buf, sizeof(buf));
2811 if (rc != sizeof(buf)) {
2812 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
Aneesh Kumar K.Vc1385932014-02-20 18:52:38 +01002813 }
David Gibson1ad9f0a2017-02-27 15:34:19 +11002814 close(fd);
Aneesh Kumar K.Vc1385932014-02-20 18:52:38 +01002815}
Frank Blaschka9e03a042015-01-09 09:04:40 +01002816
2817int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
Pavel Fedindc9f06c2015-10-15 16:44:52 +03002818 uint64_t address, uint32_t data, PCIDevice *dev)
Frank Blaschka9e03a042015-01-09 09:04:40 +01002819{
2820 return 0;
2821}
Eric Auger1850b6b2015-06-02 14:56:23 +01002822
Peter Xu38d87492016-07-14 13:56:31 +08002823int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2824 int vector, PCIDevice *dev)
2825{
2826 return 0;
2827}
2828
2829int kvm_arch_release_virq_post(int virq)
2830{
2831 return 0;
2832}
2833
Eric Auger1850b6b2015-06-02 14:56:23 +01002834int kvm_arch_msi_data_to_gsi(uint32_t data)
2835{
2836 return data & 0xffff;
2837}
Thomas Huth4d9392b2015-09-17 10:49:41 +02002838
Aravinda Prasad9ac703a2020-01-31 00:14:19 +05302839#if defined(TARGET_PPC64)
2840int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2841{
Ganesh Goudar211a7782020-04-08 22:39:44 +05302842 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
Aravinda Prasad81fe70e2020-01-31 00:14:20 +05302843
Aravinda Prasad9ac703a2020-01-31 00:14:19 +05302844 cpu_synchronize_state(CPU(cpu));
2845
Ganesh Goudar211a7782020-04-08 22:39:44 +05302846 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
Aravinda Prasad9ac703a2020-01-31 00:14:19 +05302847
2848 return 0;
2849}
2850#endif
2851
Thomas Huth4d9392b2015-09-17 10:49:41 +02002852int kvmppc_enable_hwrng(void)
2853{
2854 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2855 return -1;
2856 }
2857
2858 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2859}
David Gibson30f4b052017-05-12 15:46:11 +10002860
2861void kvmppc_check_papr_resize_hpt(Error **errp)
2862{
2863 if (!kvm_enabled()) {
David Gibsonb55d2952017-07-12 17:56:55 +10002864 return; /* No KVM, we're good */
2865 }
2866
2867 if (cap_resize_hpt) {
2868 return; /* Kernel has explicit support, we're good */
2869 }
2870
2871 /* Otherwise fallback on looking for PR KVM */
2872 if (kvmppc_is_pr(kvm_state)) {
David Gibson30f4b052017-05-12 15:46:11 +10002873 return;
2874 }
2875
David Gibson30f4b052017-05-12 15:46:11 +10002876 error_setg(errp,
2877 "Hash page table resizing not available with this KVM version");
2878}
David Gibsonb55d2952017-07-12 17:56:55 +10002879
2880int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2881{
2882 CPUState *cs = CPU(cpu);
2883 struct kvm_ppc_resize_hpt rhpt = {
2884 .flags = flags,
2885 .shift = shift,
2886 };
2887
2888 if (!cap_resize_hpt) {
2889 return -ENOSYS;
2890 }
2891
2892 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2893}
2894
2895int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2896{
2897 CPUState *cs = CPU(cpu);
2898 struct kvm_ppc_resize_hpt rhpt = {
2899 .flags = flags,
2900 .shift = shift,
2901 };
2902
2903 if (!cap_resize_hpt) {
2904 return -ENOSYS;
2905 }
2906
2907 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2908}
2909
Daniel Henrique Barbozac363a372017-08-09 17:43:46 -03002910/*
2911 * This is a helper function to detect a post migration scenario
2912 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2913 * the guest kernel can't handle a PVR value other than the actual host
2914 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2915 *
2916 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2917 * (so, we're HV), return true. The workaround itself is done in
2918 * cpu_post_load.
2919 *
2920 * The order here is important: we'll only check for KVM PR as a
2921 * fallback if the guest kernel can't handle the situation itself.
2922 * We need to avoid as much as possible querying the running KVM type
2923 * in QEMU level.
2924 */
2925bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2926{
2927 CPUState *cs = CPU(cpu);
2928
2929 if (!kvm_enabled()) {
2930 return false;
2931 }
2932
2933 if (cap_ppc_pvr_compat) {
2934 return false;
2935 }
2936
2937 return !kvmppc_is_pr(cs->kvm_state);
2938}
Nikunj A Dadhaniaa84f7172018-09-04 14:54:18 +05302939
2940void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2941{
2942 CPUState *cs = CPU(cpu);
2943
2944 if (kvm_enabled()) {
2945 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2946 }
2947}
Greg Kurz97232952019-06-14 13:09:17 +02002948
2949void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2950{
2951 CPUState *cs = CPU(cpu);
2952
2953 if (kvm_enabled()) {
2954 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2955 }
2956}
Tom Lendacky92a51992021-01-26 11:36:47 -06002957
2958bool kvm_arch_cpu_check_are_resettable(void)
2959{
2960 return true;
2961}