bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * i386 micro operations (templates for various register related |
| 3 | * operations) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4 | * |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5 | * Copyright (c) 2003 Fabrice Bellard |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
| 21 | void OPPROTO glue(op_movl_A0,REGNAME)(void) |
| 22 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 23 | A0 = (uint32_t)REG; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 24 | } |
| 25 | |
| 26 | void OPPROTO glue(op_addl_A0,REGNAME)(void) |
| 27 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 28 | A0 = (uint32_t)(A0 + REG); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 29 | } |
| 30 | |
| 31 | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s1)(void) |
| 32 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 33 | A0 = (uint32_t)(A0 + (REG << 1)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s2)(void) |
| 37 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 38 | A0 = (uint32_t)(A0 + (REG << 2)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 39 | } |
| 40 | |
| 41 | void OPPROTO glue(glue(op_addl_A0,REGNAME),_s3)(void) |
| 42 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 43 | A0 = (uint32_t)(A0 + (REG << 3)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 44 | } |
| 45 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 46 | #ifdef TARGET_X86_64 |
| 47 | void OPPROTO glue(op_movq_A0,REGNAME)(void) |
| 48 | { |
| 49 | A0 = REG; |
| 50 | } |
| 51 | |
| 52 | void OPPROTO glue(op_addq_A0,REGNAME)(void) |
| 53 | { |
| 54 | A0 = (A0 + REG); |
| 55 | } |
| 56 | |
| 57 | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s1)(void) |
| 58 | { |
| 59 | A0 = (A0 + (REG << 1)); |
| 60 | } |
| 61 | |
| 62 | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s2)(void) |
| 63 | { |
| 64 | A0 = (A0 + (REG << 2)); |
| 65 | } |
| 66 | |
| 67 | void OPPROTO glue(glue(op_addq_A0,REGNAME),_s3)(void) |
| 68 | { |
| 69 | A0 = (A0 + (REG << 3)); |
| 70 | } |
| 71 | #endif |
| 72 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 73 | void OPPROTO glue(op_movl_T0,REGNAME)(void) |
| 74 | { |
| 75 | T0 = REG; |
| 76 | } |
| 77 | |
| 78 | void OPPROTO glue(op_movl_T1,REGNAME)(void) |
| 79 | { |
| 80 | T1 = REG; |
| 81 | } |
| 82 | |
| 83 | void OPPROTO glue(op_movh_T0,REGNAME)(void) |
| 84 | { |
| 85 | T0 = REG >> 8; |
| 86 | } |
| 87 | |
| 88 | void OPPROTO glue(op_movh_T1,REGNAME)(void) |
| 89 | { |
| 90 | T1 = REG >> 8; |
| 91 | } |
| 92 | |
| 93 | void OPPROTO glue(glue(op_movl,REGNAME),_T0)(void) |
| 94 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 95 | REG = (uint32_t)T0; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | void OPPROTO glue(glue(op_movl,REGNAME),_T1)(void) |
| 99 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 100 | REG = (uint32_t)T1; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | void OPPROTO glue(glue(op_movl,REGNAME),_A0)(void) |
| 104 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 105 | REG = (uint32_t)A0; |
| 106 | } |
| 107 | |
| 108 | #ifdef TARGET_X86_64 |
| 109 | void OPPROTO glue(glue(op_movq,REGNAME),_T0)(void) |
| 110 | { |
| 111 | REG = T0; |
| 112 | } |
| 113 | |
| 114 | void OPPROTO glue(glue(op_movq,REGNAME),_T1)(void) |
| 115 | { |
| 116 | REG = T1; |
| 117 | } |
| 118 | |
| 119 | void OPPROTO glue(glue(op_movq,REGNAME),_A0)(void) |
| 120 | { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 121 | REG = A0; |
| 122 | } |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 123 | #endif |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 124 | |
| 125 | /* mov T1 to REG if T0 is true */ |
| 126 | void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void) |
| 127 | { |
| 128 | if (T0) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 129 | REG = (REG & ~0xffff) | (T1 & 0xffff); |
bellard | 128b346 | 2003-10-30 01:05:49 +0000 | [diff] [blame] | 130 | FORCE_RET(); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void) |
| 134 | { |
| 135 | if (T0) |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 136 | REG = (uint32_t)T1; |
| 137 | FORCE_RET(); |
| 138 | } |
| 139 | |
| 140 | #ifdef TARGET_X86_64 |
| 141 | void OPPROTO glue(glue(op_cmovq,REGNAME),_T1_T0)(void) |
| 142 | { |
| 143 | if (T0) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 144 | REG = T1; |
bellard | 128b346 | 2003-10-30 01:05:49 +0000 | [diff] [blame] | 145 | FORCE_RET(); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 146 | } |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 147 | #endif |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 148 | |
| 149 | /* NOTE: T0 high order bits are ignored */ |
| 150 | void OPPROTO glue(glue(op_movw,REGNAME),_T0)(void) |
| 151 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 152 | REG = (REG & ~0xffff) | (T0 & 0xffff); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | /* NOTE: T0 high order bits are ignored */ |
| 156 | void OPPROTO glue(glue(op_movw,REGNAME),_T1)(void) |
| 157 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 158 | REG = (REG & ~0xffff) | (T1 & 0xffff); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | /* NOTE: A0 high order bits are ignored */ |
| 162 | void OPPROTO glue(glue(op_movw,REGNAME),_A0)(void) |
| 163 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 164 | REG = (REG & ~0xffff) | (A0 & 0xffff); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | /* NOTE: T0 high order bits are ignored */ |
| 168 | void OPPROTO glue(glue(op_movb,REGNAME),_T0)(void) |
| 169 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 170 | REG = (REG & ~0xff) | (T0 & 0xff); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | /* NOTE: T0 high order bits are ignored */ |
| 174 | void OPPROTO glue(glue(op_movh,REGNAME),_T0)(void) |
| 175 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 176 | REG = (REG & ~0xff00) | ((T0 & 0xff) << 8); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | /* NOTE: T1 high order bits are ignored */ |
| 180 | void OPPROTO glue(glue(op_movb,REGNAME),_T1)(void) |
| 181 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 182 | REG = (REG & ~0xff) | (T1 & 0xff); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | /* NOTE: T1 high order bits are ignored */ |
| 186 | void OPPROTO glue(glue(op_movh,REGNAME),_T1)(void) |
| 187 | { |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 188 | REG = (REG & ~0xff00) | ((T1 & 0xff) << 8); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 189 | } |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 190 | |