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Andrew Jeffery43e33462016-03-16 17:06:00 +00001/*
Cédric Le Goaterff906062016-09-22 18:13:05 +01002 * ASPEED SoC family
Andrew Jeffery43e33462016-03-16 17:06:00 +00003 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13#include "qemu/osdep.h"
Cédric Le Goater346160c2022-06-30 09:21:13 +020014#include "qemu/units.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010015#include "qapi/error.h"
Philippe Mathieu-Daudéc7c3c9f2018-02-15 18:29:36 +000016#include "hw/misc/unimp.h"
Cédric Le Goater00442402016-09-22 18:13:05 +010017#include "hw/arm/aspeed_soc.h"
Bernhard Beschow7e6b5492024-09-05 09:38:32 +020018#include "hw/char/serial-mm.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020019#include "qemu/module.h"
Cédric Le Goaterece09be2019-07-01 17:26:16 +010020#include "qemu/error-report.h"
Cédric Le Goater16020012016-06-06 16:59:29 +010021#include "hw/i2c/aspeed_i2c.h"
Cédric Le Goaterea337c62017-04-14 10:35:02 +020022#include "net/net.h"
Markus Armbruster46517dd2019-08-12 07:23:57 +020023#include "sysemu/sysemu.h"
Philippe Mathieu-Daudéd780d052024-01-18 21:06:38 +010024#include "target/arm/cpu-qom.h"
Andrew Jeffery43e33462016-03-16 17:06:00 +000025
Cédric Le Goaterff906062016-09-22 18:13:05 +010026#define ASPEED_SOC_IOMEM_SIZE 0x00200000
Cédric Le Goaterd783d1f2019-07-01 17:26:15 +010027
28static const hwaddr aspeed_soc_ast2400_memmap[] = {
Jamin Lindb052d02024-02-15 15:53:31 +080029 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040030 [ASPEED_DEV_IOMEM] = 0x1E600000,
31 [ASPEED_DEV_FMC] = 0x1E620000,
32 [ASPEED_DEV_SPI1] = 0x1E630000,
33 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
34 [ASPEED_DEV_VIC] = 0x1E6C0000,
35 [ASPEED_DEV_SDMC] = 0x1E6E0000,
36 [ASPEED_DEV_SCU] = 0x1E6E2000,
Joel Stanleya3888d72021-05-01 10:03:51 +020037 [ASPEED_DEV_HACE] = 0x1E6E3000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040038 [ASPEED_DEV_XDMA] = 0x1E6E7000,
39 [ASPEED_DEV_VIDEO] = 0x1E700000,
40 [ASPEED_DEV_ADC] = 0x1E6E9000,
41 [ASPEED_DEV_SRAM] = 0x1E720000,
42 [ASPEED_DEV_SDHCI] = 0x1E740000,
43 [ASPEED_DEV_GPIO] = 0x1E780000,
44 [ASPEED_DEV_RTC] = 0x1E781000,
45 [ASPEED_DEV_TIMER1] = 0x1E782000,
46 [ASPEED_DEV_WDT] = 0x1E785000,
47 [ASPEED_DEV_PWM] = 0x1E786000,
48 [ASPEED_DEV_LPC] = 0x1E789000,
49 [ASPEED_DEV_IBT] = 0x1E789140,
50 [ASPEED_DEV_I2C] = 0x1E78A000,
Peter Delevoryas55c57022022-06-30 09:21:14 +020051 [ASPEED_DEV_PECI] = 0x1E78B000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040052 [ASPEED_DEV_ETH1] = 0x1E660000,
53 [ASPEED_DEV_ETH2] = 0x1E680000,
54 [ASPEED_DEV_UART1] = 0x1E783000,
Peter Delevoryasab5e8602022-05-25 10:31:33 +020055 [ASPEED_DEV_UART2] = 0x1E78D000,
56 [ASPEED_DEV_UART3] = 0x1E78E000,
57 [ASPEED_DEV_UART4] = 0x1E78F000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040058 [ASPEED_DEV_UART5] = 0x1E784000,
59 [ASPEED_DEV_VUART] = 0x1E787000,
60 [ASPEED_DEV_SDRAM] = 0x40000000,
Cédric Le Goaterd783d1f2019-07-01 17:26:15 +010061};
62
63static const hwaddr aspeed_soc_ast2500_memmap[] = {
Jamin Lindb052d02024-02-15 15:53:31 +080064 [ASPEED_DEV_SPI_BOOT] = 0x00000000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040065 [ASPEED_DEV_IOMEM] = 0x1E600000,
66 [ASPEED_DEV_FMC] = 0x1E620000,
67 [ASPEED_DEV_SPI1] = 0x1E630000,
68 [ASPEED_DEV_SPI2] = 0x1E631000,
69 [ASPEED_DEV_EHCI1] = 0x1E6A1000,
70 [ASPEED_DEV_EHCI2] = 0x1E6A3000,
71 [ASPEED_DEV_VIC] = 0x1E6C0000,
72 [ASPEED_DEV_SDMC] = 0x1E6E0000,
73 [ASPEED_DEV_SCU] = 0x1E6E2000,
Joel Stanleya3888d72021-05-01 10:03:51 +020074 [ASPEED_DEV_HACE] = 0x1E6E3000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040075 [ASPEED_DEV_XDMA] = 0x1E6E7000,
76 [ASPEED_DEV_ADC] = 0x1E6E9000,
77 [ASPEED_DEV_VIDEO] = 0x1E700000,
78 [ASPEED_DEV_SRAM] = 0x1E720000,
79 [ASPEED_DEV_SDHCI] = 0x1E740000,
80 [ASPEED_DEV_GPIO] = 0x1E780000,
81 [ASPEED_DEV_RTC] = 0x1E781000,
82 [ASPEED_DEV_TIMER1] = 0x1E782000,
83 [ASPEED_DEV_WDT] = 0x1E785000,
84 [ASPEED_DEV_PWM] = 0x1E786000,
85 [ASPEED_DEV_LPC] = 0x1E789000,
86 [ASPEED_DEV_IBT] = 0x1E789140,
87 [ASPEED_DEV_I2C] = 0x1E78A000,
Peter Delevoryas55c57022022-06-30 09:21:14 +020088 [ASPEED_DEV_PECI] = 0x1E78B000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040089 [ASPEED_DEV_ETH1] = 0x1E660000,
90 [ASPEED_DEV_ETH2] = 0x1E680000,
91 [ASPEED_DEV_UART1] = 0x1E783000,
Peter Delevoryasab5e8602022-05-25 10:31:33 +020092 [ASPEED_DEV_UART2] = 0x1E78D000,
93 [ASPEED_DEV_UART3] = 0x1E78E000,
94 [ASPEED_DEV_UART4] = 0x1E78F000,
Eduardo Habkost347df6f2020-08-25 15:20:02 -040095 [ASPEED_DEV_UART5] = 0x1E784000,
96 [ASPEED_DEV_VUART] = 0x1E787000,
97 [ASPEED_DEV_SDRAM] = 0x80000000,
Cédric Le Goaterd783d1f2019-07-01 17:26:15 +010098};
Andrew Jeffery43e33462016-03-16 17:06:00 +000099
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100100static const int aspeed_soc_ast2400_irqmap[] = {
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400101 [ASPEED_DEV_UART1] = 9,
102 [ASPEED_DEV_UART2] = 32,
103 [ASPEED_DEV_UART3] = 33,
104 [ASPEED_DEV_UART4] = 34,
105 [ASPEED_DEV_UART5] = 10,
106 [ASPEED_DEV_VUART] = 8,
107 [ASPEED_DEV_FMC] = 19,
108 [ASPEED_DEV_EHCI1] = 5,
109 [ASPEED_DEV_EHCI2] = 13,
110 [ASPEED_DEV_SDMC] = 0,
111 [ASPEED_DEV_SCU] = 21,
112 [ASPEED_DEV_ADC] = 31,
113 [ASPEED_DEV_GPIO] = 20,
114 [ASPEED_DEV_RTC] = 22,
115 [ASPEED_DEV_TIMER1] = 16,
116 [ASPEED_DEV_TIMER2] = 17,
117 [ASPEED_DEV_TIMER3] = 18,
118 [ASPEED_DEV_TIMER4] = 35,
119 [ASPEED_DEV_TIMER5] = 36,
120 [ASPEED_DEV_TIMER6] = 37,
121 [ASPEED_DEV_TIMER7] = 38,
122 [ASPEED_DEV_TIMER8] = 39,
123 [ASPEED_DEV_WDT] = 27,
124 [ASPEED_DEV_PWM] = 28,
125 [ASPEED_DEV_LPC] = 8,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400126 [ASPEED_DEV_I2C] = 12,
Peter Delevoryas55c57022022-06-30 09:21:14 +0200127 [ASPEED_DEV_PECI] = 15,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400128 [ASPEED_DEV_ETH1] = 2,
129 [ASPEED_DEV_ETH2] = 3,
130 [ASPEED_DEV_XDMA] = 6,
131 [ASPEED_DEV_SDHCI] = 26,
Joel Stanleya3888d72021-05-01 10:03:51 +0200132 [ASPEED_DEV_HACE] = 4,
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100133};
Andrew Jeffery43e33462016-03-16 17:06:00 +0000134
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100135#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
136
Cédric Le Goater699db712022-05-25 10:31:33 +0200137static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100138{
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200139 Aspeed2400SoCState *a = ASPEED2400_SOC(s);
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
141
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200142 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100143}
144
Philippe Mathieu-Daudéa1508362023-10-24 18:24:13 +0200145static void aspeed_ast2400_soc_init(Object *obj)
Andrew Jeffery43e33462016-03-16 17:06:00 +0000146{
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200147 Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
Cédric Le Goaterff906062016-09-22 18:13:05 +0100148 AspeedSoCState *s = ASPEED_SOC(obj);
Cédric Le Goaterb0332712016-09-22 18:13:05 +0100149 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Cédric Le Goaterdbcabee2016-10-17 19:22:16 +0100150 int i;
Cédric Le Goater811a5b12019-09-04 09:05:00 +0200151 char socname[8];
152 char typename[64];
153
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200154 if (sscanf(sc->name, "%7s", socname) != 1) {
Cédric Le Goater811a5b12019-09-04 09:05:00 +0200155 g_assert_not_reached();
156 }
Andrew Jeffery43e33462016-03-16 17:06:00 +0000157
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200158 for (i = 0; i < sc->num_cpus; i++) {
Philippe Mathieu-Daudéd8156492024-01-25 06:55:43 +0100159 object_initialize_child(obj, "cpu[*]", &a->cpu[i],
160 aspeed_soc_cpu_type(sc));
Cédric Le Goaterece09be2019-07-01 17:26:16 +0100161 }
Andrew Jeffery43e33462016-03-16 17:06:00 +0000162
Cédric Le Goater9a937f62019-09-04 09:05:05 +0200163 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200164 object_initialize_child(obj, "scu", &s->scu, typename);
Andrew Jeffery334973b2016-06-27 15:37:33 +0100165 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200166 sc->silicon_rev);
Andrew Jeffery334973b2016-06-27 15:37:33 +0100167 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
Markus Armbrusterd2623122020-05-05 17:29:22 +0200168 "hw-strap1");
Andrew Jeffery334973b2016-06-27 15:37:33 +0100169 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
Markus Armbrusterd2623122020-05-05 17:29:22 +0200170 "hw-strap2");
Joel Stanleyb6e70d12017-11-14 22:50:18 +1030171 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
Markus Armbrusterd2623122020-05-05 17:29:22 +0200172 "hw-prot-key");
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100173
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200174 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100175
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200176 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
Joel Stanley75fb4572019-07-01 17:26:16 +0100177
Cédric Le Goater72d96f82019-09-25 16:32:29 +0200178 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200179 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100180
Andrew Jeffery199fd622021-10-12 08:20:08 +0200181 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
182 object_initialize_child(obj, "adc", &s->adc, typename);
183
Cédric Le Goaterf7da1aa2019-09-25 16:32:40 +0200184 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200185 object_initialize_child(obj, "i2c", &s->i2c, typename);
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100186
Peter Delevoryas55c57022022-06-30 09:21:14 +0200187 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
188
Cédric Le Goater811a5b12019-09-04 09:05:00 +0200189 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200190 object_initialize_child(obj, "fmc", &s->fmc, typename);
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100191
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200192 for (i = 0; i < sc->spis_num; i++) {
Cédric Le Goater811a5b12019-09-04 09:05:00 +0200193 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200194 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
Cédric Le Goaterdbcabee2016-10-17 19:22:16 +0100195 }
Cédric Le Goaterc2da8a82016-09-06 19:52:17 +0100196
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800197 for (i = 0; i < sc->ehcis_num; i++) {
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200198 object_initialize_child(obj, "ehci[*]", &s->ehci[i],
199 TYPE_PLATFORM_EHCI);
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800200 }
201
Cédric Le Goater8e00d1a2019-09-25 16:32:33 +0200202 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200203 object_initialize_child(obj, "sdmc", &s->sdmc, typename);
Cédric Le Goaterc6c7cfb2016-09-22 18:13:06 +0100204 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
Markus Armbrusterd2623122020-05-05 17:29:22 +0200205 "ram-size");
Cédric Le Goater013befe2017-02-07 18:29:59 +0000206
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200207 for (i = 0; i < sc->wdts_num; i++) {
Cédric Le Goater6112bd62019-09-25 16:32:35 +0200208 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200209 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
Joel Stanleyf986ee12017-07-11 11:21:26 +0100210 }
Cédric Le Goaterea337c62017-04-14 10:35:02 +0200211
Joel Stanleyd300db02019-09-25 16:32:46 +0200212 for (i = 0; i < sc->macs_num; i++) {
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200213 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
214 TYPE_FTGMAC100);
Cédric Le Goater67340992019-07-01 17:26:16 +0100215 }
Eddie James118c82e2019-07-01 17:26:18 +0100216
Peter Delevoryasd2b3eae2022-07-14 16:24:38 +0200217 for (i = 0; i < sc->uarts_num; i++) {
218 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
219 }
220
Cédric Le Goater8efbee22021-05-01 10:03:52 +0200221 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
222 object_initialize_child(obj, "xdma", &s->xdma, typename);
Rashmica Guptafdcc7c02019-09-04 09:04:58 +0200223
Cédric Le Goater811a5b12019-09-04 09:05:00 +0200224 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
Markus Armbrusterdb873cc2020-06-10 07:32:37 +0200225 object_initialize_child(obj, "gpio", &s->gpio, typename);
Eddie James2bea1282019-09-25 16:32:27 +0200226
Jamin Lin6a0238a2024-12-04 16:44:50 +0800227 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
228 object_initialize_child(obj, "sdc", &s->sdhci, typename);
Eddie James2bea1282019-09-25 16:32:27 +0200229
Markus Armbruster5325cc32020-07-07 18:05:54 +0200230 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
Andrew Jeffery0e2c24c2020-01-30 16:02:02 +0000231
Eddie James2bea1282019-09-25 16:32:27 +0200232 /* Init sd card slot class here so that they're under the correct parent */
233 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
Markus Armbruster7089e0c2020-06-10 07:32:39 +0200234 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
235 TYPE_SYSBUS_SDHCI);
Eddie James2bea1282019-09-25 16:32:27 +0200236 }
Cédric Le Goater2ecf1722021-03-09 12:01:28 +0100237
238 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
Joel Stanleya3888d72021-05-01 10:03:51 +0200239
240 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
241 object_initialize_child(obj, "hace", &s->hace, typename);
Peter Delevoryas80beb082022-06-30 09:21:13 +0200242
243 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
244 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
Andrew Jeffery43e33462016-03-16 17:06:00 +0000245}
246
Philippe Mathieu-Daudéaa6c6692023-10-24 18:24:14 +0200247static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
Andrew Jeffery43e33462016-03-16 17:06:00 +0000248{
249 int i;
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200250 Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
Cédric Le Goaterff906062016-09-22 18:13:05 +0100251 AspeedSoCState *s = ASPEED_SOC(dev);
Cédric Le Goaterdbcabee2016-10-17 19:22:16 +0100252 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
Peter Delevoryas72a7c472022-07-14 16:24:38 +0200253 g_autofree char *sram_name = NULL;
Andrew Jeffery43e33462016-03-16 17:06:00 +0000254
Cédric Le Goater5aa281d2023-03-02 13:57:50 +0100255 /* Default boot region (SPI memory or ROMs) */
256 memory_region_init(&s->spi_boot_container, OBJECT(s),
257 "aspeed.spi_boot_container", 0x10000000);
258 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
259 &s->spi_boot_container);
260
Andrew Jeffery43e33462016-03-16 17:06:00 +0000261 /* IO space */
Peter Delevoryas80beb082022-06-30 09:21:13 +0200262 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
263 sc->memmap[ASPEED_DEV_IOMEM],
264 ASPEED_SOC_IOMEM_SIZE);
Andrew Jeffery43e33462016-03-16 17:06:00 +0000265
Joel Stanley514bcf62019-09-25 16:32:48 +0200266 /* Video engine stub */
Peter Delevoryas80beb082022-06-30 09:21:13 +0200267 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
268 sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
Joel Stanley514bcf62019-09-25 16:32:48 +0200269
Cédric Le Goater2d105bd2016-12-27 14:59:26 +0000270 /* CPU */
Cédric Le Goaterb7f1a0c2020-06-09 14:23:19 +0200271 for (i = 0; i < sc->num_cpus; i++) {
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200272 object_property_set_link(OBJECT(&a->cpu[i]), "memory",
Peter Delevoryas4dd9d552022-06-30 09:21:13 +0200273 OBJECT(s->memory), &error_abort);
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200274 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
Cédric Le Goaterece09be2019-07-01 17:26:16 +0100275 return;
276 }
Cédric Le Goater2d105bd2016-12-27 14:59:26 +0000277 }
278
Cédric Le Goater74af4ee2016-12-27 14:59:27 +0000279 /* SRAM */
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200280 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
Philippe Mathieu-Daudé2198f5f2023-11-20 13:36:35 +0100281 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
282 errp)) {
Cédric Le Goater74af4ee2016-12-27 14:59:27 +0000283 return;
284 }
Peter Delevoryas4dd9d552022-06-30 09:21:13 +0200285 memory_region_add_subregion(s->memory,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400286 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
Cédric Le Goater74af4ee2016-12-27 14:59:27 +0000287
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100288 /* SCU */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200289 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100290 return;
291 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200292 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
Cédric Le Goatere2a11ca2018-06-26 17:50:42 +0100293
Andrew Jeffery43e33462016-03-16 17:06:00 +0000294 /* VIC */
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200295 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
Andrew Jeffery43e33462016-03-16 17:06:00 +0000296 return;
297 }
Philippe Mathieu-Daudédd41ce72023-10-24 18:24:22 +0200298 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
299 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
300 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
301 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
302 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
Andrew Jeffery43e33462016-03-16 17:06:00 +0000303
Joel Stanley75fb4572019-07-01 17:26:16 +0100304 /* RTC */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200305 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
Joel Stanley75fb4572019-07-01 17:26:16 +0100306 return;
307 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200308 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
Joel Stanley75fb4572019-07-01 17:26:16 +0100309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400310 aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
Joel Stanley75fb4572019-07-01 17:26:16 +0100311
Andrew Jeffery43e33462016-03-16 17:06:00 +0000312 /* Timer */
Markus Armbruster5325cc32020-07-07 18:05:54 +0200313 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
314 &error_abort);
Markus Armbruster668f62e2020-07-07 18:06:02 +0200315 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
Andrew Jeffery43e33462016-03-16 17:06:00 +0000316 return;
317 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200318 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400319 sc->memmap[ASPEED_DEV_TIMER1]);
Cédric Le Goaterb456b112019-07-01 17:26:15 +0100320 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400321 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
Andrew Jeffery43e33462016-03-16 17:06:00 +0000322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
323 }
324
Andrew Jeffery199fd622021-10-12 08:20:08 +0200325 /* ADC */
326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
327 return;
328 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200329 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
Andrew Jeffery199fd622021-10-12 08:20:08 +0200330 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
331 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
332
Peter Delevoryas470253b2022-05-25 10:31:33 +0200333 /* UART */
Peter Delevoryasd2b3eae2022-07-14 16:24:38 +0200334 if (!aspeed_soc_uart_realize(s, errp)) {
335 return;
336 }
Cédric Le Goater16020012016-06-06 16:59:29 +0100337
338 /* I2C */
Markus Armbruster5325cc32020-07-07 18:05:54 +0200339 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
Markus Armbrusterc24d97162020-06-30 11:03:41 +0200340 &error_abort);
Markus Armbruster668f62e2020-07-07 18:06:02 +0200341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
Cédric Le Goater16020012016-06-06 16:59:29 +0100342 return;
343 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200344 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
Cédric Le Goater16020012016-06-06 16:59:29 +0100345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400346 aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100347
Peter Delevoryas55c57022022-06-30 09:21:14 +0200348 /* PECI */
349 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
350 return;
351 }
352 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
353 sc->memmap[ASPEED_DEV_PECI]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
355 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
356
Cédric Le Goater26d5df92016-12-27 14:59:29 +0000357 /* FMC, The number of CS is set at the board level */
Markus Armbruster5325cc32020-07-07 18:05:54 +0200358 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
Markus Armbrusterc24d97162020-06-30 11:03:41 +0200359 &error_abort);
Markus Armbruster668f62e2020-07-07 18:06:02 +0200360 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100361 return;
362 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
364 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
Cédric Le Goater30b68522021-10-12 08:20:08 +0200365 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
Cédric Le Goater0e5803d2016-10-17 19:22:16 +0100366 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400367 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100368
Cédric Le Goater5aa281d2023-03-02 13:57:50 +0100369 /* Set up an alias on the FMC CE0 region (boot default) */
370 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
371 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
372 fmc0_mmio, 0, memory_region_size(fmc0_mmio));
373 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
374
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100375 /* SPI */
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200376 for (i = 0; i < sc->spis_num; i++) {
Markus Armbruster668f62e2020-07-07 18:06:02 +0200377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
Cédric Le Goaterdbcabee2016-10-17 19:22:16 +0100378 return;
379 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400381 sc->memmap[ASPEED_DEV_SPI1 + i]);
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200382 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
Cédric Le Goater30b68522021-10-12 08:20:08 +0200383 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
Cédric Le Goater7c1c69b2016-07-04 13:06:37 +0100384 }
Cédric Le Goaterc2da8a82016-09-06 19:52:17 +0100385
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800386 /* EHCI */
387 for (i = 0; i < sc->ehcis_num; i++) {
Markus Armbruster668f62e2020-07-07 18:06:02 +0200388 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800389 return;
390 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200391 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400392 sc->memmap[ASPEED_DEV_EHCI1 + i]);
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800393 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400394 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800395 }
396
Cédric Le Goaterc2da8a82016-09-06 19:52:17 +0100397 /* SDMC - SDRAM Memory Controller */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200398 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
Cédric Le Goaterc2da8a82016-09-06 19:52:17 +0100399 return;
400 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200401 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
402 sc->memmap[ASPEED_DEV_SDMC]);
Cédric Le Goater013befe2017-02-07 18:29:59 +0000403
404 /* Watch dog */
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200405 for (i = 0; i < sc->wdts_num; i++) {
Cédric Le Goater6112bd62019-09-25 16:32:35 +0200406 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
Philippe Mathieu-Daudé6fdb4382023-02-07 09:02:05 +0100407 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
Cédric Le Goater6112bd62019-09-25 16:32:35 +0200408
Markus Armbruster5325cc32020-07-07 18:05:54 +0200409 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
410 &error_abort);
Markus Armbruster668f62e2020-07-07 18:06:02 +0200411 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
Joel Stanleyf986ee12017-07-11 11:21:26 +0100412 return;
413 }
Philippe Mathieu-Daudé6fdb4382023-02-07 09:02:05 +0100414 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
Cédric Le Goater013befe2017-02-07 18:29:59 +0000415 }
Cédric Le Goaterea337c62017-04-14 10:35:02 +0200416
Cédric Le Goater346160c2022-06-30 09:21:13 +0200417 /* RAM */
418 if (!aspeed_soc_dram_init(s, errp)) {
419 return;
420 }
421
Cédric Le Goaterea337c62017-04-14 10:35:02 +0200422 /* Net */
Cédric Le Goaterd3bad7e2020-06-09 14:23:20 +0200423 for (i = 0; i < sc->macs_num; i++) {
Markus Armbruster5325cc32020-07-07 18:05:54 +0200424 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
Markus Armbruster2255f6b2020-06-30 11:03:48 +0200425 &error_abort);
Markus Armbruster668f62e2020-07-07 18:06:02 +0200426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
Markus Armbruster123327d2020-06-30 11:03:37 +0200427 return;
Cédric Le Goater67340992019-07-01 17:26:16 +0100428 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200429 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400430 sc->memmap[ASPEED_DEV_ETH1 + i]);
Cédric Le Goater67340992019-07-01 17:26:16 +0100431 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400432 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
Cédric Le Goaterea337c62017-04-14 10:35:02 +0200433 }
Eddie James118c82e2019-07-01 17:26:18 +0100434
435 /* XDMA */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
Eddie James118c82e2019-07-01 17:26:18 +0100437 return;
438 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200439 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400440 sc->memmap[ASPEED_DEV_XDMA]);
Eddie James118c82e2019-07-01 17:26:18 +0100441 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400442 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
Rashmica Guptafdcc7c02019-09-04 09:04:58 +0200443
444 /* GPIO */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200445 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
Rashmica Guptafdcc7c02019-09-04 09:04:58 +0200446 return;
447 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200448 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
449 sc->memmap[ASPEED_DEV_GPIO]);
Rashmica Guptafdcc7c02019-09-04 09:04:58 +0200450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400451 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
Eddie James2bea1282019-09-25 16:32:27 +0200452
453 /* SDHCI */
Markus Armbruster668f62e2020-07-07 18:06:02 +0200454 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
Eddie James2bea1282019-09-25 16:32:27 +0200455 return;
456 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200457 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400458 sc->memmap[ASPEED_DEV_SDHCI]);
Eddie James2bea1282019-09-25 16:32:27 +0200459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
Eduardo Habkost347df6f2020-08-25 15:20:02 -0400460 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
Cédric Le Goater2ecf1722021-03-09 12:01:28 +0100461
462 /* LPC */
463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
464 return;
465 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200466 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
Andrew Jefferyc59f7812021-03-09 12:01:28 +0100467
468 /* Connect the LPC IRQ to the VIC */
Cédric Le Goater2ecf1722021-03-09 12:01:28 +0100469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
470 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
Andrew Jefferyc59f7812021-03-09 12:01:28 +0100471
472 /*
473 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
474 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
475 * contrast, on the AST2600, the subdevice IRQs are connected straight to
476 * the GIC).
477 *
478 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
479 * to the VIC is at offset 0.
480 */
481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
482 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
483
484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
485 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
486
487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
488 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
489
490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
491 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
Joel Stanleya3888d72021-05-01 10:03:51 +0200492
493 /* HACE */
494 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
495 &error_abort);
496 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
497 return;
498 }
Peter Delevoryas5bfcbda2022-06-30 09:21:13 +0200499 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
500 sc->memmap[ASPEED_DEV_HACE]);
Joel Stanleya3888d72021-05-01 10:03:51 +0200501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
502 aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
Andrew Jeffery43e33462016-03-16 17:06:00 +0000503}
Andrew Jeffery43e33462016-03-16 17:06:00 +0000504
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200505static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
506{
Philippe Mathieu-Daudédc139092024-01-25 06:55:44 +0100507 static const char * const valid_cpu_types[] = {
508 ARM_CPU_TYPE_NAME("arm926"),
509 NULL
510 };
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200511 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
Philippe Mathieu-Daudéaa6c6692023-10-24 18:24:14 +0200512 DeviceClass *dc = DEVICE_CLASS(oc);
513
514 dc->realize = aspeed_ast2400_soc_realize;
515 /* Reason: Uses serial_hds and nd_table in realize() directly */
516 dc->user_creatable = false;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200517
518 sc->name = "ast2400-a1";
Philippe Mathieu-Daudédc139092024-01-25 06:55:44 +0100519 sc->valid_cpu_types = valid_cpu_types;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200520 sc->silicon_rev = AST2400_A1_SILICON_REV;
521 sc->sram_size = 0x8000;
522 sc->spis_num = 1;
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800523 sc->ehcis_num = 1;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200524 sc->wdts_num = 2;
Joel Stanleyd300db02019-09-25 16:32:46 +0200525 sc->macs_num = 2;
Peter Delevoryasc5e1bdb2022-05-25 10:31:33 +0200526 sc->uarts_num = 5;
Jamin Lin944128e2024-02-15 15:53:30 +0800527 sc->uarts_base = ASPEED_DEV_UART1;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200528 sc->irqmap = aspeed_soc_ast2400_irqmap;
529 sc->memmap = aspeed_soc_ast2400_memmap;
530 sc->num_cpus = 1;
Cédric Le Goater699db712022-05-25 10:31:33 +0200531 sc->get_irq = aspeed_soc_ast2400_get_irq;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200532}
533
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200534static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
535{
Philippe Mathieu-Daudédc139092024-01-25 06:55:44 +0100536 static const char * const valid_cpu_types[] = {
537 ARM_CPU_TYPE_NAME("arm1176"),
538 NULL
539 };
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200540 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
Philippe Mathieu-Daudéaa6c6692023-10-24 18:24:14 +0200541 DeviceClass *dc = DEVICE_CLASS(oc);
542
543 dc->realize = aspeed_ast2400_soc_realize;
544 /* Reason: Uses serial_hds and nd_table in realize() directly */
545 dc->user_creatable = false;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200546
547 sc->name = "ast2500-a1";
Philippe Mathieu-Daudédc139092024-01-25 06:55:44 +0100548 sc->valid_cpu_types = valid_cpu_types;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200549 sc->silicon_rev = AST2500_A1_SILICON_REV;
550 sc->sram_size = 0x9000;
551 sc->spis_num = 2;
Guenter Roeckbfdd34f2020-02-06 10:34:37 -0800552 sc->ehcis_num = 2;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200553 sc->wdts_num = 3;
Joel Stanleyd300db02019-09-25 16:32:46 +0200554 sc->macs_num = 2;
Peter Delevoryasc5e1bdb2022-05-25 10:31:33 +0200555 sc->uarts_num = 5;
Jamin Lin944128e2024-02-15 15:53:30 +0800556 sc->uarts_base = ASPEED_DEV_UART1;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200557 sc->irqmap = aspeed_soc_ast2500_irqmap;
558 sc->memmap = aspeed_soc_ast2500_memmap;
559 sc->num_cpus = 1;
Cédric Le Goater699db712022-05-25 10:31:33 +0200560 sc->get_irq = aspeed_soc_ast2400_get_irq;
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200561}
562
Philippe Mathieu-Daudé1a94fae2023-10-24 18:24:18 +0200563static const TypeInfo aspeed_soc_ast2400_types[] = {
564 {
565 .name = TYPE_ASPEED2400_SOC,
566 .parent = TYPE_ASPEED_SOC,
567 .instance_init = aspeed_ast2400_soc_init,
568 .instance_size = sizeof(Aspeed2400SoCState),
569 .abstract = true,
570 }, {
571 .name = "ast2400-a1",
572 .parent = TYPE_ASPEED2400_SOC,
573 .class_init = aspeed_soc_ast2400_class_init,
574 }, {
575 .name = "ast2500-a1",
576 .parent = TYPE_ASPEED2400_SOC,
577 .class_init = aspeed_soc_ast2500_class_init,
578 },
Cédric Le Goater54ecafb2019-09-25 16:32:42 +0200579};
Andrew Jeffery43e33462016-03-16 17:06:00 +0000580
Philippe Mathieu-Daudé1a94fae2023-10-24 18:24:18 +0200581DEFINE_TYPES(aspeed_soc_ast2400_types)