Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 1 | /* |
| 2 | * pcie_host.c |
| 3 | * utility functions for pci express host bridge. |
| 4 | * |
| 5 | * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> |
| 6 | * VA Linux Systems Japan K.K. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | |
| 18 | * You should have received a copy of the GNU General Public License along |
Blue Swirl | 70539e1 | 2010-03-07 15:48:43 +0000 | [diff] [blame] | 19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 20 | */ |
| 21 | |
| 22 | #include "hw.h" |
| 23 | #include "pci.h" |
| 24 | #include "pcie_host.h" |
| 25 | |
| 26 | /* |
| 27 | * PCI express mmcfig address |
| 28 | * bit 20 - 28: bus number |
| 29 | * bit 15 - 19: device number |
| 30 | * bit 12 - 14: function number |
| 31 | * bit 0 - 11: offset in configuration space of a given device |
| 32 | */ |
| 33 | #define PCIE_MMCFG_SIZE_MAX (1ULL << 28) |
| 34 | #define PCIE_MMCFG_SIZE_MIN (1ULL << 20) |
| 35 | #define PCIE_MMCFG_BUS_BIT 20 |
| 36 | #define PCIE_MMCFG_BUS_MASK 0x1ff |
| 37 | #define PCIE_MMCFG_DEVFN_BIT 12 |
| 38 | #define PCIE_MMCFG_DEVFN_MASK 0xff |
| 39 | #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff |
| 40 | #define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \ |
| 41 | PCIE_MMCFG_BUS_MASK) |
| 42 | #define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \ |
| 43 | PCIE_MMCFG_DEVFN_MASK) |
| 44 | #define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK) |
| 45 | |
| 46 | |
| 47 | /* a helper function to get a PCIDevice for a given mmconfig address */ |
Isaku Yamahata | 8d6514f | 2009-11-12 13:17:23 +0200 | [diff] [blame] | 48 | static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, |
| 49 | uint32_t mmcfg_addr) |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 50 | { |
| 51 | return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr), |
| 52 | PCI_SLOT(PCIE_MMCFG_DEVFN(mmcfg_addr)), |
| 53 | PCI_FUNC(PCIE_MMCFG_DEVFN(mmcfg_addr))); |
| 54 | } |
| 55 | |
| 56 | static void pcie_mmcfg_data_write(PCIBus *s, |
| 57 | uint32_t mmcfg_addr, uint32_t val, int len) |
| 58 | { |
Isaku Yamahata | 8d6514f | 2009-11-12 13:17:23 +0200 | [diff] [blame] | 59 | PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr); |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 60 | |
| 61 | if (!pci_dev) |
| 62 | return; |
| 63 | |
| 64 | pci_dev->config_write(pci_dev, |
| 65 | PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len); |
| 66 | } |
| 67 | |
Michael S. Tsirkin | 4677d8e | 2009-11-12 14:58:31 +0900 | [diff] [blame] | 68 | static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len) |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 69 | { |
Isaku Yamahata | 8d6514f | 2009-11-12 13:17:23 +0200 | [diff] [blame] | 70 | PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, addr); |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 71 | |
Michael S. Tsirkin | 4677d8e | 2009-11-12 14:58:31 +0900 | [diff] [blame] | 72 | assert(len == 1 || len == 2 || len == 4); |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 73 | if (!pci_dev) { |
Michael S. Tsirkin | 4677d8e | 2009-11-12 14:58:31 +0900 | [diff] [blame] | 74 | return ~0x0; |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 75 | } |
Michael S. Tsirkin | 4677d8e | 2009-11-12 14:58:31 +0900 | [diff] [blame] | 76 | return pci_dev->config_read(pci_dev, PCIE_MMCFG_CONFOFFSET(addr), len); |
Isaku Yamahata | a9f4994 | 2009-10-30 21:21:18 +0900 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void pcie_mmcfg_data_writeb(void *opaque, |
| 80 | target_phys_addr_t addr, uint32_t value) |
| 81 | { |
| 82 | PCIExpressHost *e = opaque; |
| 83 | pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1); |
| 84 | } |
| 85 | |
| 86 | static void pcie_mmcfg_data_writew(void *opaque, |
| 87 | target_phys_addr_t addr, uint32_t value) |
| 88 | { |
| 89 | PCIExpressHost *e = opaque; |
| 90 | pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2); |
| 91 | } |
| 92 | |
| 93 | static void pcie_mmcfg_data_writel(void *opaque, |
| 94 | target_phys_addr_t addr, uint32_t value) |
| 95 | { |
| 96 | PCIExpressHost *e = opaque; |
| 97 | pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4); |
| 98 | } |
| 99 | |
| 100 | static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr) |
| 101 | { |
| 102 | PCIExpressHost *e = opaque; |
| 103 | return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1); |
| 104 | } |
| 105 | |
| 106 | static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr) |
| 107 | { |
| 108 | PCIExpressHost *e = opaque; |
| 109 | return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2); |
| 110 | } |
| 111 | |
| 112 | static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr) |
| 113 | { |
| 114 | PCIExpressHost *e = opaque; |
| 115 | return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4); |
| 116 | } |
| 117 | |
| 118 | |
| 119 | static CPUWriteMemoryFunc * const pcie_mmcfg_write[] = |
| 120 | { |
| 121 | pcie_mmcfg_data_writeb, |
| 122 | pcie_mmcfg_data_writew, |
| 123 | pcie_mmcfg_data_writel, |
| 124 | }; |
| 125 | |
| 126 | static CPUReadMemoryFunc * const pcie_mmcfg_read[] = |
| 127 | { |
| 128 | pcie_mmcfg_data_readb, |
| 129 | pcie_mmcfg_data_readw, |
| 130 | pcie_mmcfg_data_readl, |
| 131 | }; |
| 132 | |
| 133 | /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ |
| 134 | #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) |
| 135 | |
| 136 | int pcie_host_init(PCIExpressHost *e) |
| 137 | { |
| 138 | e->base_addr = PCIE_BASE_ADDR_UNMAPPED; |
| 139 | e->mmio_index = |
| 140 | cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e); |
| 141 | if (e->mmio_index < 0) { |
| 142 | return -1; |
| 143 | } |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | void pcie_host_mmcfg_unmap(PCIExpressHost *e) |
| 149 | { |
| 150 | if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { |
| 151 | cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED); |
| 152 | e->base_addr = PCIE_BASE_ADDR_UNMAPPED; |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | void pcie_host_mmcfg_map(PCIExpressHost *e, |
| 157 | target_phys_addr_t addr, uint32_t size) |
| 158 | { |
| 159 | assert(!(size & (size - 1))); /* power of 2 */ |
| 160 | assert(size >= PCIE_MMCFG_SIZE_MIN); |
| 161 | assert(size <= PCIE_MMCFG_SIZE_MAX); |
| 162 | |
| 163 | e->base_addr = addr; |
| 164 | e->size = size; |
| 165 | cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index); |
| 166 | } |
| 167 | |
| 168 | void pcie_host_mmcfg_update(PCIExpressHost *e, |
| 169 | int enable, |
| 170 | target_phys_addr_t addr, uint32_t size) |
| 171 | { |
| 172 | pcie_host_mmcfg_unmap(e); |
| 173 | if (enable) { |
| 174 | pcie_host_mmcfg_map(e, addr, size); |
| 175 | } |
| 176 | } |