Isaku Yamahata | 8135aee | 2010-10-20 17:18:53 +0900 | [diff] [blame] | 1 | /* |
| 2 | * ioh3420.c |
| 3 | * Intel X58 north bridge IOH |
| 4 | * PCI Express root port device id 3420 |
| 5 | * |
| 6 | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> |
| 7 | * VA Linux Systems Japan K.K. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #include "pci_ids.h" |
| 24 | #include "msi.h" |
| 25 | #include "pcie.h" |
| 26 | #include "ioh3420.h" |
| 27 | |
| 28 | #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ |
| 29 | #define PCI_DEVICE_ID_IOH_REV 0x2 |
| 30 | #define IOH_EP_SSVID_OFFSET 0x40 |
| 31 | #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL |
| 32 | #define IOH_EP_SSVID_SSID 0 |
| 33 | #define IOH_EP_MSI_OFFSET 0x60 |
| 34 | #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT |
| 35 | #define IOH_EP_MSI_NR_VECTOR 2 |
| 36 | #define IOH_EP_EXP_OFFSET 0x90 |
| 37 | #define IOH_EP_AER_OFFSET 0x100 |
| 38 | |
| 39 | static void ioh3420_write_config(PCIDevice *d, |
| 40 | uint32_t address, uint32_t val, int len) |
| 41 | { |
Isaku Yamahata | 8135aee | 2010-10-20 17:18:53 +0900 | [diff] [blame] | 42 | pci_bridge_write_config(d, address, val, len); |
| 43 | msi_write_config(d, address, val, len); |
Michael S. Tsirkin | 6bde6aa | 2010-10-25 07:46:47 +0200 | [diff] [blame] | 44 | pcie_cap_slot_write_config(d, address, val, len); |
Isaku Yamahata | 8135aee | 2010-10-20 17:18:53 +0900 | [diff] [blame] | 45 | /* TODO: AER */ |
| 46 | } |
| 47 | |
| 48 | static void ioh3420_reset(DeviceState *qdev) |
| 49 | { |
| 50 | PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); |
| 51 | msi_reset(d); |
| 52 | pcie_cap_root_reset(d); |
| 53 | pcie_cap_deverr_reset(d); |
| 54 | pcie_cap_slot_reset(d); |
| 55 | pci_bridge_reset(qdev); |
| 56 | pci_bridge_disable_base_limit(d); |
| 57 | /* TODO: AER */ |
| 58 | } |
| 59 | |
| 60 | static int ioh3420_initfn(PCIDevice *d) |
| 61 | { |
| 62 | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
| 63 | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
| 64 | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
| 65 | int rc; |
| 66 | |
| 67 | rc = pci_bridge_initfn(d); |
| 68 | if (rc < 0) { |
| 69 | return rc; |
| 70 | } |
| 71 | |
| 72 | d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV; |
| 73 | pcie_port_init_reg(d); |
| 74 | |
| 75 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); |
| 76 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT); |
| 77 | |
| 78 | rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, |
| 79 | IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); |
| 80 | if (rc < 0) { |
| 81 | return rc; |
| 82 | } |
| 83 | rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, |
| 84 | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
| 85 | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
| 86 | if (rc < 0) { |
| 87 | return rc; |
| 88 | } |
| 89 | rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); |
| 90 | if (rc < 0) { |
| 91 | return rc; |
| 92 | } |
| 93 | pcie_cap_deverr_init(d); |
| 94 | pcie_cap_slot_init(d, s->slot); |
| 95 | pcie_chassis_create(s->chassis); |
| 96 | rc = pcie_chassis_add_slot(s); |
| 97 | if (rc < 0) { |
| 98 | return rc; |
| 99 | } |
| 100 | pcie_cap_root_init(d); |
| 101 | /* TODO: AER */ |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | static int ioh3420_exitfn(PCIDevice *d) |
| 106 | { |
| 107 | /* TODO: AER */ |
| 108 | msi_uninit(d); |
| 109 | pcie_cap_exit(d); |
| 110 | return pci_bridge_exitfn(d); |
| 111 | } |
| 112 | |
| 113 | PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, |
| 114 | const char *bus_name, pci_map_irq_fn map_irq, |
| 115 | uint8_t port, uint8_t chassis, uint16_t slot) |
| 116 | { |
| 117 | PCIDevice *d; |
| 118 | PCIBridge *br; |
| 119 | DeviceState *qdev; |
| 120 | |
| 121 | d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420"); |
| 122 | if (!d) { |
| 123 | return NULL; |
| 124 | } |
| 125 | br = DO_UPCAST(PCIBridge, dev, d); |
| 126 | |
| 127 | qdev = &br->dev.qdev; |
| 128 | pci_bridge_map_irq(br, bus_name, map_irq); |
| 129 | qdev_prop_set_uint8(qdev, "port", port); |
| 130 | qdev_prop_set_uint8(qdev, "chassis", chassis); |
| 131 | qdev_prop_set_uint16(qdev, "slot", slot); |
| 132 | qdev_init_nofail(qdev); |
| 133 | |
| 134 | return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); |
| 135 | } |
| 136 | |
| 137 | static const VMStateDescription vmstate_ioh3420 = { |
| 138 | .name = "ioh-3240-express-root-port", |
| 139 | .version_id = 1, |
| 140 | .minimum_version_id = 1, |
| 141 | .minimum_version_id_old = 1, |
Michael S. Tsirkin | 6bde6aa | 2010-10-25 07:46:47 +0200 | [diff] [blame] | 142 | .post_load = pcie_cap_slot_post_load, |
Isaku Yamahata | 8135aee | 2010-10-20 17:18:53 +0900 | [diff] [blame] | 143 | .fields = (VMStateField[]) { |
| 144 | VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
| 145 | /* TODO: AER */ |
| 146 | VMSTATE_END_OF_LIST() |
| 147 | } |
| 148 | }; |
| 149 | |
| 150 | static PCIDeviceInfo ioh3420_info = { |
| 151 | .qdev.name = "ioh3420", |
| 152 | .qdev.desc = "Intel IOH device id 3420 PCIE Root Port", |
| 153 | .qdev.size = sizeof(PCIESlot), |
| 154 | .qdev.reset = ioh3420_reset, |
| 155 | .qdev.vmsd = &vmstate_ioh3420, |
| 156 | |
| 157 | .is_express = 1, |
| 158 | .is_bridge = 1, |
| 159 | .config_write = ioh3420_write_config, |
| 160 | .init = ioh3420_initfn, |
| 161 | .exit = ioh3420_exitfn, |
| 162 | |
| 163 | .qdev.props = (Property[]) { |
| 164 | DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), |
| 165 | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
| 166 | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
| 167 | /* TODO: AER */ |
| 168 | DEFINE_PROP_END_OF_LIST(), |
| 169 | } |
| 170 | }; |
| 171 | |
| 172 | static void ioh3420_register(void) |
| 173 | { |
| 174 | pci_qdev_register(&ioh3420_info); |
| 175 | } |
| 176 | |
| 177 | device_init(ioh3420_register); |
| 178 | |
| 179 | /* |
| 180 | * Local variables: |
| 181 | * c-indent-level: 4 |
| 182 | * c-basic-offset: 4 |
| 183 | * tab-width: 8 |
| 184 | * indent-tab-mode: nil |
| 185 | * End: |
| 186 | */ |