| Thomas Huth | e3355a0 | 2018-06-30 07:19:42 +0200 | [diff] [blame] | 1 | |
| 2 | #ifndef NEXT_CUBE_H |
| 3 | #define NEXT_CUBE_H |
| 4 | |
| 5 | #define TYPE_NEXTFB "next-fb" |
| 6 | |
| Thomas Huth | c8e8bc8 | 2018-06-30 07:50:23 +0200 | [diff] [blame] | 7 | #define TYPE_NEXTKBD "next-kbd" |
| 8 | |
| Thomas Huth | 956a781 | 2018-06-30 08:45:25 +0200 | [diff] [blame^] | 9 | enum next_dma_chan { |
| 10 | NEXTDMA_FD, |
| 11 | NEXTDMA_ENRX, |
| 12 | NEXTDMA_ENTX, |
| 13 | NEXTDMA_SCSI, |
| 14 | NEXTDMA_SCC, |
| 15 | NEXTDMA_SND |
| 16 | }; |
| 17 | |
| 18 | #define DMA_ENABLE 0x01000000 |
| 19 | #define DMA_SUPDATE 0x02000000 |
| 20 | #define DMA_COMPLETE 0x08000000 |
| 21 | |
| 22 | #define DMA_M2DEV 0x0 |
| 23 | #define DMA_SETENABLE 0x00010000 |
| 24 | #define DMA_SETSUPDATE 0x00020000 |
| 25 | #define DMA_DEV2M 0x00040000 |
| 26 | #define DMA_CLRCOMPLETE 0x00080000 |
| 27 | #define DMA_RESET 0x00100000 |
| 28 | |
| 29 | enum next_irqs { |
| 30 | NEXT_FD_I, |
| 31 | NEXT_KBD_I, |
| 32 | NEXT_PWR_I, |
| 33 | NEXT_ENRX_I, |
| 34 | NEXT_ENTX_I, |
| 35 | NEXT_SCSI_I, |
| 36 | NEXT_CLK_I, |
| 37 | NEXT_SCC_I, |
| 38 | NEXT_ENTX_DMA_I, |
| 39 | NEXT_ENRX_DMA_I, |
| 40 | NEXT_SCSI_DMA_I, |
| 41 | NEXT_SCC_DMA_I, |
| 42 | NEXT_SND_I |
| 43 | }; |
| 44 | |
| 45 | void next_irq(void *opaque, int number, int level); |
| 46 | |
| Thomas Huth | e3355a0 | 2018-06-30 07:19:42 +0200 | [diff] [blame] | 47 | #endif /* NEXT_CUBE_H */ |
