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j_mayer3cbee152007-10-28 23:42:18 +00001/*
aurel324d7ca412009-01-07 23:38:59 +00002 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
j_mayer3cbee152007-10-28 23:42:18 +00003 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
26#include "ppc.h"
j_mayer3cbee152007-10-28 23:42:18 +000027#include "ppc_mac.h"
aurel3228ce5ce2009-01-30 20:39:32 +000028#include "mac_dbdma.h"
pbrook87ecb682007-11-17 17:14:51 +000029#include "nvram.h"
30#include "pc.h"
31#include "sysemu.h"
32#include "net.h"
33#include "isa.h"
34#include "pci.h"
35#include "boards.h"
blueswir1271dd5e2008-12-24 20:29:16 +000036#include "fw_cfg.h"
blueswir17fa9ae12009-01-12 17:40:23 +000037#include "escc.h"
Gerd Hoffmann977e1242009-08-20 15:22:20 +020038#include "ide.h"
j_mayer3cbee152007-10-28 23:42:18 +000039
thse4bcb142007-12-02 04:51:10 +000040#define MAX_IDE_BUS 2
aurel32a748ab62008-12-20 23:40:35 +000041#define VGA_BIOS_SIZE 65536
blueswir1271dd5e2008-12-24 20:29:16 +000042#define CFG_ADDR 0xf0000510
43
j_mayer3cbee152007-10-28 23:42:18 +000044/* temporary frame buffer OSI calls for the video.x driver. The right
45 solution is to modify the driver to use VGA PCI I/Os */
46/* XXX: to be removed. This is no way related to emulation */
47static int vga_osi_call (CPUState *env)
48{
49 static int vga_vbl_enabled;
50 int linesize;
51
Blue Swirlb11ebf62009-08-16 11:54:37 +000052#if 0
53 printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
54#endif
j_mayer3cbee152007-10-28 23:42:18 +000055
56 /* same handler as PearPC, coming from the original MOL video
57 driver. */
58 switch(env->gpr[5]) {
59 case 4:
60 break;
61 case 28: /* set_vmode */
62 if (env->gpr[6] != 1 || env->gpr[7] != 0)
63 env->gpr[3] = 1;
64 else
65 env->gpr[3] = 0;
66 break;
67 case 29: /* get_vmode_info */
68 if (env->gpr[6] != 0) {
69 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
70 env->gpr[3] = 1;
71 break;
72 }
73 }
74 env->gpr[3] = 0;
75 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
76 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
77 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
78 env->gpr[7] = 85 << 16; /* refresh rate */
79 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
80 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
81 linesize = (linesize + 3) & ~3;
82 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
83 break;
84 case 31: /* set_video power */
85 env->gpr[3] = 0;
86 break;
87 case 39: /* video_ctrl */
88 if (env->gpr[6] == 0 || env->gpr[6] == 1)
89 vga_vbl_enabled = env->gpr[6];
90 env->gpr[3] = 0;
91 break;
92 case 47:
93 break;
94 case 59: /* set_color */
95 /* R6 = index, R7 = RGB */
96 env->gpr[3] = 0;
97 break;
98 case 64: /* get color */
99 /* R6 = index */
100 env->gpr[3] = 0;
101 break;
102 case 116: /* set hwcursor */
103 /* R6 = x, R7 = y, R8 = visible, R9 = data */
104 break;
105 default:
Blue Swirlb11ebf62009-08-16 11:54:37 +0000106 fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
j_mayeraae93662007-11-24 02:56:36 +0000107 ppc_dump_gpr(env, 5));
j_mayer3cbee152007-10-28 23:42:18 +0000108 break;
109 }
110
111 return 1; /* osi_call handled */
112}
113
blueswir1513f7892009-03-08 09:51:29 +0000114static int fw_cfg_boot_set(void *opaque, const char *boot_device)
115{
116 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
117 return 0;
118}
119
Paul Brookfbe1b592009-05-13 17:56:25 +0100120static void ppc_heathrow_init (ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000121 const char *boot_device,
j_mayer3cbee152007-10-28 23:42:18 +0000122 const char *kernel_filename,
123 const char *kernel_cmdline,
124 const char *initrd_filename,
125 const char *cpu_model)
126{
bellardaaed9092007-11-10 15:15:54 +0000127 CPUState *env = NULL, *envs[MAX_CPUS];
Paul Brook5cea8592009-05-30 00:52:44 +0100128 char *filename;
j_mayer3cbee152007-10-28 23:42:18 +0000129 qemu_irq *pic, **heathrow_irqs;
j_mayer3cbee152007-10-28 23:42:18 +0000130 int linux_boot, i;
pbrookb5847262009-04-10 02:24:36 +0000131 ram_addr_t ram_offset, bios_offset, vga_bios_offset;
blueswir173730482009-01-24 12:00:23 +0000132 uint32_t kernel_base, initrd_base;
133 int32_t kernel_size, initrd_size;
j_mayer3cbee152007-10-28 23:42:18 +0000134 PCIBus *pci_bus;
135 MacIONVRAMState *nvr;
136 int vga_bios_size, bios_size;
j_mayer3cbee152007-10-28 23:42:18 +0000137 int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
blueswir17fa9ae12009-01-12 17:40:23 +0000138 int escc_mem_index, ide_mem_index[2];
blueswir1513f7892009-03-08 09:51:29 +0000139 uint16_t ppc_boot_device;
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200140 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
blueswir1271dd5e2008-12-24 20:29:16 +0000141 void *fw_cfg;
aurel3228ce5ce2009-01-30 20:39:32 +0000142 void *dbdma;
pbrook44654492009-04-10 00:26:15 +0000143 uint8_t *vga_bios_ptr;
j_mayer3cbee152007-10-28 23:42:18 +0000144
145 linux_boot = (kernel_filename != NULL);
146
147 /* init CPUs */
j_mayer3cbee152007-10-28 23:42:18 +0000148 if (cpu_model == NULL)
aurel32f2fde452008-12-20 23:39:46 +0000149 cpu_model = "G3";
j_mayer3cbee152007-10-28 23:42:18 +0000150 for (i = 0; i < smp_cpus; i++) {
bellardaaed9092007-11-10 15:15:54 +0000151 env = cpu_init(cpu_model);
152 if (!env) {
153 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
154 exit(1);
155 }
aurel32b0fb43d2009-01-14 14:48:04 +0000156 /* Set time-base frequency to 16.6 Mhz */
157 cpu_ppc_tb_init(env, 16600000UL);
j_mayer3cbee152007-10-28 23:42:18 +0000158 env->osi_call = vga_osi_call;
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200159 qemu_register_reset(&cpu_ppc_reset, env);
j_mayer3cbee152007-10-28 23:42:18 +0000160 envs[i] = env;
161 }
162
163 /* allocate RAM */
aurel326b4079f2009-01-13 19:08:10 +0000164 if (ram_size > (2047 << 20)) {
165 fprintf(stderr,
166 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
167 ((unsigned int)ram_size / (1 << 20)));
168 exit(1);
169 }
170
aurel32a748ab62008-12-20 23:40:35 +0000171 ram_offset = qemu_ram_alloc(ram_size);
172 cpu_register_physical_memory(0, ram_size, ram_offset);
173
j_mayer3cbee152007-10-28 23:42:18 +0000174 /* allocate and load BIOS */
aurel32a748ab62008-12-20 23:40:35 +0000175 bios_offset = qemu_ram_alloc(BIOS_SIZE);
j_mayer3cbee152007-10-28 23:42:18 +0000176 if (bios_name == NULL)
blueswir1992e5ac2008-12-24 20:23:51 +0000177 bios_name = PROM_FILENAME;
Paul Brook5cea8592009-05-30 00:52:44 +0100178 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
blueswir1992e5ac2008-12-24 20:23:51 +0000179 cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
180
181 /* Load OpenBIOS (ELF) */
Paul Brook5cea8592009-05-30 00:52:44 +0100182 if (filename) {
183 bios_size = load_elf(filename, 0, NULL, NULL, NULL);
184 qemu_free(filename);
185 } else {
186 bios_size = -1;
187 }
j_mayer3cbee152007-10-28 23:42:18 +0000188 if (bios_size < 0 || bios_size > BIOS_SIZE) {
Paul Brook5cea8592009-05-30 00:52:44 +0100189 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
j_mayer3cbee152007-10-28 23:42:18 +0000190 exit(1);
191 }
j_mayer3cbee152007-10-28 23:42:18 +0000192
193 /* allocate and load VGA BIOS */
aurel32a748ab62008-12-20 23:40:35 +0000194 vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
pbrook44654492009-04-10 00:26:15 +0000195 vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
Paul Brook5cea8592009-05-30 00:52:44 +0100196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
197 if (filename) {
198 vga_bios_size = load_image(filename, vga_bios_ptr + 8);
199 qemu_free(filename);
200 } else {
201 vga_bios_size = -1;
202 }
j_mayer3cbee152007-10-28 23:42:18 +0000203 if (vga_bios_size < 0) {
204 /* if no bios is present, we can still work */
Paul Brook5cea8592009-05-30 00:52:44 +0100205 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
206 VGABIOS_FILENAME);
j_mayer3cbee152007-10-28 23:42:18 +0000207 vga_bios_size = 0;
208 } else {
209 /* set a specific header (XXX: find real Apple format for NDRV
210 drivers) */
pbrook44654492009-04-10 00:26:15 +0000211 vga_bios_ptr[0] = 'N';
212 vga_bios_ptr[1] = 'D';
213 vga_bios_ptr[2] = 'R';
214 vga_bios_ptr[3] = 'V';
215 cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
j_mayer3cbee152007-10-28 23:42:18 +0000216 vga_bios_size += 8;
Alexander Grafa7b022e2009-07-26 06:31:15 +0000217
218 /* Round to page boundary */
219 vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
220 TARGET_PAGE_MASK;
j_mayer3cbee152007-10-28 23:42:18 +0000221 }
j_mayer3cbee152007-10-28 23:42:18 +0000222
223 if (linux_boot) {
aurel3236bee1e2009-01-26 10:22:15 +0000224 uint64_t lowaddr = 0;
j_mayer3cbee152007-10-28 23:42:18 +0000225 kernel_base = KERNEL_LOAD_ADDR;
aurel3236bee1e2009-01-26 10:22:15 +0000226 /* Now we can load the kernel. The first step tries to load the kernel
227 supposing PhysAddr = 0x00000000. If that was wrong the kernel is
228 loaded again, the new PhysAddr being computed from lowaddr. */
229 kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
230 if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
231 kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
Blue Swirl660f11b2009-07-31 21:16:51 +0000232 NULL, NULL, NULL);
aurel3236bee1e2009-01-26 10:22:15 +0000233 }
blueswir152f163b2008-12-24 20:30:01 +0000234 if (kernel_size < 0)
235 kernel_size = load_aout(kernel_filename, kernel_base,
236 ram_size - kernel_base);
237 if (kernel_size < 0)
238 kernel_size = load_image_targphys(kernel_filename,
239 kernel_base,
240 ram_size - kernel_base);
j_mayer3cbee152007-10-28 23:42:18 +0000241 if (kernel_size < 0) {
Paul Brook2ac71172009-05-08 02:35:15 +0100242 hw_error("qemu: could not load kernel '%s'\n",
j_mayer3cbee152007-10-28 23:42:18 +0000243 kernel_filename);
244 exit(1);
245 }
246 /* load initrd */
247 if (initrd_filename) {
248 initrd_base = INITRD_LOAD_ADDR;
pbrookdcac9672009-04-09 20:05:49 +0000249 initrd_size = load_image_targphys(initrd_filename, initrd_base,
250 ram_size - initrd_base);
j_mayer3cbee152007-10-28 23:42:18 +0000251 if (initrd_size < 0) {
Paul Brook2ac71172009-05-08 02:35:15 +0100252 hw_error("qemu: could not load initial ram disk '%s'\n",
253 initrd_filename);
j_mayer3cbee152007-10-28 23:42:18 +0000254 exit(1);
255 }
256 } else {
257 initrd_base = 0;
258 initrd_size = 0;
259 }
balrog6ac0e822007-10-31 01:54:04 +0000260 ppc_boot_device = 'm';
j_mayer3cbee152007-10-28 23:42:18 +0000261 } else {
262 kernel_base = 0;
263 kernel_size = 0;
264 initrd_base = 0;
265 initrd_size = 0;
j_mayer28c5af52007-11-11 01:50:45 +0000266 ppc_boot_device = '\0';
j_mayer0d913fd2007-11-11 14:44:28 +0000267 for (i = 0; boot_device[i] != '\0'; i++) {
j_mayer28c5af52007-11-11 01:50:45 +0000268 /* TOFIX: for now, the second IDE channel is not properly
j_mayer0d913fd2007-11-11 14:44:28 +0000269 * used by OHW. The Mac floppy disk are not emulated.
j_mayer28c5af52007-11-11 01:50:45 +0000270 * For now, OHW cannot boot from the network.
271 */
272#if 0
j_mayer0d913fd2007-11-11 14:44:28 +0000273 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
274 ppc_boot_device = boot_device[i];
j_mayer28c5af52007-11-11 01:50:45 +0000275 break;
j_mayer0d913fd2007-11-11 14:44:28 +0000276 }
j_mayer28c5af52007-11-11 01:50:45 +0000277#else
j_mayer0d913fd2007-11-11 14:44:28 +0000278 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
279 ppc_boot_device = boot_device[i];
j_mayer28c5af52007-11-11 01:50:45 +0000280 break;
j_mayer0d913fd2007-11-11 14:44:28 +0000281 }
j_mayer28c5af52007-11-11 01:50:45 +0000282#endif
283 }
284 if (ppc_boot_device == '\0') {
aurel328a901de2009-01-13 19:07:59 +0000285 fprintf(stderr, "No valid boot device for G3 Beige machine\n");
j_mayer28c5af52007-11-11 01:50:45 +0000286 exit(1);
287 }
j_mayer3cbee152007-10-28 23:42:18 +0000288 }
289
290 isa_mem_base = 0x80000000;
j_mayeraae93662007-11-24 02:56:36 +0000291
j_mayer3cbee152007-10-28 23:42:18 +0000292 /* Register 2 MB of ISA IO space */
293 isa_mmio_init(0xfe000000, 0x00200000);
294
295 /* XXX: we register only 1 output pin for heathrow PIC */
296 heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
297 heathrow_irqs[0] =
298 qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
299 /* Connect the heathrow PIC outputs to the 6xx bus */
300 for (i = 0; i < smp_cpus; i++) {
301 switch (PPC_INPUT(env)) {
302 case PPC_FLAGS_INPUT_6xx:
303 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
304 heathrow_irqs[i][0] =
305 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
306 break;
307 default:
Paul Brook2ac71172009-05-08 02:35:15 +0100308 hw_error("Bus model not supported on OldWorld Mac machine\n");
j_mayer3cbee152007-10-28 23:42:18 +0000309 }
310 }
311
312 /* init basic PC hardware */
313 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
Paul Brook2ac71172009-05-08 02:35:15 +0100314 hw_error("Only 6xx bus is supported on heathrow machine\n");
j_mayer3cbee152007-10-28 23:42:18 +0000315 }
316 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
317 pci_bus = pci_grackle_init(0xfec00000, pic);
Paul Brookfbe1b592009-05-13 17:56:25 +0100318 pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
j_mayeraae93662007-11-24 02:56:36 +0000319
aurel32aeeb69c2009-01-14 14:47:56 +0000320 escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
blueswir17fa9ae12009-01-12 17:40:23 +0000321 serial_hds[1], ESCC_CLOCK, 4);
j_mayeraae93662007-11-24 02:56:36 +0000322
aliguoricb457d72009-01-13 19:47:10 +0000323 for(i = 0; i < nb_nics; i++)
Markus Armbruster5607c382009-06-18 15:14:08 +0200324 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
j_mayer0d913fd2007-11-11 14:44:28 +0000325
thse4bcb142007-12-02 04:51:10 +0000326
327 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
328 fprintf(stderr, "qemu: too many IDE bus\n");
329 exit(1);
330 }
aurel32bd4524e2009-03-07 21:35:21 +0000331
332 /* First IDE channel is a MAC IDE on the MacIO bus */
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200333 hd[0] = drive_get(IF_IDE, 0, 0);
334 hd[1] = drive_get(IF_IDE, 0, 1);
aurel32bd4524e2009-03-07 21:35:21 +0000335 dbdma = DBDMA_init(&dbdma_mem_index);
336 ide_mem_index[0] = -1;
337 ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
thse4bcb142007-12-02 04:51:10 +0000338
aurel32bd4524e2009-03-07 21:35:21 +0000339 /* Second IDE channel is a CMD646 on the PCI bus */
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200340 hd[0] = drive_get(IF_IDE, 1, 0);
341 hd[1] = drive_get(IF_IDE, 1, 1);
aurel32bd4524e2009-03-07 21:35:21 +0000342 hd[3] = hd[2] = NULL;
343 pci_cmd646_ide_init(pci_bus, hd, 0);
j_mayer3cbee152007-10-28 23:42:18 +0000344
345 /* cuda also initialize ADB */
346 cuda_init(&cuda_mem_index, pic[0x12]);
347
348 adb_kbd_init(&adb_bus);
349 adb_mouse_init(&adb_bus);
j_mayeraae93662007-11-24 02:56:36 +0000350
blueswir168af3f22009-02-07 10:48:26 +0000351 nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
j_mayer3cbee152007-10-28 23:42:18 +0000352 pmac_format_nvram_partition(nvr, 0x2000);
353
blueswir14ebcf882009-02-01 12:01:04 +0000354 macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
355 dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
356 escc_mem_index);
j_mayer3cbee152007-10-28 23:42:18 +0000357
358 if (usb_enabled) {
Gerd Hoffmann5b19d9a2009-08-31 14:24:03 +0200359 usb_ohci_init_pci(pci_bus, -1);
j_mayer3cbee152007-10-28 23:42:18 +0000360 }
361
362 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
363 graphic_depth = 15;
364
j_mayer3cbee152007-10-28 23:42:18 +0000365 /* No PCI init: the BIOS will do it */
366
blueswir1271dd5e2008-12-24 20:29:16 +0000367 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
368 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
369 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
370 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
blueswir1513f7892009-03-08 09:51:29 +0000371 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
372 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
373 if (kernel_cmdline) {
374 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
375 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
376 } else {
377 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
378 }
379 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
380 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
381 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
Laurent Vivier7f1aec52009-08-08 10:19:24 +0000382
383 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
384 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
385 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
386
blueswir1513f7892009-03-08 09:51:29 +0000387 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
j_mayer3cbee152007-10-28 23:42:18 +0000388}
389
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500390static QEMUMachine heathrow_machine = {
aurel324d7ca412009-01-07 23:38:59 +0000391 .name = "g3beige",
aliguori4b32e162008-10-07 20:34:35 +0000392 .desc = "Heathrow based PowerMAC",
393 .init = ppc_heathrow_init,
balrog3d878ca2008-10-28 10:59:59 +0000394 .max_cpus = MAX_CPUS,
Anthony Liguori0c257432009-05-21 20:41:01 -0500395 .is_default = 1,
j_mayer3cbee152007-10-28 23:42:18 +0000396};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500397
398static void heathrow_machine_init(void)
399{
400 qemu_register_machine(&heathrow_machine);
401}
402
403machine_init(heathrow_machine_init);