balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Nokia N-series internet tablets. |
| 3 | * |
| 4 | * Copyright (C) 2007 Nokia Corporation |
| 5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 or |
| 10 | * (at your option) version 3 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
aurel32 | fad6cb1 | 2009-01-04 22:05:52 +0000 | [diff] [blame] | 17 | * You should have received a copy of the GNU General Public License along |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include "qemu-common.h" |
| 22 | #include "sysemu.h" |
| 23 | #include "omap.h" |
| 24 | #include "arm-misc.h" |
| 25 | #include "irq.h" |
| 26 | #include "console.h" |
| 27 | #include "boards.h" |
| 28 | #include "i2c.h" |
| 29 | #include "devices.h" |
| 30 | #include "flash.h" |
| 31 | #include "hw.h" |
balrog | 1ae26a1 | 2008-09-28 23:19:47 +0000 | [diff] [blame] | 32 | #include "bt.h" |
Blue Swirl | ca20cf3 | 2009-09-20 14:58:02 +0000 | [diff] [blame] | 33 | #include "loader.h" |
Peter Maydell | af5a75f | 2011-07-29 16:35:25 +0100 | [diff] [blame] | 34 | #include "blockdev.h" |
Juha Riihimäki | 500954e | 2011-08-28 16:22:17 +0000 | [diff] [blame] | 35 | #include "sysbus.h" |
Avi Kivity | aee3950 | 2011-11-22 15:06:46 +0200 | [diff] [blame] | 36 | #include "exec-memory.h" |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 37 | |
| 38 | /* Nokia N8x0 support */ |
| 39 | struct n800_s { |
| 40 | struct omap_mpu_state_s *cpu; |
| 41 | |
| 42 | struct rfbi_chip_s blizzard; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 43 | struct { |
| 44 | void *opaque; |
| 45 | uint32_t (*txrx)(void *opaque, uint32_t value, int len); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 46 | uWireSlave *chip; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 47 | } ts; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 48 | i2c_bus *i2c; |
| 49 | |
| 50 | int keymap[0x80]; |
Peter Maydell | c4f05c8 | 2011-07-29 16:35:18 +0100 | [diff] [blame] | 51 | DeviceState *kbd; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 52 | |
Peter Maydell | bdc7646 | 2011-08-30 18:36:56 +0100 | [diff] [blame] | 53 | DeviceState *usb; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 54 | void *retu; |
| 55 | void *tahvo; |
Juha Riihimäki | 500954e | 2011-08-28 16:22:17 +0000 | [diff] [blame] | 56 | DeviceState *nand; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | /* GPIO pins */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 60 | #define N8X0_TUSB_ENABLE_GPIO 0 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 61 | #define N800_MMC2_WP_GPIO 8 |
| 62 | #define N800_UNKNOWN_GPIO0 9 /* out */ |
balrog | 0941041 | 2008-05-18 13:14:29 +0000 | [diff] [blame] | 63 | #define N810_MMC2_VIOSD_GPIO 9 |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 64 | #define N810_HEADSET_AMP_GPIO 10 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 65 | #define N800_CAM_TURN_GPIO 12 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 66 | #define N810_GPS_RESET_GPIO 12 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 67 | #define N800_BLIZZARD_POWERDOWN_GPIO 15 |
| 68 | #define N800_MMC1_WP_GPIO 23 |
balrog | 0941041 | 2008-05-18 13:14:29 +0000 | [diff] [blame] | 69 | #define N810_MMC2_VSD_GPIO 23 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 70 | #define N8X0_ONENAND_GPIO 26 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 71 | #define N810_BLIZZARD_RESET_GPIO 30 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 72 | #define N800_UNKNOWN_GPIO2 53 /* out */ |
| 73 | #define N8X0_TUSB_INT_GPIO 58 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 74 | #define N8X0_BT_WKUP_GPIO 61 |
| 75 | #define N8X0_STI_GPIO 62 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 76 | #define N8X0_CBUS_SEL_GPIO 64 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 77 | #define N8X0_CBUS_DAT_GPIO 65 |
| 78 | #define N8X0_CBUS_CLK_GPIO 66 |
| 79 | #define N8X0_WLAN_IRQ_GPIO 87 |
| 80 | #define N8X0_BT_RESET_GPIO 92 |
| 81 | #define N8X0_TEA5761_CS_GPIO 93 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 82 | #define N800_UNKNOWN_GPIO 94 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 83 | #define N810_TSC_RESET_GPIO 94 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 84 | #define N800_CAM_ACT_GPIO 95 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 85 | #define N810_GPS_WAKEUP_GPIO 95 |
| 86 | #define N8X0_MMC_CS_GPIO 96 |
| 87 | #define N8X0_WLAN_PWR_GPIO 97 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 88 | #define N8X0_BT_HOST_WKUP_GPIO 98 |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 89 | #define N810_SPEAKER_AMP_GPIO 101 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 90 | #define N810_KB_LOCK_GPIO 102 |
| 91 | #define N800_TSC_TS_GPIO 103 |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 92 | #define N810_TSC_TS_GPIO 106 |
| 93 | #define N8X0_HEADPHONE_GPIO 107 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 94 | #define N8X0_RETU_GPIO 108 |
| 95 | #define N800_TSC_KP_IRQ_GPIO 109 |
| 96 | #define N810_KEYBOARD_GPIO 109 |
| 97 | #define N800_BAT_COVER_GPIO 110 |
| 98 | #define N810_SLIDE_GPIO 110 |
| 99 | #define N8X0_TAHVO_GPIO 111 |
| 100 | #define N800_UNKNOWN_GPIO4 112 /* out */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 101 | #define N810_SLEEPX_LED_GPIO 112 |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 102 | #define N800_TSC_RESET_GPIO 118 /* ? */ |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 103 | #define N810_AIC33_RESET_GPIO 118 |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 104 | #define N800_TSC_UNKNOWN_GPIO 119 /* out */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 105 | #define N8X0_TMP105_GPIO 125 |
| 106 | |
| 107 | /* Config */ |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 108 | #define BT_UART 0 |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 109 | #define XLDR_LL_UART 1 |
| 110 | |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 111 | /* Addresses on the I2C bus 0 */ |
| 112 | #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ |
| 113 | #define N8X0_TCM825x_ADDR 0x29 /* Camera */ |
| 114 | #define N810_LP5521_ADDR 0x32 /* LEDs */ |
| 115 | #define N810_TSL2563_ADDR 0x3d /* Light sensor */ |
| 116 | #define N810_LM8323_ADDR 0x45 /* Keyboard */ |
| 117 | /* Addresses on the I2C bus 1 */ |
| 118 | #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ |
| 119 | #define N8X0_MENELAUS_ADDR 0x72 /* Power management */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 120 | |
| 121 | /* Chipselects on GPMC NOR interface */ |
| 122 | #define N8X0_ONENAND_CS 0 |
| 123 | #define N8X0_USB_ASYNC_CS 1 |
| 124 | #define N8X0_USB_SYNC_CS 4 |
| 125 | |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 126 | #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81 |
| 127 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 128 | static void n800_mmc_cs_cb(void *opaque, int line, int level) |
| 129 | { |
| 130 | /* TODO: this seems to actually be connected to the menelaus, to |
| 131 | * which also both MMC slots connect. */ |
| 132 | omap_mmc_enable((struct omap_mmc_s *) opaque, !level); |
| 133 | |
| 134 | printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1); |
| 135 | } |
| 136 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 137 | static void n8x0_gpio_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 138 | { |
| 139 | qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1); |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 140 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 141 | |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 142 | qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 143 | } |
| 144 | |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 145 | #define MAEMO_CAL_HEADER(...) \ |
| 146 | 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \ |
| 147 | __VA_ARGS__, \ |
| 148 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 149 | |
| 150 | static const uint8_t n8x0_cal_wlan_mac[] = { |
| 151 | MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c') |
| 152 | 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3, |
| 153 | 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00, |
| 154 | 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, |
| 155 | 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, |
| 156 | 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, |
| 157 | }; |
| 158 | |
| 159 | static const uint8_t n8x0_cal_bt_id[] = { |
| 160 | MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0) |
| 161 | 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96, |
| 162 | 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00, |
| 163 | N8X0_BD_ADDR, |
| 164 | }; |
| 165 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 166 | static void n8x0_nand_setup(struct n800_s *s) |
| 167 | { |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 168 | char *otp_region; |
Peter Maydell | af5a75f | 2011-07-29 16:35:25 +0100 | [diff] [blame] | 169 | DriveInfo *dinfo; |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 170 | |
Juha Riihimäki | 500954e | 2011-08-28 16:22:17 +0000 | [diff] [blame] | 171 | s->nand = qdev_create(NULL, "onenand"); |
| 172 | qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG); |
Juha Riihimäki | 5923ba4 | 2011-07-29 16:35:26 +0100 | [diff] [blame] | 173 | /* Either 0x40 or 0x48 are OK for the device ID */ |
Juha Riihimäki | 500954e | 2011-08-28 16:22:17 +0000 | [diff] [blame] | 174 | qdev_prop_set_uint16(s->nand, "device_id", 0x48); |
| 175 | qdev_prop_set_uint16(s->nand, "version_id", 0); |
| 176 | qdev_prop_set_int32(s->nand, "shift", 1); |
| 177 | dinfo = drive_get(IF_MTD, 0, 0); |
| 178 | if (dinfo && dinfo->bdrv) { |
| 179 | qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv); |
| 180 | } |
| 181 | qdev_init_nofail(s->nand); |
| 182 | sysbus_connect_irq(sysbus_from_qdev(s->nand), 0, |
| 183 | qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO)); |
| 184 | omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, |
Peter Maydell | 07bc2f8 | 2011-08-28 16:22:18 +0000 | [diff] [blame] | 185 | sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0)); |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 186 | otp_region = onenand_raw_otp(s->nand); |
| 187 | |
| 188 | memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); |
| 189 | memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id)); |
| 190 | /* XXX: in theory should also update the OOB for both pages */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 191 | } |
| 192 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 193 | static void n8x0_i2c_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 194 | { |
Paul Brook | 697454e | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 195 | DeviceState *dev; |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 196 | qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 197 | |
| 198 | /* Attach the CPU on one end of our I2C bus. */ |
| 199 | s->i2c = omap_i2c_bus(s->cpu->i2c[0]); |
| 200 | |
| 201 | /* Attach a menelaus PM chip */ |
Paul Brook | d335681 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 202 | dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR); |
Peter Maydell | 0919ac7 | 2011-09-23 09:44:38 +0000 | [diff] [blame] | 203 | qdev_connect_gpio_out(dev, 3, |
| 204 | qdev_get_gpio_in(s->cpu->ih[0], |
| 205 | OMAP_INT_24XX_SYS_NIRQ)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 206 | |
| 207 | /* Attach a TMP105 PM chip (A0 wired to ground) */ |
Paul Brook | 697454e | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 208 | dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR); |
| 209 | qdev_connect_gpio_out(dev, 0, tmp_irq); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* Touchscreen and keypad controller */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 213 | static MouseTransformInfo n800_pointercal = { |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 214 | .x = 800, |
| 215 | .y = 480, |
| 216 | .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, |
| 217 | }; |
| 218 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 219 | static MouseTransformInfo n810_pointercal = { |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 220 | .x = 800, |
| 221 | .y = 480, |
| 222 | .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, |
| 223 | }; |
| 224 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 225 | #define RETU_KEYCODE 61 /* F3 */ |
| 226 | |
| 227 | static void n800_key_event(void *opaque, int keycode) |
| 228 | { |
| 229 | struct n800_s *s = (struct n800_s *) opaque; |
| 230 | int code = s->keymap[keycode & 0x7f]; |
| 231 | |
| 232 | if (code == -1) { |
| 233 | if ((keycode & 0x7f) == RETU_KEYCODE) |
| 234 | retu_key_event(s->retu, !(keycode & 0x80)); |
| 235 | return; |
| 236 | } |
| 237 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 238 | tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | static const int n800_keys[16] = { |
| 242 | -1, |
| 243 | 72, /* Up */ |
| 244 | 63, /* Home (F5) */ |
| 245 | -1, |
| 246 | 75, /* Left */ |
| 247 | 28, /* Enter */ |
| 248 | 77, /* Right */ |
| 249 | -1, |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 250 | 1, /* Cycle (ESC) */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 251 | 80, /* Down */ |
| 252 | 62, /* Menu (F4) */ |
| 253 | -1, |
| 254 | 66, /* Zoom- (F8) */ |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 255 | 64, /* FullScreen (F6) */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 256 | 65, /* Zoom+ (F7) */ |
| 257 | -1, |
| 258 | }; |
| 259 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 260 | static void n800_tsc_kbd_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 261 | { |
| 262 | int i; |
| 263 | |
| 264 | /* XXX: are the three pins inverted inside the chip between the |
| 265 | * tsc and the cpu (N4111)? */ |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 266 | qemu_irq penirq = NULL; /* NC */ |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 267 | qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO); |
| 268 | qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 269 | |
Paul Brook | 22d83b1 | 2009-05-12 12:33:04 +0100 | [diff] [blame] | 270 | s->ts.chip = tsc2301_init(penirq, kbirq, dav); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 271 | s->ts.opaque = s->ts.chip->opaque; |
| 272 | s->ts.txrx = tsc210x_txrx; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 273 | |
| 274 | for (i = 0; i < 0x80; i ++) |
| 275 | s->keymap[i] = -1; |
| 276 | for (i = 0; i < 0x10; i ++) |
| 277 | if (n800_keys[i] >= 0) |
| 278 | s->keymap[n800_keys[i]] = i; |
| 279 | |
| 280 | qemu_add_kbd_event_handler(n800_key_event, s); |
| 281 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 282 | tsc210x_set_transform(s->ts.chip, &n800_pointercal); |
| 283 | } |
| 284 | |
| 285 | static void n810_tsc_setup(struct n800_s *s) |
| 286 | { |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 287 | qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 288 | |
| 289 | s->ts.opaque = tsc2005_init(pintdav); |
| 290 | s->ts.txrx = tsc2005_txrx; |
| 291 | |
| 292 | tsc2005_set_transform(s->ts.opaque, &n810_pointercal); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 293 | } |
| 294 | |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 295 | /* N810 Keyboard controller */ |
| 296 | static void n810_key_event(void *opaque, int keycode) |
| 297 | { |
| 298 | struct n800_s *s = (struct n800_s *) opaque; |
| 299 | int code = s->keymap[keycode & 0x7f]; |
| 300 | |
| 301 | if (code == -1) { |
| 302 | if ((keycode & 0x7f) == RETU_KEYCODE) |
| 303 | retu_key_event(s->retu, !(keycode & 0x80)); |
| 304 | return; |
| 305 | } |
| 306 | |
| 307 | lm832x_key_event(s->kbd, code, !(keycode & 0x80)); |
| 308 | } |
| 309 | |
| 310 | #define M 0 |
| 311 | |
| 312 | static int n810_keys[0x80] = { |
| 313 | [0x01] = 16, /* Q */ |
| 314 | [0x02] = 37, /* K */ |
| 315 | [0x03] = 24, /* O */ |
| 316 | [0x04] = 25, /* P */ |
| 317 | [0x05] = 14, /* Backspace */ |
| 318 | [0x06] = 30, /* A */ |
| 319 | [0x07] = 31, /* S */ |
| 320 | [0x08] = 32, /* D */ |
| 321 | [0x09] = 33, /* F */ |
| 322 | [0x0a] = 34, /* G */ |
| 323 | [0x0b] = 35, /* H */ |
| 324 | [0x0c] = 36, /* J */ |
| 325 | |
| 326 | [0x11] = 17, /* W */ |
| 327 | [0x12] = 62, /* Menu (F4) */ |
| 328 | [0x13] = 38, /* L */ |
| 329 | [0x14] = 40, /* ' (Apostrophe) */ |
| 330 | [0x16] = 44, /* Z */ |
| 331 | [0x17] = 45, /* X */ |
| 332 | [0x18] = 46, /* C */ |
| 333 | [0x19] = 47, /* V */ |
| 334 | [0x1a] = 48, /* B */ |
| 335 | [0x1b] = 49, /* N */ |
| 336 | [0x1c] = 42, /* Shift (Left shift) */ |
| 337 | [0x1f] = 65, /* Zoom+ (F7) */ |
| 338 | |
| 339 | [0x21] = 18, /* E */ |
| 340 | [0x22] = 39, /* ; (Semicolon) */ |
| 341 | [0x23] = 12, /* - (Minus) */ |
| 342 | [0x24] = 13, /* = (Equal) */ |
| 343 | [0x2b] = 56, /* Fn (Left Alt) */ |
| 344 | [0x2c] = 50, /* M */ |
| 345 | [0x2f] = 66, /* Zoom- (F8) */ |
| 346 | |
| 347 | [0x31] = 19, /* R */ |
| 348 | [0x32] = 29 | M, /* Right Ctrl */ |
| 349 | [0x34] = 57, /* Space */ |
| 350 | [0x35] = 51, /* , (Comma) */ |
| 351 | [0x37] = 72 | M, /* Up */ |
| 352 | [0x3c] = 82 | M, /* Compose (Insert) */ |
| 353 | [0x3f] = 64, /* FullScreen (F6) */ |
| 354 | |
| 355 | [0x41] = 20, /* T */ |
| 356 | [0x44] = 52, /* . (Dot) */ |
| 357 | [0x46] = 77 | M, /* Right */ |
| 358 | [0x4f] = 63, /* Home (F5) */ |
| 359 | [0x51] = 21, /* Y */ |
| 360 | [0x53] = 80 | M, /* Down */ |
| 361 | [0x55] = 28, /* Enter */ |
| 362 | [0x5f] = 1, /* Cycle (ESC) */ |
| 363 | |
| 364 | [0x61] = 22, /* U */ |
| 365 | [0x64] = 75 | M, /* Left */ |
| 366 | |
| 367 | [0x71] = 23, /* I */ |
| 368 | #if 0 |
| 369 | [0x75] = 28 | M, /* KP Enter (KP Enter) */ |
| 370 | #else |
| 371 | [0x75] = 15, /* KP Enter (Tab) */ |
| 372 | #endif |
| 373 | }; |
| 374 | |
| 375 | #undef M |
| 376 | |
| 377 | static void n810_kbd_setup(struct n800_s *s) |
| 378 | { |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 379 | qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO); |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 380 | int i; |
| 381 | |
| 382 | for (i = 0; i < 0x80; i ++) |
| 383 | s->keymap[i] = -1; |
| 384 | for (i = 0; i < 0x80; i ++) |
| 385 | if (n810_keys[i] > 0) |
| 386 | s->keymap[n810_keys[i]] = i; |
| 387 | |
| 388 | qemu_add_kbd_event_handler(n810_key_event, s); |
| 389 | |
| 390 | /* Attach the LM8322 keyboard to the I2C bus, |
| 391 | * should happen in n8x0_i2c_setup and s->kbd be initialised here. */ |
Peter Maydell | c4f05c8 | 2011-07-29 16:35:18 +0100 | [diff] [blame] | 392 | s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR); |
| 393 | qdev_connect_gpio_out(s->kbd, 0, kbd_irq); |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 394 | } |
| 395 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 396 | /* LCD MIPI DBI-C controller (URAL) */ |
| 397 | struct mipid_s { |
| 398 | int resp[4]; |
| 399 | int param[4]; |
| 400 | int p; |
| 401 | int pm; |
| 402 | int cmd; |
| 403 | |
| 404 | int sleep; |
| 405 | int booster; |
| 406 | int te; |
| 407 | int selfcheck; |
| 408 | int partial; |
| 409 | int normal; |
| 410 | int vscr; |
| 411 | int invert; |
| 412 | int onoff; |
| 413 | int gamma; |
| 414 | uint32_t id; |
| 415 | }; |
| 416 | |
| 417 | static void mipid_reset(struct mipid_s *s) |
| 418 | { |
| 419 | if (!s->sleep) |
| 420 | fprintf(stderr, "%s: Display off\n", __FUNCTION__); |
| 421 | |
| 422 | s->pm = 0; |
| 423 | s->cmd = 0; |
| 424 | |
| 425 | s->sleep = 1; |
| 426 | s->booster = 0; |
| 427 | s->selfcheck = |
| 428 | (1 << 7) | /* Register loading OK. */ |
| 429 | (1 << 5) | /* The chip is attached. */ |
| 430 | (1 << 4); /* Display glass still in one piece. */ |
| 431 | s->te = 0; |
| 432 | s->partial = 0; |
| 433 | s->normal = 1; |
| 434 | s->vscr = 0; |
| 435 | s->invert = 0; |
| 436 | s->onoff = 1; |
| 437 | s->gamma = 0; |
| 438 | } |
| 439 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 440 | static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 441 | { |
| 442 | struct mipid_s *s = (struct mipid_s *) opaque; |
| 443 | uint8_t ret; |
| 444 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 445 | if (len > 9) |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 446 | hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 447 | |
malc | b1503cd | 2008-12-22 20:33:55 +0000 | [diff] [blame] | 448 | if (s->p >= ARRAY_SIZE(s->resp)) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 449 | ret = 0; |
| 450 | else |
| 451 | ret = s->resp[s->p ++]; |
| 452 | if (s->pm --> 0) |
| 453 | s->param[s->pm] = cmd; |
| 454 | else |
| 455 | s->cmd = cmd; |
| 456 | |
| 457 | switch (s->cmd) { |
| 458 | case 0x00: /* NOP */ |
| 459 | break; |
| 460 | |
| 461 | case 0x01: /* SWRESET */ |
| 462 | mipid_reset(s); |
| 463 | break; |
| 464 | |
| 465 | case 0x02: /* BSTROFF */ |
| 466 | s->booster = 0; |
| 467 | break; |
| 468 | case 0x03: /* BSTRON */ |
| 469 | s->booster = 1; |
| 470 | break; |
| 471 | |
| 472 | case 0x04: /* RDDID */ |
| 473 | s->p = 0; |
| 474 | s->resp[0] = (s->id >> 16) & 0xff; |
| 475 | s->resp[1] = (s->id >> 8) & 0xff; |
| 476 | s->resp[2] = (s->id >> 0) & 0xff; |
| 477 | break; |
| 478 | |
| 479 | case 0x06: /* RD_RED */ |
| 480 | case 0x07: /* RD_GREEN */ |
| 481 | /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so |
| 482 | * for the bootloader one needs to change this. */ |
| 483 | case 0x08: /* RD_BLUE */ |
| 484 | s->p = 0; |
| 485 | /* TODO: return first pixel components */ |
| 486 | s->resp[0] = 0x01; |
| 487 | break; |
| 488 | |
| 489 | case 0x09: /* RDDST */ |
| 490 | s->p = 0; |
| 491 | s->resp[0] = s->booster << 7; |
| 492 | s->resp[1] = (5 << 4) | (s->partial << 2) | |
| 493 | (s->sleep << 1) | s->normal; |
| 494 | s->resp[2] = (s->vscr << 7) | (s->invert << 5) | |
| 495 | (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); |
| 496 | s->resp[3] = s->gamma << 6; |
| 497 | break; |
| 498 | |
| 499 | case 0x0a: /* RDDPM */ |
| 500 | s->p = 0; |
| 501 | s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | |
| 502 | (s->partial << 5) | (s->sleep << 6) | (s->booster << 7); |
| 503 | break; |
| 504 | case 0x0b: /* RDDMADCTR */ |
| 505 | s->p = 0; |
| 506 | s->resp[0] = 0; |
| 507 | break; |
| 508 | case 0x0c: /* RDDCOLMOD */ |
| 509 | s->p = 0; |
| 510 | s->resp[0] = 5; /* 65K colours */ |
| 511 | break; |
| 512 | case 0x0d: /* RDDIM */ |
| 513 | s->p = 0; |
| 514 | s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; |
| 515 | break; |
| 516 | case 0x0e: /* RDDSM */ |
| 517 | s->p = 0; |
| 518 | s->resp[0] = s->te << 7; |
| 519 | break; |
| 520 | case 0x0f: /* RDDSDR */ |
| 521 | s->p = 0; |
| 522 | s->resp[0] = s->selfcheck; |
| 523 | break; |
| 524 | |
| 525 | case 0x10: /* SLPIN */ |
| 526 | s->sleep = 1; |
| 527 | break; |
| 528 | case 0x11: /* SLPOUT */ |
| 529 | s->sleep = 0; |
| 530 | s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ |
| 531 | break; |
| 532 | |
| 533 | case 0x12: /* PTLON */ |
| 534 | s->partial = 1; |
| 535 | s->normal = 0; |
| 536 | s->vscr = 0; |
| 537 | break; |
| 538 | case 0x13: /* NORON */ |
| 539 | s->partial = 0; |
| 540 | s->normal = 1; |
| 541 | s->vscr = 0; |
| 542 | break; |
| 543 | |
| 544 | case 0x20: /* INVOFF */ |
| 545 | s->invert = 0; |
| 546 | break; |
| 547 | case 0x21: /* INVON */ |
| 548 | s->invert = 1; |
| 549 | break; |
| 550 | |
| 551 | case 0x22: /* APOFF */ |
| 552 | case 0x23: /* APON */ |
| 553 | goto bad_cmd; |
| 554 | |
| 555 | case 0x25: /* WRCNTR */ |
| 556 | if (s->pm < 0) |
| 557 | s->pm = 1; |
| 558 | goto bad_cmd; |
| 559 | |
| 560 | case 0x26: /* GAMSET */ |
| 561 | if (!s->pm) |
| 562 | s->gamma = ffs(s->param[0] & 0xf) - 1; |
| 563 | else if (s->pm < 0) |
| 564 | s->pm = 1; |
| 565 | break; |
| 566 | |
| 567 | case 0x28: /* DISPOFF */ |
| 568 | s->onoff = 0; |
| 569 | fprintf(stderr, "%s: Display off\n", __FUNCTION__); |
| 570 | break; |
| 571 | case 0x29: /* DISPON */ |
| 572 | s->onoff = 1; |
| 573 | fprintf(stderr, "%s: Display on\n", __FUNCTION__); |
| 574 | break; |
| 575 | |
| 576 | case 0x2a: /* CASET */ |
| 577 | case 0x2b: /* RASET */ |
| 578 | case 0x2c: /* RAMWR */ |
| 579 | case 0x2d: /* RGBSET */ |
| 580 | case 0x2e: /* RAMRD */ |
| 581 | case 0x30: /* PTLAR */ |
| 582 | case 0x33: /* SCRLAR */ |
| 583 | goto bad_cmd; |
| 584 | |
| 585 | case 0x34: /* TEOFF */ |
| 586 | s->te = 0; |
| 587 | break; |
| 588 | case 0x35: /* TEON */ |
| 589 | if (!s->pm) |
| 590 | s->te = 1; |
| 591 | else if (s->pm < 0) |
| 592 | s->pm = 1; |
| 593 | break; |
| 594 | |
| 595 | case 0x36: /* MADCTR */ |
| 596 | goto bad_cmd; |
| 597 | |
| 598 | case 0x37: /* VSCSAD */ |
| 599 | s->partial = 0; |
| 600 | s->normal = 0; |
| 601 | s->vscr = 1; |
| 602 | break; |
| 603 | |
| 604 | case 0x38: /* IDMOFF */ |
| 605 | case 0x39: /* IDMON */ |
| 606 | case 0x3a: /* COLMOD */ |
| 607 | goto bad_cmd; |
| 608 | |
| 609 | case 0xb0: /* CLKINT / DISCTL */ |
| 610 | case 0xb1: /* CLKEXT */ |
| 611 | if (s->pm < 0) |
| 612 | s->pm = 2; |
| 613 | break; |
| 614 | |
| 615 | case 0xb4: /* FRMSEL */ |
| 616 | break; |
| 617 | |
| 618 | case 0xb5: /* FRM8SEL */ |
| 619 | case 0xb6: /* TMPRNG / INIESC */ |
| 620 | case 0xb7: /* TMPHIS / NOP2 */ |
| 621 | case 0xb8: /* TMPREAD / MADCTL */ |
| 622 | case 0xba: /* DISTCTR */ |
| 623 | case 0xbb: /* EPVOL */ |
| 624 | goto bad_cmd; |
| 625 | |
| 626 | case 0xbd: /* Unknown */ |
| 627 | s->p = 0; |
| 628 | s->resp[0] = 0; |
| 629 | s->resp[1] = 1; |
| 630 | break; |
| 631 | |
| 632 | case 0xc2: /* IFMOD */ |
| 633 | if (s->pm < 0) |
| 634 | s->pm = 2; |
| 635 | break; |
| 636 | |
| 637 | case 0xc6: /* PWRCTL */ |
| 638 | case 0xc7: /* PPWRCTL */ |
| 639 | case 0xd0: /* EPWROUT */ |
| 640 | case 0xd1: /* EPWRIN */ |
| 641 | case 0xd4: /* RDEV */ |
| 642 | case 0xd5: /* RDRR */ |
| 643 | goto bad_cmd; |
| 644 | |
| 645 | case 0xda: /* RDID1 */ |
| 646 | s->p = 0; |
| 647 | s->resp[0] = (s->id >> 16) & 0xff; |
| 648 | break; |
| 649 | case 0xdb: /* RDID2 */ |
| 650 | s->p = 0; |
| 651 | s->resp[0] = (s->id >> 8) & 0xff; |
| 652 | break; |
| 653 | case 0xdc: /* RDID3 */ |
| 654 | s->p = 0; |
| 655 | s->resp[0] = (s->id >> 0) & 0xff; |
| 656 | break; |
| 657 | |
| 658 | default: |
| 659 | bad_cmd: |
| 660 | fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd); |
| 661 | break; |
| 662 | } |
| 663 | |
| 664 | return ret; |
| 665 | } |
| 666 | |
| 667 | static void *mipid_init(void) |
| 668 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 669 | struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 670 | |
| 671 | s->id = 0x838f03; |
| 672 | mipid_reset(s); |
| 673 | |
| 674 | return s; |
| 675 | } |
| 676 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 677 | static void n8x0_spi_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 678 | { |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 679 | void *tsc = s->ts.opaque; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 680 | void *mipid = mipid_init(); |
| 681 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 682 | omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 683 | omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1); |
| 684 | } |
| 685 | |
| 686 | /* This task is normally performed by the bootloader. If we're loading |
| 687 | * a kernel directly, we need to enable the Blizzard ourselves. */ |
| 688 | static void n800_dss_init(struct rfbi_chip_s *chip) |
| 689 | { |
| 690 | uint8_t *fb_blank; |
| 691 | |
| 692 | chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ |
| 693 | chip->write(chip->opaque, 1, 0x64); |
| 694 | chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ |
| 695 | chip->write(chip->opaque, 1, 0x1e); |
| 696 | chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ |
| 697 | chip->write(chip->opaque, 1, 0xe0); |
| 698 | chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ |
| 699 | chip->write(chip->opaque, 1, 0x01); |
| 700 | chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ |
| 701 | chip->write(chip->opaque, 1, 0x06); |
| 702 | chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ |
| 703 | chip->write(chip->opaque, 1, 1); /* Enable bit */ |
| 704 | |
| 705 | chip->write(chip->opaque, 0, 0x6c); |
| 706 | chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
| 707 | chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
| 708 | chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
| 709 | chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
| 710 | chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ |
| 711 | chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ |
| 712 | chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ |
| 713 | chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ |
| 714 | chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
| 715 | chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
| 716 | chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
| 717 | chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
| 718 | chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ |
| 719 | chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ |
| 720 | chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ |
| 721 | chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ |
| 722 | chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ |
| 723 | chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ |
| 724 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 725 | fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 726 | /* Display Memory Data Port */ |
| 727 | chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 728 | g_free(fb_blank); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 729 | } |
| 730 | |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 731 | static void n8x0_dss_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 732 | { |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 733 | s->blizzard.opaque = s1d13745_init(NULL); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 734 | s->blizzard.block = s1d13745_write_block; |
| 735 | s->blizzard.write = s1d13745_write; |
| 736 | s->blizzard.read = s1d13745_read; |
| 737 | |
| 738 | omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard); |
| 739 | } |
| 740 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 741 | static void n8x0_cbus_setup(struct n800_s *s) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 742 | { |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 743 | qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO); |
| 744 | qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO); |
| 745 | qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 746 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 747 | CBus *cbus = cbus_init(dat_out); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 748 | |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 749 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk); |
| 750 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat); |
| 751 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 752 | |
| 753 | cbus_attach(cbus, s->retu = retu_init(retu_irq, 1)); |
| 754 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); |
| 755 | } |
| 756 | |
balrog | 58a26b4 | 2008-09-28 23:34:13 +0000 | [diff] [blame] | 757 | static void n8x0_uart_setup(struct n800_s *s) |
| 758 | { |
| 759 | CharDriverState *radio = uart_hci_init( |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 760 | qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO)); |
balrog | 58a26b4 | 2008-09-28 23:34:13 +0000 | [diff] [blame] | 761 | |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 762 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO, |
balrog | 58a26b4 | 2008-09-28 23:34:13 +0000 | [diff] [blame] | 763 | csrhci_pins_get(radio)[csrhci_pin_reset]); |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 764 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO, |
balrog | 58a26b4 | 2008-09-28 23:34:13 +0000 | [diff] [blame] | 765 | csrhci_pins_get(radio)[csrhci_pin_wakeup]); |
| 766 | |
| 767 | omap_uart_attach(s->cpu->uart[BT_UART], radio); |
| 768 | } |
| 769 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 770 | static void n8x0_usb_setup(struct n800_s *s) |
balrog | 942ac05 | 2008-04-22 03:15:10 +0000 | [diff] [blame] | 771 | { |
Peter Maydell | bdc7646 | 2011-08-30 18:36:56 +0100 | [diff] [blame] | 772 | SysBusDevice *dev; |
| 773 | s->usb = qdev_create(NULL, "tusb6010"); |
| 774 | dev = sysbus_from_qdev(s->usb); |
| 775 | qdev_init_nofail(s->usb); |
| 776 | sysbus_connect_irq(dev, 0, |
| 777 | qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO)); |
balrog | 942ac05 | 2008-04-22 03:15:10 +0000 | [diff] [blame] | 778 | /* Using the NOR interface */ |
Peter Maydell | bdc7646 | 2011-08-30 18:36:56 +0100 | [diff] [blame] | 779 | omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, |
| 780 | sysbus_mmio_get_region(dev, 0)); |
| 781 | omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, |
| 782 | sysbus_mmio_get_region(dev, 1)); |
| 783 | qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, |
| 784 | qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */ |
balrog | 942ac05 | 2008-04-22 03:15:10 +0000 | [diff] [blame] | 785 | } |
| 786 | |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 787 | /* Setup done before the main bootloader starts by some early setup code |
| 788 | * - used when we want to run the main bootloader in emulation. This |
| 789 | * isn't documented. */ |
| 790 | static uint32_t n800_pinout[104] = { |
| 791 | 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, |
| 792 | 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, |
| 793 | 0x08080808, 0x180800c4, 0x00b80000, 0x08080808, |
| 794 | 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, |
| 795 | 0x01241800, 0x18181818, 0x000000f0, 0x01300000, |
| 796 | 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, |
| 797 | 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, |
| 798 | 0x007c0000, 0x00000000, 0x00000088, 0x00840000, |
| 799 | 0x00000000, 0x00000094, 0x00980300, 0x0f180003, |
| 800 | 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, |
| 801 | 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, |
| 802 | 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, |
| 803 | 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, |
| 804 | 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, |
| 805 | 0x00000000, 0x00000038, 0x00340000, 0x00000000, |
| 806 | 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, |
| 807 | 0x005c0808, 0x08080808, 0x08080058, 0x00540808, |
| 808 | 0x08080808, 0x0808006c, 0x00680808, 0x08080808, |
| 809 | 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, |
| 810 | 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, |
| 811 | 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, |
| 812 | 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, |
| 813 | 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, |
| 814 | 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, |
| 815 | 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, |
| 816 | 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, |
| 817 | }; |
| 818 | |
| 819 | static void n800_setup_nolo_tags(void *sram_base) |
| 820 | { |
| 821 | int i; |
| 822 | uint32_t *p = sram_base + 0x8000; |
| 823 | uint32_t *v = sram_base + 0xa000; |
| 824 | |
| 825 | memset(p, 0, 0x3000); |
| 826 | |
| 827 | strcpy((void *) (p + 0), "QEMU N800"); |
| 828 | |
| 829 | strcpy((void *) (p + 8), "F5"); |
| 830 | |
| 831 | stl_raw(p + 10, 0x04f70000); |
| 832 | strcpy((void *) (p + 9), "RX-34"); |
| 833 | |
| 834 | /* RAM size in MB? */ |
| 835 | stl_raw(p + 12, 0x80); |
| 836 | |
| 837 | /* Pointer to the list of tags */ |
| 838 | stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000); |
| 839 | |
| 840 | /* The NOLO tags start here */ |
| 841 | p = sram_base + 0x9000; |
| 842 | #define ADD_TAG(tag, len) \ |
| 843 | stw_raw((uint16_t *) p + 0, tag); \ |
| 844 | stw_raw((uint16_t *) p + 1, len); p ++; \ |
| 845 | stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); |
| 846 | |
| 847 | /* OMAP STI console? Pin out settings? */ |
| 848 | ADD_TAG(0x6e01, 414); |
malc | b1503cd | 2008-12-22 20:33:55 +0000 | [diff] [blame] | 849 | for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++) |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 850 | stl_raw(v ++, n800_pinout[i]); |
| 851 | |
| 852 | /* Kernel memsize? */ |
| 853 | ADD_TAG(0x6e05, 1); |
| 854 | stl_raw(v ++, 2); |
| 855 | |
| 856 | /* NOLO serial console */ |
| 857 | ADD_TAG(0x6e02, 4); |
| 858 | stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */ |
| 859 | |
| 860 | #if 0 |
| 861 | /* CBUS settings (Retu/AVilma) */ |
| 862 | ADD_TAG(0x6e03, 6); |
| 863 | stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */ |
| 864 | stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */ |
| 865 | stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */ |
| 866 | v += 2; |
| 867 | #endif |
| 868 | |
| 869 | /* Nokia ASIC BB5 (Retu/Tahvo) */ |
| 870 | ADD_TAG(0x6e0a, 4); |
| 871 | stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ |
| 872 | stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ |
| 873 | v ++; |
| 874 | |
| 875 | /* LCD console? */ |
| 876 | ADD_TAG(0x6e04, 4); |
| 877 | stw_raw((uint16_t *) v + 0, 30); /* ??? */ |
| 878 | stw_raw((uint16_t *) v + 1, 24); /* ??? */ |
| 879 | v ++; |
| 880 | |
| 881 | #if 0 |
| 882 | /* LCD settings */ |
| 883 | ADD_TAG(0x6e06, 2); |
| 884 | stw_raw((uint16_t *) (v ++), 15); /* ??? */ |
| 885 | #endif |
| 886 | |
| 887 | /* I^2C (Menelaus) */ |
| 888 | ADD_TAG(0x6e07, 4); |
| 889 | stl_raw(v ++, 0x00720000); /* ??? */ |
| 890 | |
| 891 | /* Unknown */ |
| 892 | ADD_TAG(0x6e0b, 6); |
| 893 | stw_raw((uint16_t *) v + 0, 94); /* ??? */ |
| 894 | stw_raw((uint16_t *) v + 1, 23); /* ??? */ |
| 895 | stw_raw((uint16_t *) v + 2, 0); /* ??? */ |
| 896 | v += 2; |
| 897 | |
| 898 | /* OMAP gpio switch info */ |
| 899 | ADD_TAG(0x6e0c, 80); |
| 900 | strcpy((void *) v, "bat_cover"); v += 3; |
| 901 | stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */ |
| 902 | stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */ |
| 903 | v += 2; |
| 904 | strcpy((void *) v, "cam_act"); v += 3; |
| 905 | stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */ |
| 906 | stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */ |
| 907 | v += 2; |
| 908 | strcpy((void *) v, "cam_turn"); v += 3; |
| 909 | stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */ |
| 910 | stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */ |
| 911 | v += 2; |
| 912 | strcpy((void *) v, "headphone"); v += 3; |
| 913 | stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */ |
| 914 | stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */ |
| 915 | v += 2; |
| 916 | |
| 917 | /* Bluetooth */ |
| 918 | ADD_TAG(0x6e0e, 12); |
| 919 | stl_raw(v ++, 0x5c623d01); /* ??? */ |
| 920 | stl_raw(v ++, 0x00000201); /* ??? */ |
| 921 | stl_raw(v ++, 0x00000000); /* ??? */ |
| 922 | |
| 923 | /* CX3110x WLAN settings */ |
| 924 | ADD_TAG(0x6e0f, 8); |
| 925 | stl_raw(v ++, 0x00610025); /* ??? */ |
| 926 | stl_raw(v ++, 0xffff0057); /* ??? */ |
| 927 | |
| 928 | /* MMC host settings */ |
| 929 | ADD_TAG(0x6e10, 12); |
| 930 | stl_raw(v ++, 0xffff000f); /* ??? */ |
| 931 | stl_raw(v ++, 0xffffffff); /* ??? */ |
| 932 | stl_raw(v ++, 0x00000060); /* ??? */ |
| 933 | |
| 934 | /* OneNAND chip select */ |
| 935 | ADD_TAG(0x6e11, 10); |
| 936 | stl_raw(v ++, 0x00000401); /* ??? */ |
| 937 | stl_raw(v ++, 0x0002003a); /* ??? */ |
| 938 | stl_raw(v ++, 0x00000002); /* ??? */ |
| 939 | |
| 940 | /* TEA5761 sensor settings */ |
| 941 | ADD_TAG(0x6e12, 2); |
| 942 | stl_raw(v ++, 93); /* GPIO num ??? */ |
| 943 | |
| 944 | #if 0 |
| 945 | /* Unknown tag */ |
| 946 | ADD_TAG(6e09, 0); |
| 947 | |
| 948 | /* Kernel UART / console */ |
| 949 | ADD_TAG(6e12, 0); |
| 950 | #endif |
| 951 | |
| 952 | /* End of the list */ |
| 953 | stl_raw(p ++, 0x00000000); |
| 954 | stl_raw(p ++, 0x00000000); |
| 955 | } |
| 956 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 957 | /* This task is normally performed by the bootloader. If we're loading |
| 958 | * a kernel directly, we need to set up GPMC mappings ourselves. */ |
| 959 | static void n800_gpmc_init(struct n800_s *s) |
| 960 | { |
| 961 | uint32_t config7 = |
| 962 | (0xf << 8) | /* MASKADDRESS */ |
| 963 | (1 << 6) | /* CSVALID */ |
| 964 | (4 << 0); /* BASEADDRESS */ |
| 965 | |
| 966 | cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ |
| 967 | (void *) &config7, sizeof(config7)); |
| 968 | } |
| 969 | |
| 970 | /* Setup sequence done by the bootloader */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 971 | static void n8x0_boot_init(void *opaque) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 972 | { |
| 973 | struct n800_s *s = (struct n800_s *) opaque; |
| 974 | uint32_t buf; |
| 975 | |
| 976 | /* PRCM setup */ |
| 977 | #define omap_writel(addr, val) \ |
| 978 | buf = (val); \ |
| 979 | cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf)) |
| 980 | |
| 981 | omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ |
| 982 | omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ |
| 983 | omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ |
| 984 | omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ |
| 985 | omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ |
| 986 | omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ |
| 987 | omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ |
| 988 | omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ |
| 989 | omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ |
| 990 | omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ |
| 991 | omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ |
| 992 | omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ |
| 993 | omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ |
| 994 | omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ |
| 995 | omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ |
| 996 | omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ |
| 997 | omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ |
| 998 | omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ |
| 999 | omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ |
| 1000 | omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ |
| 1001 | omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ |
| 1002 | omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ |
| 1003 | omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ |
| 1004 | omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ |
| 1005 | omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ |
| 1006 | omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ |
| 1007 | omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ |
| 1008 | omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ |
| 1009 | omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ |
| 1010 | omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ |
| 1011 | omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ |
| 1012 | omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ |
| 1013 | omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ |
| 1014 | omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ |
| 1015 | omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ |
| 1016 | (0x78 << 12) | (6 << 8)); |
| 1017 | omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ |
| 1018 | |
| 1019 | /* GPMC setup */ |
| 1020 | n800_gpmc_init(s); |
| 1021 | |
| 1022 | /* Video setup */ |
| 1023 | n800_dss_init(&s->blizzard); |
| 1024 | |
| 1025 | /* CPU setup */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1026 | s->cpu->env->GE = 0x5; |
balrog | 0941041 | 2008-05-18 13:14:29 +0000 | [diff] [blame] | 1027 | |
| 1028 | /* If the machine has a slided keyboard, open it */ |
| 1029 | if (s->kbd) |
Juha Riihimäki | 77831c2 | 2011-07-29 16:35:17 +0100 | [diff] [blame] | 1030 | qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1031 | } |
| 1032 | |
| 1033 | #define OMAP_TAG_NOKIA_BT 0x4e01 |
| 1034 | #define OMAP_TAG_WLAN_CX3110X 0x4e02 |
| 1035 | #define OMAP_TAG_CBUS 0x4e03 |
| 1036 | #define OMAP_TAG_EM_ASIC_BB5 0x4e04 |
| 1037 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1038 | static struct omap_gpiosw_info_s { |
| 1039 | const char *name; |
| 1040 | int line; |
| 1041 | int type; |
| 1042 | } n800_gpiosw_info[] = { |
| 1043 | { |
| 1044 | "bat_cover", N800_BAT_COVER_GPIO, |
| 1045 | OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 1046 | }, { |
| 1047 | "cam_act", N800_CAM_ACT_GPIO, |
| 1048 | OMAP_GPIOSW_TYPE_ACTIVITY, |
| 1049 | }, { |
| 1050 | "cam_turn", N800_CAM_TURN_GPIO, |
| 1051 | OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, |
| 1052 | }, { |
| 1053 | "headphone", N8X0_HEADPHONE_GPIO, |
| 1054 | OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
| 1055 | }, |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 1056 | { NULL } |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1057 | }, n810_gpiosw_info[] = { |
| 1058 | { |
| 1059 | "gps_reset", N810_GPS_RESET_GPIO, |
| 1060 | OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
| 1061 | }, { |
| 1062 | "gps_wakeup", N810_GPS_WAKEUP_GPIO, |
| 1063 | OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
| 1064 | }, { |
| 1065 | "headphone", N8X0_HEADPHONE_GPIO, |
| 1066 | OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
| 1067 | }, { |
| 1068 | "kb_lock", N810_KB_LOCK_GPIO, |
| 1069 | OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 1070 | }, { |
| 1071 | "sleepx_led", N810_SLEEPX_LED_GPIO, |
| 1072 | OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, |
| 1073 | }, { |
| 1074 | "slide", N810_SLIDE_GPIO, |
| 1075 | OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
| 1076 | }, |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 1077 | { NULL } |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1078 | }; |
| 1079 | |
| 1080 | static struct omap_partition_info_s { |
| 1081 | uint32_t offset; |
| 1082 | uint32_t size; |
| 1083 | int mask; |
| 1084 | const char *name; |
| 1085 | } n800_part_info[] = { |
| 1086 | { 0x00000000, 0x00020000, 0x3, "bootloader" }, |
| 1087 | { 0x00020000, 0x00060000, 0x0, "config" }, |
| 1088 | { 0x00080000, 0x00200000, 0x0, "kernel" }, |
| 1089 | { 0x00280000, 0x00200000, 0x3, "initfs" }, |
| 1090 | { 0x00480000, 0x0fb80000, 0x3, "rootfs" }, |
| 1091 | |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 1092 | { 0, 0, 0, NULL } |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1093 | }, n810_part_info[] = { |
| 1094 | { 0x00000000, 0x00020000, 0x3, "bootloader" }, |
| 1095 | { 0x00020000, 0x00060000, 0x0, "config" }, |
| 1096 | { 0x00080000, 0x00220000, 0x0, "kernel" }, |
| 1097 | { 0x002a0000, 0x00400000, 0x0, "initfs" }, |
| 1098 | { 0x006a0000, 0x0f960000, 0x0, "rootfs" }, |
| 1099 | |
Blue Swirl | b9d38e9 | 2009-09-21 18:11:34 +0000 | [diff] [blame] | 1100 | { 0, 0, 0, NULL } |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1101 | }; |
| 1102 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1103 | static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }}; |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 1104 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1105 | static int n8x0_atag_setup(void *p, int model) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1106 | { |
| 1107 | uint8_t *b; |
| 1108 | uint16_t *w; |
| 1109 | uint32_t *l; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1110 | struct omap_gpiosw_info_s *gpiosw; |
| 1111 | struct omap_partition_info_s *partition; |
| 1112 | const char *tag; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1113 | |
| 1114 | w = p; |
| 1115 | |
| 1116 | stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */ |
| 1117 | stw_raw(w ++, 4); /* u16 len */ |
| 1118 | stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ |
| 1119 | w ++; |
| 1120 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1121 | #if 0 |
| 1122 | stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1123 | stw_raw(w ++, 4); /* u16 len */ |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 1124 | stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1125 | stw_raw(w ++, 115200); /* u32 console_speed */ |
| 1126 | #endif |
| 1127 | |
| 1128 | stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */ |
| 1129 | stw_raw(w ++, 36); /* u16 len */ |
| 1130 | strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ |
| 1131 | w += 8; |
| 1132 | strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ |
| 1133 | w += 8; |
| 1134 | stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */ |
| 1135 | stw_raw(w ++, 24); /* u8 data_lines */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1136 | |
| 1137 | stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */ |
| 1138 | stw_raw(w ++, 8); /* u16 len */ |
| 1139 | stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */ |
| 1140 | stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */ |
| 1141 | stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */ |
| 1142 | w ++; |
| 1143 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1144 | stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */ |
| 1145 | stw_raw(w ++, 4); /* u16 len */ |
| 1146 | stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */ |
| 1147 | stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1148 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1149 | gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info; |
| 1150 | for (; gpiosw->name; gpiosw ++) { |
| 1151 | stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */ |
| 1152 | stw_raw(w ++, 20); /* u16 len */ |
| 1153 | strcpy((void *) w, gpiosw->name); /* char name[12] */ |
| 1154 | w += 6; |
| 1155 | stw_raw(w ++, gpiosw->line); /* u16 gpio */ |
| 1156 | stw_raw(w ++, gpiosw->type); |
| 1157 | stw_raw(w ++, 0); |
| 1158 | stw_raw(w ++, 0); |
| 1159 | } |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1160 | |
| 1161 | stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */ |
| 1162 | stw_raw(w ++, 12); /* u16 len */ |
| 1163 | b = (void *) w; |
| 1164 | stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1165 | stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1166 | stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1167 | stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */ |
balrog | c580d92 | 2008-07-29 14:19:16 +0000 | [diff] [blame] | 1168 | stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */ |
| 1169 | memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1170 | b += 6; |
| 1171 | stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */ |
| 1172 | w = (void *) b; |
| 1173 | |
| 1174 | stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */ |
| 1175 | stw_raw(w ++, 8); /* u16 len */ |
| 1176 | stw_raw(w ++, 0x25); /* u8 chip_type */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1177 | stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */ |
| 1178 | stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1179 | stw_raw(w ++, -1); /* s16 spi_cs_gpio */ |
| 1180 | |
| 1181 | stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */ |
| 1182 | stw_raw(w ++, 16); /* u16 len */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1183 | if (model == 810) { |
| 1184 | stw_raw(w ++, 0x23f); /* unsigned flags */ |
| 1185 | stw_raw(w ++, -1); /* s16 power_pin */ |
| 1186 | stw_raw(w ++, -1); /* s16 switch_pin */ |
| 1187 | stw_raw(w ++, -1); /* s16 wp_pin */ |
| 1188 | stw_raw(w ++, 0x240); /* unsigned flags */ |
| 1189 | stw_raw(w ++, 0xc000); /* s16 power_pin */ |
| 1190 | stw_raw(w ++, 0x0248); /* s16 switch_pin */ |
| 1191 | stw_raw(w ++, 0xc000); /* s16 wp_pin */ |
| 1192 | } else { |
| 1193 | stw_raw(w ++, 0xf); /* unsigned flags */ |
| 1194 | stw_raw(w ++, -1); /* s16 power_pin */ |
| 1195 | stw_raw(w ++, -1); /* s16 switch_pin */ |
| 1196 | stw_raw(w ++, -1); /* s16 wp_pin */ |
| 1197 | stw_raw(w ++, 0); /* unsigned flags */ |
| 1198 | stw_raw(w ++, 0); /* s16 power_pin */ |
| 1199 | stw_raw(w ++, 0); /* s16 switch_pin */ |
| 1200 | stw_raw(w ++, 0); /* s16 wp_pin */ |
| 1201 | } |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1202 | |
| 1203 | stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */ |
| 1204 | stw_raw(w ++, 4); /* u16 len */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1205 | stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1206 | w ++; |
| 1207 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1208 | partition = (model == 810) ? n810_part_info : n800_part_info; |
| 1209 | for (; partition->name; partition ++) { |
| 1210 | stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */ |
| 1211 | stw_raw(w ++, 28); /* u16 len */ |
| 1212 | strcpy((void *) w, partition->name); /* char name[16] */ |
| 1213 | l = (void *) (w + 8); |
| 1214 | stl_raw(l ++, partition->size); /* unsigned int size */ |
| 1215 | stl_raw(l ++, partition->offset); /* unsigned int offset */ |
| 1216 | stl_raw(l ++, partition->mask); /* unsigned int mask_flags */ |
| 1217 | w = (void *) l; |
| 1218 | } |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1219 | |
| 1220 | stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */ |
| 1221 | stw_raw(w ++, 12); /* u16 len */ |
| 1222 | #if 0 |
| 1223 | strcpy((void *) w, "por"); /* char reason_str[12] */ |
| 1224 | strcpy((void *) w, "charger"); /* char reason_str[12] */ |
| 1225 | strcpy((void *) w, "32wd_to"); /* char reason_str[12] */ |
| 1226 | strcpy((void *) w, "sw_rst"); /* char reason_str[12] */ |
| 1227 | strcpy((void *) w, "mbus"); /* char reason_str[12] */ |
| 1228 | strcpy((void *) w, "unknown"); /* char reason_str[12] */ |
| 1229 | strcpy((void *) w, "swdg_to"); /* char reason_str[12] */ |
| 1230 | strcpy((void *) w, "sec_vio"); /* char reason_str[12] */ |
| 1231 | strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
| 1232 | strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */ |
| 1233 | #else |
| 1234 | strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
| 1235 | #endif |
| 1236 | w += 6; |
| 1237 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1238 | tag = (model == 810) ? "RX-44" : "RX-34"; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1239 | stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
| 1240 | stw_raw(w ++, 24); /* u16 len */ |
| 1241 | strcpy((void *) w, "product"); /* char component[12] */ |
| 1242 | w += 6; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1243 | strcpy((void *) w, tag); /* char version[12] */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1244 | w += 6; |
| 1245 | |
| 1246 | stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
| 1247 | stw_raw(w ++, 24); /* u16 len */ |
| 1248 | strcpy((void *) w, "hw-build"); /* char component[12] */ |
| 1249 | w += 6; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1250 | strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1251 | w += 6; |
| 1252 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1253 | tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1254 | stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
| 1255 | stw_raw(w ++, 24); /* u16 len */ |
| 1256 | strcpy((void *) w, "nolo"); /* char component[12] */ |
| 1257 | w += 6; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1258 | strcpy((void *) w, tag); /* char version[12] */ |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1259 | w += 6; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1260 | |
| 1261 | return (void *) w - p; |
| 1262 | } |
| 1263 | |
Stefan Weil | 462a8bc | 2011-06-23 17:53:48 +0200 | [diff] [blame] | 1264 | static int n800_atag_setup(const struct arm_boot_info *info, void *p) |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1265 | { |
| 1266 | return n8x0_atag_setup(p, 800); |
| 1267 | } |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1268 | |
Stefan Weil | 462a8bc | 2011-06-23 17:53:48 +0200 | [diff] [blame] | 1269 | static int n810_atag_setup(const struct arm_boot_info *info, void *p) |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1270 | { |
| 1271 | return n8x0_atag_setup(p, 810); |
| 1272 | } |
| 1273 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1274 | static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1275 | const char *kernel_filename, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1276 | const char *kernel_cmdline, const char *initrd_filename, |
| 1277 | const char *cpu_model, struct arm_boot_info *binfo, int model) |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1278 | { |
Avi Kivity | aee3950 | 2011-11-22 15:06:46 +0200 | [diff] [blame] | 1279 | MemoryRegion *sysmem = get_system_memory(); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1280 | struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1281 | int sdram_size = binfo->ram_size; |
aurel32 | 0921895 | 2009-02-09 17:00:41 +0000 | [diff] [blame] | 1282 | DisplayState *ds; |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1283 | |
Avi Kivity | aee3950 | 2011-11-22 15:06:46 +0200 | [diff] [blame] | 1284 | s->cpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1285 | |
balrog | 0941041 | 2008-05-18 13:14:29 +0000 | [diff] [blame] | 1286 | /* Setup peripherals |
| 1287 | * |
| 1288 | * Believed external peripherals layout in the N810: |
| 1289 | * (spi bus 1) |
| 1290 | * tsc2005 |
| 1291 | * lcd_mipid |
| 1292 | * (spi bus 2) |
| 1293 | * Conexant cx3110x (WLAN) |
| 1294 | * optional: pc2400m (WiMAX) |
| 1295 | * (i2c bus 0) |
| 1296 | * TLV320AIC33 (audio codec) |
| 1297 | * TCM825x (camera by Toshiba) |
| 1298 | * lp5521 (clever LEDs) |
| 1299 | * tsl2563 (light sensor, hwmon, model 7, rev. 0) |
| 1300 | * lm8323 (keypad, manf 00, rev 04) |
| 1301 | * (i2c bus 1) |
| 1302 | * tmp105 (temperature sensor, hwmon) |
| 1303 | * menelaus (pm) |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 1304 | * (somewhere on i2c - maybe N800-only) |
| 1305 | * tea5761 (FM tuner) |
| 1306 | * (serial 0) |
| 1307 | * GPS |
| 1308 | * (some serial port) |
| 1309 | * csr41814 (Bluetooth) |
balrog | 0941041 | 2008-05-18 13:14:29 +0000 | [diff] [blame] | 1310 | */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1311 | n8x0_gpio_setup(s); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1312 | n8x0_nand_setup(s); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1313 | n8x0_i2c_setup(s); |
| 1314 | if (model == 800) |
| 1315 | n800_tsc_kbd_setup(s); |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 1316 | else if (model == 810) { |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1317 | n810_tsc_setup(s); |
balrog | 1d4e547 | 2008-05-09 22:16:11 +0000 | [diff] [blame] | 1318 | n810_kbd_setup(s); |
| 1319 | } |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1320 | n8x0_spi_setup(s); |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1321 | n8x0_dss_setup(s); |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1322 | n8x0_cbus_setup(s); |
balrog | 58a26b4 | 2008-09-28 23:34:13 +0000 | [diff] [blame] | 1323 | n8x0_uart_setup(s); |
balrog | 942ac05 | 2008-04-22 03:15:10 +0000 | [diff] [blame] | 1324 | if (usb_enabled) |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1325 | n8x0_usb_setup(s); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1326 | |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1327 | if (kernel_filename) { |
| 1328 | /* Or at the linux loader. */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1329 | binfo->kernel_filename = kernel_filename; |
| 1330 | binfo->kernel_cmdline = kernel_cmdline; |
| 1331 | binfo->initrd_filename = initrd_filename; |
| 1332 | arm_load_kernel(s->cpu->env, binfo); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1333 | |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 1334 | qemu_register_reset(n8x0_boot_init, s); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1335 | } |
| 1336 | |
Gleb Natapov | 2e55e84 | 2010-12-08 13:35:07 +0200 | [diff] [blame] | 1337 | if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) { |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 1338 | int rom_size; |
pbrook | 5c130f6 | 2009-04-10 14:29:45 +0000 | [diff] [blame] | 1339 | uint8_t nolo_tags[0x10000]; |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 1340 | /* No, wait, better start at the ROM. */ |
| 1341 | s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; |
| 1342 | |
| 1343 | /* This is intended for loading the `secondary.bin' program from |
| 1344 | * Nokia images (the NOLO bootloader). The entry point seems |
| 1345 | * to be at OMAP2_Q2_BASE + 0x400000. |
| 1346 | * |
| 1347 | * The `2nd.bin' files contain some kind of earlier boot code and |
| 1348 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. |
| 1349 | * |
| 1350 | * The code above is for loading the `zImage' file from Nokia |
| 1351 | * images. */ |
Gleb Natapov | 2e55e84 | 2010-12-08 13:35:07 +0200 | [diff] [blame] | 1352 | rom_size = load_image_targphys(option_rom[0].name, |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 1353 | OMAP2_Q2_BASE + 0x400000, |
| 1354 | sdram_size - 0x400000); |
| 1355 | printf("%i bytes of image loaded\n", rom_size); |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 1356 | |
pbrook | 5c130f6 | 2009-04-10 14:29:45 +0000 | [diff] [blame] | 1357 | n800_setup_nolo_tags(nolo_tags); |
| 1358 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); |
balrog | d238db7 | 2008-05-18 13:58:19 +0000 | [diff] [blame] | 1359 | } |
pbrook | c60e08d | 2008-07-01 16:24:38 +0000 | [diff] [blame] | 1360 | /* FIXME: We shouldn't really be doing this here. The LCD controller |
| 1361 | will set the size once configured, so this just sets an initial |
| 1362 | size until the guest activates the display. */ |
aurel32 | 0921895 | 2009-02-09 17:00:41 +0000 | [diff] [blame] | 1363 | ds = get_displaystate(); |
aliguori | 7b5d76d | 2009-03-13 15:02:13 +0000 | [diff] [blame] | 1364 | ds->surface = qemu_resize_displaysurface(ds, 800, 480); |
aliguori | 7d957bd | 2009-01-15 22:14:11 +0000 | [diff] [blame] | 1365 | dpy_resize(ds); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1366 | } |
| 1367 | |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1368 | static struct arm_boot_info n800_binfo = { |
| 1369 | .loader_start = OMAP2_Q2_BASE, |
| 1370 | /* Actually two chips of 0x4000000 bytes each */ |
| 1371 | .ram_size = 0x08000000, |
| 1372 | .board_id = 0x4f7, |
| 1373 | .atag_board = n800_atag_setup, |
| 1374 | }; |
| 1375 | |
| 1376 | static struct arm_boot_info n810_binfo = { |
| 1377 | .loader_start = OMAP2_Q2_BASE, |
| 1378 | /* Actually two chips of 0x4000000 bytes each */ |
| 1379 | .ram_size = 0x08000000, |
| 1380 | /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not |
| 1381 | * used by some older versions of the bootloader and 5555 is used |
| 1382 | * instead (including versions that shipped with many devices). */ |
| 1383 | .board_id = 0x60c, |
| 1384 | .atag_board = n810_atag_setup, |
| 1385 | }; |
| 1386 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1387 | static void n800_init(ram_addr_t ram_size, |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1388 | const char *boot_device, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1389 | const char *kernel_filename, const char *kernel_cmdline, |
| 1390 | const char *initrd_filename, const char *cpu_model) |
| 1391 | { |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1392 | return n8x0_init(ram_size, boot_device, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1393 | kernel_filename, kernel_cmdline, initrd_filename, |
| 1394 | cpu_model, &n800_binfo, 800); |
| 1395 | } |
| 1396 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1397 | static void n810_init(ram_addr_t ram_size, |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1398 | const char *boot_device, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1399 | const char *kernel_filename, const char *kernel_cmdline, |
| 1400 | const char *initrd_filename, const char *cpu_model) |
| 1401 | { |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 1402 | return n8x0_init(ram_size, boot_device, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1403 | kernel_filename, kernel_cmdline, initrd_filename, |
| 1404 | cpu_model, &n810_binfo, 810); |
| 1405 | } |
| 1406 | |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1407 | static QEMUMachine n800_machine = { |
aliguori | 4b32e16 | 2008-10-07 20:34:35 +0000 | [diff] [blame] | 1408 | .name = "n800", |
| 1409 | .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)", |
| 1410 | .init = n800_init, |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 1411 | }; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1412 | |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1413 | static QEMUMachine n810_machine = { |
aliguori | 4b32e16 | 2008-10-07 20:34:35 +0000 | [diff] [blame] | 1414 | .name = "n810", |
| 1415 | .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)", |
| 1416 | .init = n810_init, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1417 | }; |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 1418 | |
| 1419 | static void nseries_machine_init(void) |
| 1420 | { |
| 1421 | qemu_register_machine(&n800_machine); |
| 1422 | qemu_register_machine(&n810_machine); |
| 1423 | } |
| 1424 | |
| 1425 | machine_init(nseries_machine_init); |