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ths663e8e52007-04-02 12:35:34 +00001/*
2 * QEMU i8255x (PRO100) emulation
3 *
Stefan Weil1b4f97d2011-04-30 22:40:04 +02004 * Copyright (C) 2006-2011 Stefan Weil
ths663e8e52007-04-02 12:35:34 +00005 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
Stefan Weil230a1672010-03-02 22:37:47 +01009 * This program is free software: you can redistribute it and/or modify
ths663e8e52007-04-02 12:35:34 +000010 * it under the terms of the GNU General Public License as published by
Stefan Weil230a1672010-03-02 22:37:47 +010011 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
ths663e8e52007-04-02 12:35:34 +000013 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
Stefan Weil230a1672010-03-02 22:37:47 +010020 * along with this program. If not, see <http://www.gnu.org/licenses/>.
ths663e8e52007-04-02 12:35:34 +000021 *
22 * Tested features (i82559):
Stefan Weile5e23ab2011-04-30 22:40:08 +020023 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
ths663e8e52007-04-02 12:35:34 +000024 * Linux networking (i386) ok
25 *
26 * Untested:
ths663e8e52007-04-02 12:35:34 +000027 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
Stefan Weilba19f2d2010-03-02 22:37:46 +010033 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
ths663e8e52007-04-02 12:35:34 +000041 */
42
ths663e8e52007-04-02 12:35:34 +000043#include <stddef.h> /* offsetof */
pbrook87ecb682007-11-17 17:14:51 +000044#include "hw.h"
45#include "pci.h"
46#include "net.h"
ths663e8e52007-04-02 12:35:34 +000047#include "eeprom93xx.h"
Gleb Natapov1ca4d092010-12-08 13:35:05 +020048#include "sysemu.h"
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +110049#include "dma.h"
ths663e8e52007-04-02 12:35:34 +000050
Stefan Weil792f1d62011-04-30 22:40:07 +020051/* QEMU sends frames smaller than 60 bytes to ethernet nics.
52 * Such frames are rejected by real nics and their emulations.
53 * To avoid this behaviour, other nic emulations pad received
54 * frames. The following definition enables this padding for
55 * eepro100, too. We keep the define around in case it might
56 * become useful the future if the core networking is ever
57 * changed to pad short packets itself. */
58#define CONFIG_PAD_RECEIVED_FRAMES
59
ths663e8e52007-04-02 12:35:34 +000060#define KiB 1024
61
Stefan Weilaac443e2009-09-19 12:11:36 +020062/* Debug EEPRO100 card. */
Stefan Weilce0e58b2010-03-02 22:37:41 +010063#if 0
64# define DEBUG_EEPRO100
65#endif
ths663e8e52007-04-02 12:35:34 +000066
67#ifdef DEBUG_EEPRO100
Blue Swirl001faf32009-05-13 17:53:17 +000068#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
ths663e8e52007-04-02 12:35:34 +000069#else
Blue Swirl001faf32009-05-13 17:53:17 +000070#define logout(fmt, ...) ((void)0)
ths663e8e52007-04-02 12:35:34 +000071#endif
72
73/* Set flags to 0 to disable debug output. */
Stefan Weilaac443e2009-09-19 12:11:36 +020074#define INT 1 /* interrupt related actions */
75#define MDI 1 /* mdi related actions */
76#define OTHER 1
77#define RXTX 1
78#define EEPROM 1 /* eeprom related actions */
ths663e8e52007-04-02 12:35:34 +000079
80#define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
Kevin Wolf7f1e9d42009-09-23 17:42:42 +020082#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
ths663e8e52007-04-02 12:35:34 +000083
84#define MAX_ETH_FRAME_SIZE 1514
85
86/* This driver supports several different devices which are declared here. */
Stefan Weilc4c270e2009-09-19 13:02:09 +020087#define i82550 0x82550
ths663e8e52007-04-02 12:35:34 +000088#define i82551 0x82551
Stefan Weilc4c270e2009-09-19 13:02:09 +020089#define i82557A 0x82557a
ths663e8e52007-04-02 12:35:34 +000090#define i82557B 0x82557b
91#define i82557C 0x82557c
Stefan Weilc4c270e2009-09-19 13:02:09 +020092#define i82558A 0x82558a
ths663e8e52007-04-02 12:35:34 +000093#define i82558B 0x82558b
Stefan Weilc4c270e2009-09-19 13:02:09 +020094#define i82559A 0x82559a
95#define i82559B 0x82559b
ths663e8e52007-04-02 12:35:34 +000096#define i82559C 0x82559c
97#define i82559ER 0x82559e
98#define i82562 0x82562
Stefan Weildb667a12010-04-06 13:44:04 +020099#define i82801 0x82801
ths663e8e52007-04-02 12:35:34 +0000100
Stefan Weilaac443e2009-09-19 12:11:36 +0200101/* Use 64 word EEPROM. TODO: could be a runtime option. */
ths663e8e52007-04-02 12:35:34 +0000102#define EEPROM_SIZE 64
103
104#define PCI_MEM_SIZE (4 * KiB)
105#define PCI_IO_SIZE 64
106#define PCI_FLASH_SIZE (128 * KiB)
107
108#define BIT(n) (1 << (n))
109#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110
111/* The SCB accepts the following controls for the Tx and Rx units: */
112#define CU_NOP 0x0000 /* No operation. */
113#define CU_START 0x0010 /* CU start. */
114#define CU_RESUME 0x0020 /* CU resume. */
115#define CU_STATSADDR 0x0040 /* Load dump counters address. */
116#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
117#define CU_CMD_BASE 0x0060 /* Load CU base address. */
118#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
119#define CU_SRESUME 0x00a0 /* CU static resume. */
120
121#define RU_NOP 0x0000
122#define RX_START 0x0001
123#define RX_RESUME 0x0002
Stefan Weile8240122010-03-02 22:37:53 +0100124#define RU_ABORT 0x0004
ths663e8e52007-04-02 12:35:34 +0000125#define RX_ADDR_LOAD 0x0006
126#define RX_RESUMENR 0x0007
127#define INT_MASK 0x0100
128#define DRVR_INT 0x0200 /* Driver generated interrupt. */
129
Stefan Weil558c8632010-04-06 13:44:03 +0200130typedef struct {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600131 const char *name;
132 const char *desc;
Anthony Liguori40021f02011-12-04 12:22:06 -0600133 uint16_t device_id;
134 uint8_t revision;
135 uint16_t subsystem_vendor_id;
136 uint16_t subsystem_id;
137
Stefan Weil558c8632010-04-06 13:44:03 +0200138 uint32_t device;
Stefan Weil558c8632010-04-06 13:44:03 +0200139 uint8_t stats_size;
140 bool has_extended_tcb_support;
141 bool power_management;
142} E100PCIDeviceInfo;
143
ths663e8e52007-04-02 12:35:34 +0000144/* Offsets to the various registers.
145 All accesses need not be longword aligned. */
Stefan Weile5e23ab2011-04-30 22:40:08 +0200146typedef enum {
Stefan Weil0908bba2010-03-02 22:37:42 +0100147 SCBStatus = 0, /* Status Word. */
ths663e8e52007-04-02 12:35:34 +0000148 SCBAck = 1,
149 SCBCmd = 2, /* Rx/Command Unit command and status. */
150 SCBIntmask = 3,
151 SCBPointer = 4, /* General purpose pointer. */
152 SCBPort = 8, /* Misc. commands and operands. */
Stefan Weil0908bba2010-03-02 22:37:42 +0100153 SCBflash = 12, /* Flash memory control. */
154 SCBeeprom = 14, /* EEPROM control. */
ths663e8e52007-04-02 12:35:34 +0000155 SCBCtrlMDI = 16, /* MDI interface control. */
156 SCBEarlyRx = 20, /* Early receive byte count. */
Stefan Weil0908bba2010-03-02 22:37:42 +0100157 SCBFlow = 24, /* Flow Control. */
158 SCBpmdr = 27, /* Power Management Driver. */
159 SCBgctrl = 28, /* General Control. */
160 SCBgstat = 29, /* General Status. */
Stefan Weile5e23ab2011-04-30 22:40:08 +0200161} E100RegisterOffset;
ths663e8e52007-04-02 12:35:34 +0000162
163/* A speedo3 transmit buffer descriptor with two buffers... */
164typedef struct {
165 uint16_t status;
166 uint16_t command;
167 uint32_t link; /* void * */
Stefan Weil7b8737d2009-12-20 16:52:24 +0100168 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
ths663e8e52007-04-02 12:35:34 +0000169 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
170 uint8_t tx_threshold; /* transmit threshold */
171 uint8_t tbd_count; /* TBD number */
Stefan Weile7493b22010-03-02 22:37:59 +0100172#if 0
173 /* This constitutes two "TBD" entries: hdr and data */
174 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
175 int32_t tx_buf_size0; /* Length of Tx hdr. */
176 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
177 int32_t tx_buf_size1; /* Length of Tx data. */
178#endif
Anthony Liguoric227f092009-10-01 16:12:16 -0500179} eepro100_tx_t;
ths663e8e52007-04-02 12:35:34 +0000180
181/* Receive frame descriptor. */
182typedef struct {
183 int16_t status;
184 uint16_t command;
185 uint32_t link; /* struct RxFD * */
186 uint32_t rx_buf_addr; /* void * */
187 uint16_t count;
188 uint16_t size;
Stefan Weil27112f12011-04-30 22:40:06 +0200189 /* Ethernet frame data follows. */
Anthony Liguoric227f092009-10-01 16:12:16 -0500190} eepro100_rx_t;
ths663e8e52007-04-02 12:35:34 +0000191
Stefan Weilced52962010-03-02 22:37:49 +0100192typedef enum {
193 COMMAND_EL = BIT(15),
194 COMMAND_S = BIT(14),
195 COMMAND_I = BIT(13),
196 COMMAND_NC = BIT(4),
197 COMMAND_SF = BIT(3),
198 COMMAND_CMD = BITS(2, 0),
199} scb_command_bit;
200
201typedef enum {
202 STATUS_C = BIT(15),
203 STATUS_OK = BIT(13),
204} scb_status_bit;
205
ths663e8e52007-04-02 12:35:34 +0000206typedef struct {
207 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
Stefan Weilcc02c662010-03-02 22:37:55 +0100208 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
209 tx_multiple_collisions, tx_total_collisions;
ths663e8e52007-04-02 12:35:34 +0000210 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
Stefan Weilcc02c662010-03-02 22:37:55 +0100211 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
212 rx_short_frame_errors;
ths663e8e52007-04-02 12:35:34 +0000213 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
214 uint16_t xmt_tco_frames, rcv_tco_frames;
Stefan Weilba42b642009-10-30 13:36:21 +0100215 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
216 uint32_t reserved[4];
Anthony Liguoric227f092009-10-01 16:12:16 -0500217} eepro100_stats_t;
ths663e8e52007-04-02 12:35:34 +0000218
219typedef enum {
220 cu_idle = 0,
221 cu_suspended = 1,
222 cu_active = 2,
223 cu_lpq_active = 2,
224 cu_hqp_active = 3
Anthony Liguoric227f092009-10-01 16:12:16 -0500225} cu_state_t;
ths663e8e52007-04-02 12:35:34 +0000226
227typedef enum {
228 ru_idle = 0,
229 ru_suspended = 1,
230 ru_no_resources = 2,
231 ru_ready = 4
Anthony Liguoric227f092009-10-01 16:12:16 -0500232} ru_state_t;
ths663e8e52007-04-02 12:35:34 +0000233
ths663e8e52007-04-02 12:35:34 +0000234typedef struct {
Juan Quintela273a2142009-08-24 18:42:37 +0200235 PCIDevice dev;
Stefan Weil010ec622010-09-29 21:59:55 +0200236 /* Hash register (multicast mask array, multiple individual addresses). */
237 uint8_t mult[8];
Avi Kivity5e6ffdd2011-08-08 16:09:09 +0300238 MemoryRegion mmio_bar;
239 MemoryRegion io_bar;
240 MemoryRegion flash_bar;
Mark McLoughline00e3652009-11-25 18:49:16 +0000241 NICState *nic;
Gerd Hoffmann508ef932009-10-21 15:25:36 +0200242 NICConf conf;
ths663e8e52007-04-02 12:35:34 +0000243 uint8_t scb_stat; /* SCB stat/ack byte */
244 uint8_t int_stat; /* PCI interrupt status */
Stefan Weil3706c432009-10-09 19:49:58 +0200245 /* region must not be saved by nic_save. */
ths663e8e52007-04-02 12:35:34 +0000246 uint16_t mdimem[32];
Anthony Liguoric227f092009-10-01 16:12:16 -0500247 eeprom_t *eeprom;
ths663e8e52007-04-02 12:35:34 +0000248 uint32_t device; /* device variant */
ths663e8e52007-04-02 12:35:34 +0000249 /* (cu_base + cu_offset) address the next command block in the command block list. */
250 uint32_t cu_base; /* CU base address */
251 uint32_t cu_offset; /* CU address offset */
252 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
253 uint32_t ru_base; /* RU base address */
254 uint32_t ru_offset; /* RU address offset */
Anthony Liguoric227f092009-10-01 16:12:16 -0500255 uint32_t statsaddr; /* pointer to eepro100_stats_t */
Stefan Weilba42b642009-10-30 13:36:21 +0100256
Stefan Weilf3a52e52009-12-20 16:52:22 +0100257 /* Temporary status information (no need to save these values),
258 * used while processing CU commands. */
259 eepro100_tx_t tx; /* transmit buffer descriptor */
260 uint32_t cb_address; /* = cu_base + cu_offset */
261
Stefan Weilba42b642009-10-30 13:36:21 +0100262 /* Statistical counters. Also used for wake-up packet (i82559). */
263 eepro100_stats_t statistics;
264
Stefan Weile5e23ab2011-04-30 22:40:08 +0200265 /* Data in mem is always in the byte order of the controller (le).
266 * It must be dword aligned to allow direct access to 32 bit values. */
Dong Xu Wang3a931132011-11-29 16:52:38 +0800267 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
Stefan Weile5e23ab2011-04-30 22:40:08 +0200268
ths663e8e52007-04-02 12:35:34 +0000269 /* Configuration bytes. */
270 uint8_t configuration[22];
271
Juan Quintela151b2982009-10-19 15:37:57 +0200272 /* vmstate for each particular nic */
273 VMStateDescription *vmstate;
Stefan Weilba42b642009-10-30 13:36:21 +0100274
275 /* Quasi static device properties (no need to save them). */
276 uint16_t stats_size;
277 bool has_extended_tcb_support;
ths663e8e52007-04-02 12:35:34 +0000278} EEPRO100State;
279
Stefan Weil6cded3a2010-03-02 22:37:43 +0100280/* Word indices in EEPROM. */
281typedef enum {
282 EEPROM_CNFG_MDIX = 0x03,
283 EEPROM_ID = 0x05,
284 EEPROM_PHY_ID = 0x06,
285 EEPROM_VENDOR_ID = 0x0c,
286 EEPROM_CONFIG_ASF = 0x0d,
287 EEPROM_DEVICE_ID = 0x23,
288 EEPROM_SMBUS_ADDR = 0x90,
289} EEPROMOffset;
290
Stefan Weilb1e87012010-03-02 22:37:51 +0100291/* Bit values for EEPROM ID word. */
292typedef enum {
293 EEPROM_ID_MDM = BIT(0), /* Modem */
294 EEPROM_ID_STB = BIT(1), /* Standby Enable */
295 EEPROM_ID_WMR = BIT(2), /* ??? */
296 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
297 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
298 EEPROM_ID_ALT = BIT(7), /* */
299 /* BITS(10, 8) device revision */
300 EEPROM_ID_BD = BIT(11), /* boot disable */
301 EEPROM_ID_ID = BIT(13), /* id bit */
302 /* BITS(15, 14) signature */
303 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
304} eeprom_id_bit;
305
ths663e8e52007-04-02 12:35:34 +0000306/* Default values for MDI (PHY) registers */
307static const uint16_t eepro100_mdi_default[] = {
308 /* MDI Registers 0 - 6, 7 */
309 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
310 /* MDI Registers 8 - 15 */
311 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
312 /* MDI Registers 16 - 31 */
313 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315};
316
317/* Readonly mask for MDI (PHY) registers */
318static const uint16_t eepro100_mdi_mask[] = {
319 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
322 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323};
324
325#define POLYNOMIAL 0x04c11db6
326
Anthony Liguori40021f02011-12-04 12:22:06 -0600327static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
328
ths663e8e52007-04-02 12:35:34 +0000329/* From FreeBSD */
330/* XXX: optimize */
Stefan Weil7b8737d2009-12-20 16:52:24 +0100331static unsigned compute_mcast_idx(const uint8_t * ep)
ths663e8e52007-04-02 12:35:34 +0000332{
333 uint32_t crc;
334 int carry, i, j;
335 uint8_t b;
336
337 crc = 0xffffffff;
338 for (i = 0; i < 6; i++) {
339 b = *ep++;
340 for (j = 0; j < 8; j++) {
341 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
342 crc <<= 1;
343 b >>= 1;
Stefan Weilaac443e2009-09-19 12:11:36 +0200344 if (carry) {
ths663e8e52007-04-02 12:35:34 +0000345 crc = ((crc ^ POLYNOMIAL) | carry);
Stefan Weilaac443e2009-09-19 12:11:36 +0200346 }
ths663e8e52007-04-02 12:35:34 +0000347 }
348 }
Stefan Weil7b8737d2009-12-20 16:52:24 +0100349 return (crc & BITS(7, 2)) >> 2;
ths663e8e52007-04-02 12:35:34 +0000350}
351
Stefan Weile5e23ab2011-04-30 22:40:08 +0200352/* Read a 16 bit control/status (CSR) register. */
353static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
354{
355 assert(!((uintptr_t)&s->mem[addr] & 1));
356 return le16_to_cpup((uint16_t *)&s->mem[addr]);
357}
358
359/* Read a 32 bit control/status (CSR) register. */
360static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
361{
362 assert(!((uintptr_t)&s->mem[addr] & 3));
363 return le32_to_cpup((uint32_t *)&s->mem[addr]);
364}
365
366/* Write a 16 bit control/status (CSR) register. */
367static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
368 uint16_t val)
369{
370 assert(!((uintptr_t)&s->mem[addr] & 1));
371 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
372}
373
374/* Read a 32 bit control/status (CSR) register. */
375static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
376 uint32_t val)
377{
378 assert(!((uintptr_t)&s->mem[addr] & 3));
379 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
380}
381
ths663e8e52007-04-02 12:35:34 +0000382#if defined(DEBUG_EEPRO100)
383static const char *nic_dump(const uint8_t * buf, unsigned size)
384{
385 static char dump[3 * 16 + 1];
386 char *p = &dump[0];
Stefan Weilaac443e2009-09-19 12:11:36 +0200387 if (size > 16) {
ths663e8e52007-04-02 12:35:34 +0000388 size = 16;
Stefan Weilaac443e2009-09-19 12:11:36 +0200389 }
ths663e8e52007-04-02 12:35:34 +0000390 while (size-- > 0) {
391 p += sprintf(p, " %02x", *buf++);
392 }
393 return dump;
394}
395#endif /* DEBUG_EEPRO100 */
396
397enum scb_stat_ack {
398 stat_ack_not_ours = 0x00,
399 stat_ack_sw_gen = 0x04,
400 stat_ack_rnr = 0x10,
401 stat_ack_cu_idle = 0x20,
402 stat_ack_frame_rx = 0x40,
403 stat_ack_cu_cmd_done = 0x80,
404 stat_ack_not_present = 0xFF,
405 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
406 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
407};
408
409static void disable_interrupt(EEPRO100State * s)
410{
411 if (s->int_stat) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200412 TRACE(INT, logout("interrupt disabled\n"));
Juan Quintela273a2142009-08-24 18:42:37 +0200413 qemu_irq_lower(s->dev.irq[0]);
ths663e8e52007-04-02 12:35:34 +0000414 s->int_stat = 0;
415 }
416}
417
418static void enable_interrupt(EEPRO100State * s)
419{
420 if (!s->int_stat) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200421 TRACE(INT, logout("interrupt enabled\n"));
Juan Quintela273a2142009-08-24 18:42:37 +0200422 qemu_irq_raise(s->dev.irq[0]);
ths663e8e52007-04-02 12:35:34 +0000423 s->int_stat = 1;
424 }
425}
426
427static void eepro100_acknowledge(EEPRO100State * s)
428{
429 s->scb_stat &= ~s->mem[SCBAck];
430 s->mem[SCBAck] = s->scb_stat;
431 if (s->scb_stat == 0) {
432 disable_interrupt(s);
433 }
434}
435
Stefan Weile715c8e2010-03-02 22:37:52 +0100436static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
ths663e8e52007-04-02 12:35:34 +0000437{
438 uint8_t mask = ~s->mem[SCBIntmask];
Stefan Weile715c8e2010-03-02 22:37:52 +0100439 s->mem[SCBAck] |= status;
440 status = s->scb_stat = s->mem[SCBAck];
441 status &= (mask | 0x0f);
Stefan Weile7493b22010-03-02 22:37:59 +0100442#if 0
443 status &= (~s->mem[SCBIntmask] | 0x0xf);
444#endif
Stefan Weile715c8e2010-03-02 22:37:52 +0100445 if (status && (mask & 0x01)) {
ths663e8e52007-04-02 12:35:34 +0000446 /* SCB mask and SCB Bit M do not disable interrupt. */
447 enable_interrupt(s);
448 } else if (s->int_stat) {
449 disable_interrupt(s);
450 }
451}
452
453static void eepro100_cx_interrupt(EEPRO100State * s)
454{
455 /* CU completed action command. */
456 /* Transmit not ok (82557 only, not in emulation). */
457 eepro100_interrupt(s, 0x80);
458}
459
460static void eepro100_cna_interrupt(EEPRO100State * s)
461{
462 /* CU left the active state. */
463 eepro100_interrupt(s, 0x20);
464}
465
466static void eepro100_fr_interrupt(EEPRO100State * s)
467{
468 /* RU received a complete frame. */
469 eepro100_interrupt(s, 0x40);
470}
471
ths663e8e52007-04-02 12:35:34 +0000472static void eepro100_rnr_interrupt(EEPRO100State * s)
473{
474 /* RU is not ready. */
475 eepro100_interrupt(s, 0x10);
476}
ths663e8e52007-04-02 12:35:34 +0000477
478static void eepro100_mdi_interrupt(EEPRO100State * s)
479{
480 /* MDI completed read or write cycle. */
481 eepro100_interrupt(s, 0x08);
482}
483
484static void eepro100_swi_interrupt(EEPRO100State * s)
485{
486 /* Software has requested an interrupt. */
487 eepro100_interrupt(s, 0x04);
488}
489
490#if 0
491static void eepro100_fcp_interrupt(EEPRO100State * s)
492{
493 /* Flow control pause interrupt (82558 and later). */
494 eepro100_interrupt(s, 0x01);
495}
496#endif
497
Anthony Liguori40021f02011-12-04 12:22:06 -0600498static void e100_pci_reset(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000499{
Anthony Liguori40021f02011-12-04 12:22:06 -0600500 E100PCIDeviceInfo *info = eepro100_get_class(s);
ths663e8e52007-04-02 12:35:34 +0000501 uint32_t device = s->device;
Juan Quintela273a2142009-08-24 18:42:37 +0200502 uint8_t *pci_conf = s->dev.config;
ths663e8e52007-04-02 12:35:34 +0000503
Stefan Weilaac443e2009-09-19 12:11:36 +0200504 TRACE(OTHER, logout("%p\n", s));
ths663e8e52007-04-02 12:35:34 +0000505
ths663e8e52007-04-02 12:35:34 +0000506 /* PCI Status */
Stefan Weilae543b42010-04-06 13:44:07 +0200507 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
508 PCI_STATUS_FAST_BACK);
ths663e8e52007-04-02 12:35:34 +0000509 /* PCI Latency Timer */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200510 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
Stefan Weilae543b42010-04-06 13:44:07 +0200511 /* Capability Pointer is set by PCI framework. */
Stefan Weilf62719c2010-04-06 13:44:09 +0200512 /* Interrupt Line */
513 /* Interrupt Pin */
514 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
ths663e8e52007-04-02 12:35:34 +0000515 /* Minimum Grant */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200516 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
ths663e8e52007-04-02 12:35:34 +0000517 /* Maximum Latency */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200518 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
ths663e8e52007-04-02 12:35:34 +0000519
Anthony Liguori40021f02011-12-04 12:22:06 -0600520 s->stats_size = info->stats_size;
521 s->has_extended_tcb_support = info->has_extended_tcb_support;
Stefan Weil558c8632010-04-06 13:44:03 +0200522
ths663e8e52007-04-02 12:35:34 +0000523 switch (device) {
Stefan Weilba42b642009-10-30 13:36:21 +0100524 case i82550:
ths663e8e52007-04-02 12:35:34 +0000525 case i82551:
Stefan Weilba42b642009-10-30 13:36:21 +0100526 case i82557A:
ths663e8e52007-04-02 12:35:34 +0000527 case i82557B:
ths663e8e52007-04-02 12:35:34 +0000528 case i82557C:
Stefan Weilba42b642009-10-30 13:36:21 +0100529 case i82558A:
ths663e8e52007-04-02 12:35:34 +0000530 case i82558B:
Stefan Weilba42b642009-10-30 13:36:21 +0100531 case i82559A:
Stefan Weilba42b642009-10-30 13:36:21 +0100532 case i82559B:
Stefan Weil558c8632010-04-06 13:44:03 +0200533 case i82559ER:
534 case i82562:
Stefan Weildb667a12010-04-06 13:44:04 +0200535 case i82801:
ths663e8e52007-04-02 12:35:34 +0000536 case i82559C:
Stefan Weilba42b642009-10-30 13:36:21 +0100537 break;
ths663e8e52007-04-02 12:35:34 +0000538 default:
539 logout("Device %X is undefined!\n", device);
540 }
541
Stefan Weil3dec59a2010-04-06 13:44:05 +0200542 /* Standard TxCB. */
543 s->configuration[6] |= BIT(4);
544
Stefan Weil558c8632010-04-06 13:44:03 +0200545 /* Standard statistical counters. */
Stefan Weilba42b642009-10-30 13:36:21 +0100546 s->configuration[6] |= BIT(5);
547
548 if (s->stats_size == 80) {
549 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
550 if (s->configuration[6] & BIT(2)) {
551 /* TCO statistical counters. */
552 assert(s->configuration[6] & BIT(5));
553 } else {
554 if (s->configuration[6] & BIT(5)) {
555 /* No extended statistical counters, i82557 compatible. */
556 s->stats_size = 64;
557 } else {
558 /* i82558 compatible. */
559 s->stats_size = 76;
560 }
561 }
562 } else {
563 if (s->configuration[6] & BIT(5)) {
564 /* No extended statistical counters. */
565 s->stats_size = 64;
566 }
567 }
568 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
569
Anthony Liguori40021f02011-12-04 12:22:06 -0600570 if (info->power_management) {
Stefan Weilba42b642009-10-30 13:36:21 +0100571 /* Power Management Capabilities */
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300572 int cfg_offset = 0xdc;
Isaku Yamahataca770892010-09-06 16:46:16 +0900573 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
574 cfg_offset, PCI_PM_SIZEOF);
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300575 assert(r >= 0);
576 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
Stefan Weilae543b42010-04-06 13:44:07 +0200577#if 0 /* TODO: replace dummy code for power management emulation. */
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300578 /* TODO: Power Management Control / Status. */
579 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
580 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
581 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
Stefan Weilae543b42010-04-06 13:44:07 +0200582#endif
Stefan Weilba42b642009-10-30 13:36:21 +0100583 }
584
585#if EEPROM_SIZE > 0
ths663e8e52007-04-02 12:35:34 +0000586 if (device == i82557C || device == i82558B || device == i82559C) {
Stefan Weile7493b22010-03-02 22:37:59 +0100587 /*
588 TODO: get vendor id from EEPROM for i82557C or later.
589 TODO: get device id from EEPROM for i82557C or later.
590 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
591 TODO: header type is determined by EEPROM for i82559.
592 TODO: get subsystem id from EEPROM for i82557C or later.
593 TODO: get subsystem vendor id from EEPROM for i82557C or later.
594 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
595 TODO: capability pointer depends on EEPROM for i82558.
596 */
ths663e8e52007-04-02 12:35:34 +0000597 logout("Get device id and revision from EEPROM!!!\n");
598 }
Stefan Weilba42b642009-10-30 13:36:21 +0100599#endif /* EEPROM_SIZE > 0 */
ths663e8e52007-04-02 12:35:34 +0000600}
601
602static void nic_selective_reset(EEPRO100State * s)
603{
604 size_t i;
605 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
Stefan Weile7493b22010-03-02 22:37:59 +0100606#if 0
607 eeprom93xx_reset(s->eeprom);
608#endif
Gerd Hoffmann508ef932009-10-21 15:25:36 +0200609 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
Stefan Weilb1e87012010-03-02 22:37:51 +0100610 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
=?UTF-8?q?Reimar=20D=C3=B6ffinger?=f4e94df2009-09-12 15:42:01 +0200611 if (s->device == i82557B || s->device == i82557C)
612 eeprom_contents[5] = 0x0100;
Stefan Weil6cded3a2010-03-02 22:37:43 +0100613 eeprom_contents[EEPROM_PHY_ID] = 1;
ths663e8e52007-04-02 12:35:34 +0000614 uint16_t sum = 0;
615 for (i = 0; i < EEPROM_SIZE - 1; i++) {
616 sum += eeprom_contents[i];
617 }
618 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
Stefan Weilaac443e2009-09-19 12:11:36 +0200619 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
ths663e8e52007-04-02 12:35:34 +0000620
621 memset(s->mem, 0, sizeof(s->mem));
Stefan Weile5e23ab2011-04-30 22:40:08 +0200622 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
ths663e8e52007-04-02 12:35:34 +0000623
624 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
625 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
626}
627
628static void nic_reset(void *opaque)
629{
Juan Quintela769cf7a2009-08-24 18:42:36 +0200630 EEPRO100State *s = opaque;
Stefan Weilaac443e2009-09-19 12:11:36 +0200631 TRACE(OTHER, logout("%p\n", s));
Stefan Weil010ec622010-09-29 21:59:55 +0200632 /* TODO: Clearing of hash register for selective reset, too? */
Stefan Weil7b8737d2009-12-20 16:52:24 +0100633 memset(&s->mult[0], 0, sizeof(s->mult));
ths663e8e52007-04-02 12:35:34 +0000634 nic_selective_reset(s);
635}
636
637#if defined(DEBUG_EEPRO100)
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100638static const char * const e100_reg[PCI_IO_SIZE / 4] = {
ths663e8e52007-04-02 12:35:34 +0000639 "Command/Status",
640 "General Pointer",
641 "Port",
642 "EEPROM/Flash Control",
643 "MDI Control",
644 "Receive DMA Byte Count",
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100645 "Flow Control",
ths663e8e52007-04-02 12:35:34 +0000646 "General Status/Control"
647};
648
649static char *regname(uint32_t addr)
650{
David Benjaminec169282009-11-25 21:20:10 -0500651 static char buf[32];
ths663e8e52007-04-02 12:35:34 +0000652 if (addr < PCI_IO_SIZE) {
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100653 const char *r = e100_reg[addr / 4];
ths663e8e52007-04-02 12:35:34 +0000654 if (r != 0) {
Stefan Weil41cbc232009-09-19 12:29:59 +0200655 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
ths663e8e52007-04-02 12:35:34 +0000656 } else {
Stefan Weil41cbc232009-09-19 12:29:59 +0200657 snprintf(buf, sizeof(buf), "0x%02x", addr);
ths663e8e52007-04-02 12:35:34 +0000658 }
659 } else {
Stefan Weil41cbc232009-09-19 12:29:59 +0200660 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
ths663e8e52007-04-02 12:35:34 +0000661 }
662 return buf;
663}
664#endif /* DEBUG_EEPRO100 */
665
ths663e8e52007-04-02 12:35:34 +0000666/*****************************************************************************
667 *
668 * Command emulation.
669 *
670 ****************************************************************************/
671
672#if 0
673static uint16_t eepro100_read_command(EEPRO100State * s)
674{
675 uint16_t val = 0xffff;
Stefan Weile7493b22010-03-02 22:37:59 +0100676 TRACE(OTHER, logout("val=0x%04x\n", val));
ths663e8e52007-04-02 12:35:34 +0000677 return val;
678}
679#endif
680
681/* Commands that can be put in a command list entry. */
682enum commands {
683 CmdNOp = 0,
684 CmdIASetup = 1,
685 CmdConfigure = 2,
686 CmdMulticastList = 3,
687 CmdTx = 4,
688 CmdTDR = 5, /* load microcode */
689 CmdDump = 6,
690 CmdDiagnose = 7,
691
692 /* And some extra flags: */
693 CmdSuspend = 0x4000, /* Suspend after completion. */
694 CmdIntr = 0x2000, /* Interrupt after completion. */
695 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
696};
697
Anthony Liguoric227f092009-10-01 16:12:16 -0500698static cu_state_t get_cu_state(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000699{
Stefan Weilced52962010-03-02 22:37:49 +0100700 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
ths663e8e52007-04-02 12:35:34 +0000701}
702
Anthony Liguoric227f092009-10-01 16:12:16 -0500703static void set_cu_state(EEPRO100State * s, cu_state_t state)
ths663e8e52007-04-02 12:35:34 +0000704{
Stefan Weilced52962010-03-02 22:37:49 +0100705 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
ths663e8e52007-04-02 12:35:34 +0000706}
707
Anthony Liguoric227f092009-10-01 16:12:16 -0500708static ru_state_t get_ru_state(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000709{
Stefan Weilced52962010-03-02 22:37:49 +0100710 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
ths663e8e52007-04-02 12:35:34 +0000711}
712
Anthony Liguoric227f092009-10-01 16:12:16 -0500713static void set_ru_state(EEPRO100State * s, ru_state_t state)
ths663e8e52007-04-02 12:35:34 +0000714{
Stefan Weilced52962010-03-02 22:37:49 +0100715 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
ths663e8e52007-04-02 12:35:34 +0000716}
717
718static void dump_statistics(EEPRO100State * s)
719{
720 /* Dump statistical data. Most data is never changed by the emulation
721 * and always 0, so we first just copy the whole block and then those
722 * values which really matter.
723 * Number of data should check configuration!!!
724 */
David Gibsone965d4b2011-11-04 12:03:32 +1100725 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100726 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
727 s->statistics.tx_good_frames);
728 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
729 s->statistics.rx_good_frames);
730 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
731 s->statistics.rx_resource_errors);
732 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
733 s->statistics.rx_short_frame_errors);
Stefan Weile7493b22010-03-02 22:37:59 +0100734#if 0
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100735 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
736 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
Stefan Weile7493b22010-03-02 22:37:59 +0100737 missing("CU dump statistical counters");
738#endif
ths663e8e52007-04-02 12:35:34 +0000739}
740
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100741static void read_cb(EEPRO100State *s)
742{
David Gibsone965d4b2011-11-04 12:03:32 +1100743 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100744 s->tx.status = le16_to_cpu(s->tx.status);
745 s->tx.command = le16_to_cpu(s->tx.command);
746 s->tx.link = le32_to_cpu(s->tx.link);
747 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
748 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
749}
750
Stefan Weilf3a52e52009-12-20 16:52:22 +0100751static void tx_command(EEPRO100State *s)
752{
Stefan Weil7b8737d2009-12-20 16:52:24 +0100753 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100754 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
755 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
756 uint8_t buf[2600];
757 uint16_t size = 0;
758 uint32_t tbd_address = s->cb_address + 0x10;
759 TRACE(RXTX, logout
760 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
761 tbd_array, tcb_bytes, s->tx.tbd_count));
762
763 if (tcb_bytes > 2600) {
764 logout("TCB byte count too large, using 2600\n");
765 tcb_bytes = 2600;
766 }
767 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
768 logout
769 ("illegal values of TBD array address and TCB byte count!\n");
770 }
771 assert(tcb_bytes <= sizeof(buf));
772 while (size < tcb_bytes) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100773 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
774 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
Stefan Weile7493b22010-03-02 22:37:59 +0100775#if 0
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100776 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
Stefan Weile7493b22010-03-02 22:37:59 +0100777#endif
Stefan Weilf3a52e52009-12-20 16:52:22 +0100778 tbd_address += 8;
779 TRACE(RXTX, logout
780 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
781 tx_buffer_address, tx_buffer_size));
782 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100783 pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100784 size += tx_buffer_size;
785 }
786 if (tbd_array == 0xffffffff) {
787 /* Simplified mode. Was already handled by code above. */
788 } else {
789 /* Flexible mode. */
790 uint8_t tbd_count = 0;
791 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
792 /* Extended Flexible TCB. */
793 for (; tbd_count < 2; tbd_count++) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100794 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
795 tbd_address);
796 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
797 tbd_address + 4);
798 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
799 tbd_address + 6);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100800 tbd_address += 8;
801 TRACE(RXTX, logout
802 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
803 tx_buffer_address, tx_buffer_size));
804 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100805 pci_dma_read(&s->dev, tx_buffer_address,
806 &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100807 size += tx_buffer_size;
808 if (tx_buffer_el & 1) {
809 break;
810 }
811 }
812 }
813 tbd_address = tbd_array;
814 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100815 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
816 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
817 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100818 tbd_address += 8;
819 TRACE(RXTX, logout
820 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
821 tx_buffer_address, tx_buffer_size));
822 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100823 pci_dma_read(&s->dev, tx_buffer_address,
824 &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100825 size += tx_buffer_size;
826 if (tx_buffer_el & 1) {
827 break;
828 }
829 }
830 }
831 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
832 qemu_send_packet(&s->nic->nc, buf, size);
833 s->statistics.tx_good_frames++;
834 /* Transmit with bad status would raise an CX/TNO interrupt.
835 * (82557 only). Emulation never has bad status. */
Stefan Weile7493b22010-03-02 22:37:59 +0100836#if 0
837 eepro100_cx_interrupt(s);
838#endif
Stefan Weilf3a52e52009-12-20 16:52:22 +0100839}
840
Stefan Weil7b8737d2009-12-20 16:52:24 +0100841static void set_multicast_list(EEPRO100State *s)
842{
843 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
844 uint16_t i;
845 memset(&s->mult[0], 0, sizeof(s->mult));
846 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
847 for (i = 0; i < multicast_count; i += 6) {
848 uint8_t multicast_addr[6];
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100849 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
Stefan Weil7b8737d2009-12-20 16:52:24 +0100850 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
851 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
852 assert(mcast_idx < 64);
853 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
854 }
855}
856
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200857static void action_command(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +0000858{
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200859 for (;;) {
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100860 bool bit_el;
861 bool bit_s;
862 bool bit_i;
863 bool bit_nc;
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200864 uint16_t ok_status = STATUS_OK;
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100865 s->cb_address = s->cu_base + s->cu_offset;
866 read_cb(s);
867 bit_el = ((s->tx.command & COMMAND_EL) != 0);
868 bit_s = ((s->tx.command & COMMAND_S) != 0);
869 bit_i = ((s->tx.command & COMMAND_I) != 0);
870 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
871#if 0
872 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
873#endif
874 s->cu_offset = s->tx.link;
875 TRACE(OTHER,
876 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
877 s->tx.status, s->tx.command, s->tx.link));
878 switch (s->tx.command & COMMAND_CMD) {
ths663e8e52007-04-02 12:35:34 +0000879 case CmdNOp:
880 /* Do nothing. */
881 break;
882 case CmdIASetup:
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100883 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
Stefan Weilce0e58b2010-03-02 22:37:41 +0100884 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
ths663e8e52007-04-02 12:35:34 +0000885 break;
886 case CmdConfigure:
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100887 pci_dma_read(&s->dev, s->cb_address + 8,
888 &s->configuration[0], sizeof(s->configuration));
Stefan Weil010ec622010-09-29 21:59:55 +0200889 TRACE(OTHER, logout("configuration: %s\n",
890 nic_dump(&s->configuration[0], 16)));
891 TRACE(OTHER, logout("configuration: %s\n",
892 nic_dump(&s->configuration[16],
893 ARRAY_SIZE(s->configuration) - 16)));
894 if (s->configuration[20] & BIT(6)) {
895 TRACE(OTHER, logout("Multiple IA bit\n"));
896 }
ths663e8e52007-04-02 12:35:34 +0000897 break;
898 case CmdMulticastList:
Stefan Weil7b8737d2009-12-20 16:52:24 +0100899 set_multicast_list(s);
ths663e8e52007-04-02 12:35:34 +0000900 break;
901 case CmdTx:
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200902 if (bit_nc) {
903 missing("CmdTx: NC = 0");
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200904 ok_status = 0;
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200905 break;
906 }
Stefan Weilf3a52e52009-12-20 16:52:22 +0100907 tx_command(s);
ths663e8e52007-04-02 12:35:34 +0000908 break;
909 case CmdTDR:
Stefan Weilaac443e2009-09-19 12:11:36 +0200910 TRACE(OTHER, logout("load microcode\n"));
ths663e8e52007-04-02 12:35:34 +0000911 /* Starting with offset 8, the command contains
912 * 64 dwords microcode which we just ignore here. */
913 break;
Stefan Weilf80a7fc2010-03-02 22:37:58 +0100914 case CmdDiagnose:
915 TRACE(OTHER, logout("diagnose\n"));
916 /* Make sure error flag is not set. */
917 s->tx.status = 0;
918 break;
ths663e8e52007-04-02 12:35:34 +0000919 default:
920 missing("undefined command");
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200921 ok_status = 0;
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200922 break;
ths663e8e52007-04-02 12:35:34 +0000923 }
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200924 /* Write new status. */
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100925 stw_le_pci_dma(&s->dev, s->cb_address,
926 s->tx.status | ok_status | STATUS_C);
ths663e8e52007-04-02 12:35:34 +0000927 if (bit_i) {
928 /* CU completed action. */
929 eepro100_cx_interrupt(s);
930 }
931 if (bit_el) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200932 /* CU becomes idle. Terminate command loop. */
ths663e8e52007-04-02 12:35:34 +0000933 set_cu_state(s, cu_idle);
934 eepro100_cna_interrupt(s);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200935 break;
ths663e8e52007-04-02 12:35:34 +0000936 } else if (bit_s) {
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200937 /* CU becomes suspended. Terminate command loop. */
ths663e8e52007-04-02 12:35:34 +0000938 set_cu_state(s, cu_suspended);
939 eepro100_cna_interrupt(s);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200940 break;
ths663e8e52007-04-02 12:35:34 +0000941 } else {
942 /* More entries in list. */
Stefan Weilaac443e2009-09-19 12:11:36 +0200943 TRACE(OTHER, logout("CU list with at least one more entry\n"));
ths663e8e52007-04-02 12:35:34 +0000944 }
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200945 }
946 TRACE(OTHER, logout("CU list empty\n"));
947 /* List is empty. Now CU is idle or suspended. */
948}
949
950static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
951{
Stefan Weilcb25a3f2010-03-02 22:37:54 +0100952 cu_state_t cu_state;
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200953 switch (val) {
954 case CU_NOP:
955 /* No operation. */
956 break;
957 case CU_START:
Stefan Weilcb25a3f2010-03-02 22:37:54 +0100958 cu_state = get_cu_state(s);
959 if (cu_state != cu_idle && cu_state != cu_suspended) {
960 /* Intel documentation says that CU must be idle or suspended
961 * for the CU start command. */
962 logout("unexpected CU state is %u\n", cu_state);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200963 }
964 set_cu_state(s, cu_active);
Stefan Weil27a05002011-04-30 22:40:10 +0200965 s->cu_offset = e100_read_reg4(s, SCBPointer);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200966 action_command(s);
ths663e8e52007-04-02 12:35:34 +0000967 break;
968 case CU_RESUME:
969 if (get_cu_state(s) != cu_suspended) {
970 logout("bad CU resume from CU state %u\n", get_cu_state(s));
971 /* Workaround for bad Linux eepro100 driver which resumes
972 * from idle state. */
Stefan Weile7493b22010-03-02 22:37:59 +0100973#if 0
974 missing("cu resume");
975#endif
ths663e8e52007-04-02 12:35:34 +0000976 set_cu_state(s, cu_suspended);
977 }
978 if (get_cu_state(s) == cu_suspended) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200979 TRACE(OTHER, logout("CU resuming\n"));
ths663e8e52007-04-02 12:35:34 +0000980 set_cu_state(s, cu_active);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200981 action_command(s);
ths663e8e52007-04-02 12:35:34 +0000982 }
983 break;
984 case CU_STATSADDR:
985 /* Load dump counters address. */
Stefan Weil27a05002011-04-30 22:40:10 +0200986 s->statsaddr = e100_read_reg4(s, SCBPointer);
Stefan Weilc16ada92011-11-23 22:20:30 +0100987 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
988 if (s->statsaddr & 3) {
989 /* Memory must be Dword aligned. */
990 logout("unaligned dump counters address\n");
991 /* Handling of misaligned addresses is undefined.
992 * Here we align the address by ignoring the lower bits. */
993 /* TODO: Test unaligned dump counter address on real hardware. */
994 s->statsaddr &= ~3;
995 }
ths663e8e52007-04-02 12:35:34 +0000996 break;
997 case CU_SHOWSTATS:
998 /* Dump statistical counters. */
Stefan Weilaac443e2009-09-19 12:11:36 +0200999 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
ths663e8e52007-04-02 12:35:34 +00001000 dump_statistics(s);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001001 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
ths663e8e52007-04-02 12:35:34 +00001002 break;
1003 case CU_CMD_BASE:
1004 /* Load CU base. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001005 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
Stefan Weil27a05002011-04-30 22:40:10 +02001006 s->cu_base = e100_read_reg4(s, SCBPointer);
ths663e8e52007-04-02 12:35:34 +00001007 break;
1008 case CU_DUMPSTATS:
1009 /* Dump and reset statistical counters. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001010 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
ths663e8e52007-04-02 12:35:34 +00001011 dump_statistics(s);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001012 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
ths663e8e52007-04-02 12:35:34 +00001013 memset(&s->statistics, 0, sizeof(s->statistics));
1014 break;
1015 case CU_SRESUME:
1016 /* CU static resume. */
1017 missing("CU static resume");
1018 break;
1019 default:
1020 missing("Undefined CU command");
1021 }
1022}
1023
1024static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1025{
1026 switch (val) {
1027 case RU_NOP:
1028 /* No operation. */
1029 break;
1030 case RX_START:
1031 /* RU start. */
1032 if (get_ru_state(s) != ru_idle) {
1033 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
Stefan Weile7493b22010-03-02 22:37:59 +01001034#if 0
1035 assert(!"wrong RU state");
1036#endif
ths663e8e52007-04-02 12:35:34 +00001037 }
1038 set_ru_state(s, ru_ready);
Stefan Weil27a05002011-04-30 22:40:10 +02001039 s->ru_offset = e100_read_reg4(s, SCBPointer);
Stefan Weilaac443e2009-09-19 12:11:36 +02001040 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
ths663e8e52007-04-02 12:35:34 +00001041 break;
1042 case RX_RESUME:
1043 /* Restart RU. */
1044 if (get_ru_state(s) != ru_suspended) {
1045 logout("RU state is %u, should be %u\n", get_ru_state(s),
1046 ru_suspended);
Stefan Weile7493b22010-03-02 22:37:59 +01001047#if 0
1048 assert(!"wrong RU state");
1049#endif
ths663e8e52007-04-02 12:35:34 +00001050 }
1051 set_ru_state(s, ru_ready);
1052 break;
Stefan Weile8240122010-03-02 22:37:53 +01001053 case RU_ABORT:
1054 /* RU abort. */
1055 if (get_ru_state(s) == ru_ready) {
1056 eepro100_rnr_interrupt(s);
1057 }
1058 set_ru_state(s, ru_idle);
1059 break;
ths663e8e52007-04-02 12:35:34 +00001060 case RX_ADDR_LOAD:
1061 /* Load RU base. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001062 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
Stefan Weil27a05002011-04-30 22:40:10 +02001063 s->ru_base = e100_read_reg4(s, SCBPointer);
ths663e8e52007-04-02 12:35:34 +00001064 break;
1065 default:
1066 logout("val=0x%02x (undefined RU command)\n", val);
1067 missing("Undefined SU command");
1068 }
1069}
1070
1071static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1072{
1073 eepro100_ru_command(s, val & 0x0f);
1074 eepro100_cu_command(s, val & 0xf0);
1075 if ((val) == 0) {
Stefan Weilaac443e2009-09-19 12:11:36 +02001076 TRACE(OTHER, logout("val=0x%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001077 }
1078 /* Clear command byte after command was accepted. */
1079 s->mem[SCBCmd] = 0;
1080}
1081
1082/*****************************************************************************
1083 *
1084 * EEPROM emulation.
1085 *
1086 ****************************************************************************/
1087
1088#define EEPROM_CS 0x02
1089#define EEPROM_SK 0x01
1090#define EEPROM_DI 0x04
1091#define EEPROM_DO 0x08
1092
1093static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1094{
Stefan Weile5e23ab2011-04-30 22:40:08 +02001095 uint16_t val = e100_read_reg2(s, SCBeeprom);
ths663e8e52007-04-02 12:35:34 +00001096 if (eeprom93xx_read(s->eeprom)) {
1097 val |= EEPROM_DO;
1098 } else {
1099 val &= ~EEPROM_DO;
1100 }
Stefan Weilaac443e2009-09-19 12:11:36 +02001101 TRACE(EEPROM, logout("val=0x%04x\n", val));
ths663e8e52007-04-02 12:35:34 +00001102 return val;
1103}
1104
Anthony Liguoric227f092009-10-01 16:12:16 -05001105static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
ths663e8e52007-04-02 12:35:34 +00001106{
Stefan Weilaac443e2009-09-19 12:11:36 +02001107 TRACE(EEPROM, logout("val=0x%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001108
Stefan Weilebabb672011-04-26 10:29:36 +02001109 /* mask unwritable bits */
Stefan Weile7493b22010-03-02 22:37:59 +01001110#if 0
1111 val = SET_MASKED(val, 0x31, eeprom->value);
1112#endif
ths663e8e52007-04-02 12:35:34 +00001113
1114 int eecs = ((val & EEPROM_CS) != 0);
1115 int eesk = ((val & EEPROM_SK) != 0);
1116 int eedi = ((val & EEPROM_DI) != 0);
1117 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1118}
1119
ths663e8e52007-04-02 12:35:34 +00001120/*****************************************************************************
1121 *
1122 * MDI emulation.
1123 *
1124 ****************************************************************************/
1125
1126#if defined(DEBUG_EEPRO100)
Reimar Döffinger6a0b9cc2009-09-12 15:20:24 +00001127static const char * const mdi_op_name[] = {
ths663e8e52007-04-02 12:35:34 +00001128 "opcode 0",
1129 "write",
1130 "read",
1131 "opcode 3"
1132};
1133
Reimar Döffinger6a0b9cc2009-09-12 15:20:24 +00001134static const char * const mdi_reg_name[] = {
ths663e8e52007-04-02 12:35:34 +00001135 "Control",
1136 "Status",
1137 "PHY Identification (Word 1)",
1138 "PHY Identification (Word 2)",
1139 "Auto-Negotiation Advertisement",
1140 "Auto-Negotiation Link Partner Ability",
1141 "Auto-Negotiation Expansion"
1142};
Stefan Weilaac443e2009-09-19 12:11:36 +02001143
1144static const char *reg2name(uint8_t reg)
1145{
1146 static char buffer[10];
1147 const char *p = buffer;
1148 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1149 p = mdi_reg_name[reg];
1150 } else {
1151 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1152 }
1153 return p;
1154}
ths663e8e52007-04-02 12:35:34 +00001155#endif /* DEBUG_EEPRO100 */
1156
1157static uint32_t eepro100_read_mdi(EEPRO100State * s)
1158{
Stefan Weile5e23ab2011-04-30 22:40:08 +02001159 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
ths663e8e52007-04-02 12:35:34 +00001160
1161#ifdef DEBUG_EEPRO100
1162 uint8_t raiseint = (val & BIT(29)) >> 29;
1163 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1164 uint8_t phy = (val & BITS(25, 21)) >> 21;
1165 uint8_t reg = (val & BITS(20, 16)) >> 16;
1166 uint16_t data = (val & BITS(15, 0));
1167#endif
1168 /* Emulation takes no time to finish MDI transaction. */
1169 val |= BIT(28);
1170 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1171 val, raiseint, mdi_op_name[opcode], phy,
Stefan Weilaac443e2009-09-19 12:11:36 +02001172 reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001173 return val;
1174}
1175
Stefan Weil0113f482011-04-30 22:40:11 +02001176static void eepro100_write_mdi(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +00001177{
Stefan Weil0113f482011-04-30 22:40:11 +02001178 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
ths663e8e52007-04-02 12:35:34 +00001179 uint8_t raiseint = (val & BIT(29)) >> 29;
1180 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1181 uint8_t phy = (val & BITS(25, 21)) >> 21;
1182 uint8_t reg = (val & BITS(20, 16)) >> 16;
1183 uint16_t data = (val & BITS(15, 0));
Stefan Weilaac443e2009-09-19 12:11:36 +02001184 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1185 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001186 if (phy != 1) {
1187 /* Unsupported PHY address. */
Stefan Weile7493b22010-03-02 22:37:59 +01001188#if 0
1189 logout("phy must be 1 but is %u\n", phy);
1190#endif
ths663e8e52007-04-02 12:35:34 +00001191 data = 0;
1192 } else if (opcode != 1 && opcode != 2) {
1193 /* Unsupported opcode. */
1194 logout("opcode must be 1 or 2 but is %u\n", opcode);
1195 data = 0;
1196 } else if (reg > 6) {
1197 /* Unsupported register. */
1198 logout("register must be 0...6 but is %u\n", reg);
1199 data = 0;
1200 } else {
1201 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1202 val, raiseint, mdi_op_name[opcode], phy,
Stefan Weilaac443e2009-09-19 12:11:36 +02001203 reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001204 if (opcode == 1) {
1205 /* MDI write */
1206 switch (reg) {
1207 case 0: /* Control Register */
1208 if (data & 0x8000) {
1209 /* Reset status and control registers to default. */
1210 s->mdimem[0] = eepro100_mdi_default[0];
1211 s->mdimem[1] = eepro100_mdi_default[1];
1212 data = s->mdimem[reg];
1213 } else {
1214 /* Restart Auto Configuration = Normal Operation */
1215 data &= ~0x0200;
1216 }
1217 break;
1218 case 1: /* Status Register */
1219 missing("not writable");
1220 data = s->mdimem[reg];
1221 break;
1222 case 2: /* PHY Identification Register (Word 1) */
1223 case 3: /* PHY Identification Register (Word 2) */
1224 missing("not implemented");
1225 break;
1226 case 4: /* Auto-Negotiation Advertisement Register */
1227 case 5: /* Auto-Negotiation Link Partner Ability Register */
1228 break;
1229 case 6: /* Auto-Negotiation Expansion Register */
1230 default:
1231 missing("not implemented");
1232 }
1233 s->mdimem[reg] = data;
1234 } else if (opcode == 2) {
1235 /* MDI read */
1236 switch (reg) {
1237 case 0: /* Control Register */
1238 if (data & 0x8000) {
1239 /* Reset status and control registers to default. */
1240 s->mdimem[0] = eepro100_mdi_default[0];
1241 s->mdimem[1] = eepro100_mdi_default[1];
1242 }
1243 break;
1244 case 1: /* Status Register */
1245 s->mdimem[reg] |= 0x0020;
1246 break;
1247 case 2: /* PHY Identification Register (Word 1) */
1248 case 3: /* PHY Identification Register (Word 2) */
1249 case 4: /* Auto-Negotiation Advertisement Register */
1250 break;
1251 case 5: /* Auto-Negotiation Link Partner Ability Register */
1252 s->mdimem[reg] = 0x41fe;
1253 break;
1254 case 6: /* Auto-Negotiation Expansion Register */
1255 s->mdimem[reg] = 0x0001;
1256 break;
1257 }
1258 data = s->mdimem[reg];
1259 }
1260 /* Emulation takes no time to finish MDI transaction.
1261 * Set MDI bit in SCB status register. */
1262 s->mem[SCBAck] |= 0x08;
1263 val |= BIT(28);
1264 if (raiseint) {
1265 eepro100_mdi_interrupt(s);
1266 }
1267 }
1268 val = (val & 0xffff0000) + data;
Stefan Weile5e23ab2011-04-30 22:40:08 +02001269 e100_write_reg4(s, SCBCtrlMDI, val);
ths663e8e52007-04-02 12:35:34 +00001270}
1271
1272/*****************************************************************************
1273 *
1274 * Port emulation.
1275 *
1276 ****************************************************************************/
1277
1278#define PORT_SOFTWARE_RESET 0
1279#define PORT_SELFTEST 1
1280#define PORT_SELECTIVE_RESET 2
1281#define PORT_DUMP 3
1282#define PORT_SELECTION_MASK 3
1283
1284typedef struct {
1285 uint32_t st_sign; /* Self Test Signature */
1286 uint32_t st_result; /* Self Test Results */
Anthony Liguoric227f092009-10-01 16:12:16 -05001287} eepro100_selftest_t;
ths663e8e52007-04-02 12:35:34 +00001288
1289static uint32_t eepro100_read_port(EEPRO100State * s)
1290{
1291 return 0;
1292}
1293
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001294static void eepro100_write_port(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +00001295{
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001296 uint32_t val = e100_read_reg4(s, SCBPort);
ths663e8e52007-04-02 12:35:34 +00001297 uint32_t address = (val & ~PORT_SELECTION_MASK);
1298 uint8_t selection = (val & PORT_SELECTION_MASK);
1299 switch (selection) {
1300 case PORT_SOFTWARE_RESET:
1301 nic_reset(s);
1302 break;
1303 case PORT_SELFTEST:
Stefan Weilaac443e2009-09-19 12:11:36 +02001304 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
Anthony Liguoric227f092009-10-01 16:12:16 -05001305 eepro100_selftest_t data;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001306 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
ths663e8e52007-04-02 12:35:34 +00001307 data.st_sign = 0xffffffff;
1308 data.st_result = 0;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001309 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
ths663e8e52007-04-02 12:35:34 +00001310 break;
1311 case PORT_SELECTIVE_RESET:
Stefan Weilaac443e2009-09-19 12:11:36 +02001312 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
ths663e8e52007-04-02 12:35:34 +00001313 nic_selective_reset(s);
1314 break;
1315 default:
1316 logout("val=0x%08x\n", val);
1317 missing("unknown port selection");
1318 }
1319}
1320
1321/*****************************************************************************
1322 *
1323 * General hardware emulation.
1324 *
1325 ****************************************************************************/
1326
1327static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1328{
Blue Swirlef476062010-10-13 18:38:07 +00001329 uint8_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001330 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001331 val = s->mem[addr];
ths663e8e52007-04-02 12:35:34 +00001332 }
1333
1334 switch (addr) {
1335 case SCBStatus:
ths663e8e52007-04-02 12:35:34 +00001336 case SCBAck:
Stefan Weilaac443e2009-09-19 12:11:36 +02001337 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001338 break;
1339 case SCBCmd:
Stefan Weilaac443e2009-09-19 12:11:36 +02001340 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
Stefan Weile7493b22010-03-02 22:37:59 +01001341#if 0
1342 val = eepro100_read_command(s);
1343#endif
ths663e8e52007-04-02 12:35:34 +00001344 break;
1345 case SCBIntmask:
Stefan Weilaac443e2009-09-19 12:11:36 +02001346 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001347 break;
1348 case SCBPort + 3:
Stefan Weilaac443e2009-09-19 12:11:36 +02001349 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001350 break;
1351 case SCBeeprom:
1352 val = eepro100_read_eeprom(s);
1353 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001354 case SCBCtrlMDI:
1355 case SCBCtrlMDI + 1:
1356 case SCBCtrlMDI + 2:
1357 case SCBCtrlMDI + 3:
1358 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1359 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1360 break;
Stefan Weil0908bba2010-03-02 22:37:42 +01001361 case SCBpmdr: /* Power Management Driver Register */
ths663e8e52007-04-02 12:35:34 +00001362 val = 0;
Stefan Weilaac443e2009-09-19 12:11:36 +02001363 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001364 break;
Stefan Weila39bd012011-04-30 22:40:12 +02001365 case SCBgctrl: /* General Control Register */
1366 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1367 break;
Stefan Weil0908bba2010-03-02 22:37:42 +01001368 case SCBgstat: /* General Status Register */
ths663e8e52007-04-02 12:35:34 +00001369 /* 100 Mbps full duplex, valid link */
1370 val = 0x07;
Stefan Weilaac443e2009-09-19 12:11:36 +02001371 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001372 break;
1373 default:
1374 logout("addr=%s val=0x%02x\n", regname(addr), val);
1375 missing("unknown byte read");
1376 }
1377 return val;
1378}
1379
1380static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1381{
Blue Swirlef476062010-10-13 18:38:07 +00001382 uint16_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001383 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001384 val = e100_read_reg2(s, addr);
ths663e8e52007-04-02 12:35:34 +00001385 }
1386
ths663e8e52007-04-02 12:35:34 +00001387 switch (addr) {
1388 case SCBStatus:
=?UTF-8?q?Reimar=20D=C3=B6ffinger?=dbbaaff2009-10-02 18:39:41 +02001389 case SCBCmd:
Stefan Weilaac443e2009-09-19 12:11:36 +02001390 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001391 break;
1392 case SCBeeprom:
1393 val = eepro100_read_eeprom(s);
Stefan Weilaac443e2009-09-19 12:11:36 +02001394 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001395 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001396 case SCBCtrlMDI:
1397 case SCBCtrlMDI + 2:
1398 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1399 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1400 break;
ths663e8e52007-04-02 12:35:34 +00001401 default:
1402 logout("addr=%s val=0x%04x\n", regname(addr), val);
1403 missing("unknown word read");
1404 }
1405 return val;
1406}
1407
1408static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1409{
Blue Swirlef476062010-10-13 18:38:07 +00001410 uint32_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001411 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001412 val = e100_read_reg4(s, addr);
ths663e8e52007-04-02 12:35:34 +00001413 }
1414
1415 switch (addr) {
1416 case SCBStatus:
Stefan Weilaac443e2009-09-19 12:11:36 +02001417 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001418 break;
1419 case SCBPointer:
Stefan Weilaac443e2009-09-19 12:11:36 +02001420 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001421 break;
1422 case SCBPort:
1423 val = eepro100_read_port(s);
Stefan Weilaac443e2009-09-19 12:11:36 +02001424 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001425 break;
Stefan Weil072476e2011-04-30 22:40:13 +02001426 case SCBflash:
1427 val = eepro100_read_eeprom(s);
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
ths663e8e52007-04-02 12:35:34 +00001430 case SCBCtrlMDI:
1431 val = eepro100_read_mdi(s);
1432 break;
1433 default:
1434 logout("addr=%s val=0x%08x\n", regname(addr), val);
1435 missing("unknown longword read");
1436 }
1437 return val;
1438}
1439
1440static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1441{
Stefan Weile74818f2010-04-06 13:44:01 +02001442 /* SCBStatus is readonly. */
1443 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001444 s->mem[addr] = val;
ths663e8e52007-04-02 12:35:34 +00001445 }
1446
ths663e8e52007-04-02 12:35:34 +00001447 switch (addr) {
1448 case SCBStatus:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001449 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001450 break;
1451 case SCBAck:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001452 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001453 eepro100_acknowledge(s);
1454 break;
1455 case SCBCmd:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001456 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001457 eepro100_write_command(s, val);
1458 break;
1459 case SCBIntmask:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001460 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001461 if (val & BIT(1)) {
1462 eepro100_swi_interrupt(s);
1463 }
1464 eepro100_interrupt(s, 0);
1465 break;
Stefan Weil27a05002011-04-30 22:40:10 +02001466 case SCBPointer:
1467 case SCBPointer + 1:
1468 case SCBPointer + 2:
1469 case SCBPointer + 3:
1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1471 break;
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001472 case SCBPort:
1473 case SCBPort + 1:
1474 case SCBPort + 2:
1475 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1476 break;
ths663e8e52007-04-02 12:35:34 +00001477 case SCBPort + 3:
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001478 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1479 eepro100_write_port(s);
1480 break;
Stefan Weilaac443e2009-09-19 12:11:36 +02001481 case SCBFlow: /* does not exist on 82557 */
ths3257d2b2007-09-14 22:22:13 +00001482 case SCBFlow + 1:
1483 case SCBFlow + 2:
Stefan Weil0908bba2010-03-02 22:37:42 +01001484 case SCBpmdr: /* does not exist on 82557 */
Stefan Weilaac443e2009-09-19 12:11:36 +02001485 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001486 break;
1487 case SCBeeprom:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001488 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001489 eepro100_write_eeprom(s->eeprom, val);
1490 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001491 case SCBCtrlMDI:
1492 case SCBCtrlMDI + 1:
1493 case SCBCtrlMDI + 2:
1494 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1495 break;
1496 case SCBCtrlMDI + 3:
1497 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1498 eepro100_write_mdi(s);
1499 break;
ths663e8e52007-04-02 12:35:34 +00001500 default:
1501 logout("addr=%s val=0x%02x\n", regname(addr), val);
1502 missing("unknown byte write");
1503 }
1504}
1505
1506static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1507{
Stefan Weile74818f2010-04-06 13:44:01 +02001508 /* SCBStatus is readonly. */
1509 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001510 e100_write_reg2(s, addr, val);
ths663e8e52007-04-02 12:35:34 +00001511 }
1512
ths663e8e52007-04-02 12:35:34 +00001513 switch (addr) {
1514 case SCBStatus:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001515 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
Stefan Weile74818f2010-04-06 13:44:01 +02001516 s->mem[SCBAck] = (val >> 8);
ths663e8e52007-04-02 12:35:34 +00001517 eepro100_acknowledge(s);
1518 break;
1519 case SCBCmd:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001520 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001521 eepro100_write_command(s, val);
1522 eepro100_write1(s, SCBIntmask, val >> 8);
1523 break;
Stefan Weil27a05002011-04-30 22:40:10 +02001524 case SCBPointer:
1525 case SCBPointer + 2:
1526 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1527 break;
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001528 case SCBPort:
1529 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1530 break;
1531 case SCBPort + 2:
1532 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1533 eepro100_write_port(s);
1534 break;
ths663e8e52007-04-02 12:35:34 +00001535 case SCBeeprom:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001536 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001537 eepro100_write_eeprom(s->eeprom, val);
1538 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001539 case SCBCtrlMDI:
1540 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1541 break;
1542 case SCBCtrlMDI + 2:
1543 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1544 eepro100_write_mdi(s);
1545 break;
ths663e8e52007-04-02 12:35:34 +00001546 default:
1547 logout("addr=%s val=0x%04x\n", regname(addr), val);
1548 missing("unknown word write");
1549 }
1550}
1551
1552static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1553{
1554 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001555 e100_write_reg4(s, addr, val);
ths663e8e52007-04-02 12:35:34 +00001556 }
1557
1558 switch (addr) {
1559 case SCBPointer:
Stefan Weil27a05002011-04-30 22:40:10 +02001560 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001561 break;
1562 case SCBPort:
Stefan Weilaac443e2009-09-19 12:11:36 +02001563 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001564 eepro100_write_port(s);
ths663e8e52007-04-02 12:35:34 +00001565 break;
Stefan Weil072476e2011-04-30 22:40:13 +02001566 case SCBflash:
1567 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1568 val = val >> 16;
1569 eepro100_write_eeprom(s->eeprom, val);
1570 break;
ths663e8e52007-04-02 12:35:34 +00001571 case SCBCtrlMDI:
Stefan Weil0113f482011-04-30 22:40:11 +02001572 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1573 eepro100_write_mdi(s);
ths663e8e52007-04-02 12:35:34 +00001574 break;
1575 default:
1576 logout("addr=%s val=0x%08x\n", regname(addr), val);
1577 missing("unknown longword write");
1578 }
1579}
1580
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001581static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
1582 unsigned size)
ths663e8e52007-04-02 12:35:34 +00001583{
1584 EEPRO100State *s = opaque;
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001585
1586 switch (size) {
1587 case 1: return eepro100_read1(s, addr);
1588 case 2: return eepro100_read2(s, addr);
1589 case 4: return eepro100_read4(s, addr);
1590 default: abort();
1591 }
ths663e8e52007-04-02 12:35:34 +00001592}
1593
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001594static void eepro100_write(void *opaque, target_phys_addr_t addr,
1595 uint64_t data, unsigned size)
ths663e8e52007-04-02 12:35:34 +00001596{
1597 EEPRO100State *s = opaque;
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001598
1599 switch (size) {
1600 case 1: return eepro100_write1(s, addr, data);
1601 case 2: return eepro100_write2(s, addr, data);
1602 case 4: return eepro100_write4(s, addr, data);
1603 default: abort();
1604 }
ths663e8e52007-04-02 12:35:34 +00001605}
1606
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001607static const MemoryRegionOps eepro100_ops = {
1608 .read = eepro100_read,
1609 .write = eepro100_write,
1610 .endianness = DEVICE_LITTLE_ENDIAN,
ths663e8e52007-04-02 12:35:34 +00001611};
1612
Mark McLoughline00e3652009-11-25 18:49:16 +00001613static int nic_can_receive(VLANClientState *nc)
ths663e8e52007-04-02 12:35:34 +00001614{
Mark McLoughline00e3652009-11-25 18:49:16 +00001615 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
Stefan Weilaac443e2009-09-19 12:11:36 +02001616 TRACE(RXTX, logout("%p\n", s));
ths663e8e52007-04-02 12:35:34 +00001617 return get_ru_state(s) == ru_ready;
Stefan Weile7493b22010-03-02 22:37:59 +01001618#if 0
1619 return !eepro100_buffer_full(s);
1620#endif
ths663e8e52007-04-02 12:35:34 +00001621}
1622
Mark McLoughline00e3652009-11-25 18:49:16 +00001623static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
ths663e8e52007-04-02 12:35:34 +00001624{
1625 /* TODO:
1626 * - Magic packets should set bit 30 in power management driver register.
1627 * - Interesting packets should set bit 29 in power management driver register.
1628 */
Mark McLoughline00e3652009-11-25 18:49:16 +00001629 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
ths663e8e52007-04-02 12:35:34 +00001630 uint16_t rfd_status = 0xa000;
Stefan Weil792f1d62011-04-30 22:40:07 +02001631#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1632 uint8_t min_buf[60];
1633#endif
ths663e8e52007-04-02 12:35:34 +00001634 static const uint8_t broadcast_macaddr[6] =
1635 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1636
Stefan Weil792f1d62011-04-30 22:40:07 +02001637#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1638 /* Pad to minimum Ethernet frame length */
1639 if (size < sizeof(min_buf)) {
1640 memcpy(min_buf, buf, size);
1641 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1642 buf = min_buf;
1643 size = sizeof(min_buf);
1644 }
1645#endif
1646
ths663e8e52007-04-02 12:35:34 +00001647 if (s->configuration[8] & 0x80) {
1648 /* CSMA is disabled. */
1649 logout("%p received while CSMA is disabled\n", s);
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001650 return -1;
Stefan Weil792f1d62011-04-30 22:40:07 +02001651#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
Stefan Weilced52962010-03-02 22:37:49 +01001652 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
ths663e8e52007-04-02 12:35:34 +00001653 /* Short frame and configuration byte 7/0 (discard short receive) set:
1654 * Short frame is discarded */
Stefan Weil067d01d2009-09-19 12:37:51 +02001655 logout("%p received short frame (%zu byte)\n", s, size);
ths663e8e52007-04-02 12:35:34 +00001656 s->statistics.rx_short_frame_errors++;
Stefan Weile7493b22010-03-02 22:37:59 +01001657 return -1;
1658#endif
Stefan Weilced52962010-03-02 22:37:49 +01001659 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
ths663e8e52007-04-02 12:35:34 +00001660 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1661 * Long frames are discarded. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001662 logout("%p received long frame (%zu byte), ignored\n", s, size);
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001663 return -1;
Stefan Weile7493b22010-03-02 22:37:59 +01001664 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
ths663e8e52007-04-02 12:35:34 +00001665 /* Frame matches individual address. */
1666 /* TODO: check configuration byte 15/4 (ignore U/L). */
Stefan Weil067d01d2009-09-19 12:37:51 +02001667 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001668 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1669 /* Broadcast frame. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001670 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001671 rfd_status |= 0x0002;
Stefan Weil7b8737d2009-12-20 16:52:24 +01001672 } else if (buf[0] & 0x01) {
ths663e8e52007-04-02 12:35:34 +00001673 /* Multicast frame. */
Stefan Weil7b8737d2009-12-20 16:52:24 +01001674 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001675 if (s->configuration[21] & BIT(3)) {
Stefan Weil7b8737d2009-12-20 16:52:24 +01001676 /* Multicast all bit is set, receive all multicast frames. */
1677 } else {
1678 unsigned mcast_idx = compute_mcast_idx(buf);
1679 assert(mcast_idx < 64);
1680 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1681 /* Multicast frame is allowed in hash table. */
Stefan Weilced52962010-03-02 22:37:49 +01001682 } else if (s->configuration[15] & BIT(0)) {
Stefan Weil7b8737d2009-12-20 16:52:24 +01001683 /* Promiscuous: receive all. */
1684 rfd_status |= 0x0004;
1685 } else {
1686 TRACE(RXTX, logout("%p multicast ignored\n", s));
1687 return -1;
1688 }
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001689 }
Stefan Weil7b8737d2009-12-20 16:52:24 +01001690 /* TODO: Next not for promiscuous mode? */
ths663e8e52007-04-02 12:35:34 +00001691 rfd_status |= 0x0002;
Stefan Weilced52962010-03-02 22:37:49 +01001692 } else if (s->configuration[15] & BIT(0)) {
ths663e8e52007-04-02 12:35:34 +00001693 /* Promiscuous: receive all. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001694 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001695 rfd_status |= 0x0004;
Stefan Weil010ec622010-09-29 21:59:55 +02001696 } else if (s->configuration[20] & BIT(6)) {
1697 /* Multiple IA bit set. */
1698 unsigned mcast_idx = compute_mcast_idx(buf);
1699 assert(mcast_idx < 64);
1700 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1701 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1702 } else {
1703 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1704 return -1;
1705 }
ths663e8e52007-04-02 12:35:34 +00001706 } else {
Stefan Weil067d01d2009-09-19 12:37:51 +02001707 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
Stefan Weilaac443e2009-09-19 12:11:36 +02001708 nic_dump(buf, size)));
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001709 return size;
ths663e8e52007-04-02 12:35:34 +00001710 }
1711
1712 if (get_ru_state(s) != ru_ready) {
Stefan Weilaac443e2009-09-19 12:11:36 +02001713 /* No resources available. */
1714 logout("no resources, state=%u\n", get_ru_state(s));
Stefan Weile8240122010-03-02 22:37:53 +01001715 /* TODO: RNR interrupt only at first failed frame? */
1716 eepro100_rnr_interrupt(s);
ths663e8e52007-04-02 12:35:34 +00001717 s->statistics.rx_resource_errors++;
Stefan Weile7493b22010-03-02 22:37:59 +01001718#if 0
1719 assert(!"no resources");
1720#endif
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001721 return -1;
ths663e8e52007-04-02 12:35:34 +00001722 }
Stefan Weile7493b22010-03-02 22:37:59 +01001723 /* !!! */
Anthony Liguoric227f092009-10-01 16:12:16 -05001724 eepro100_rx_t rx;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001725 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
David Gibsone965d4b2011-11-04 12:03:32 +11001726 &rx, sizeof(eepro100_rx_t));
ths663e8e52007-04-02 12:35:34 +00001727 uint16_t rfd_command = le16_to_cpu(rx.command);
1728 uint16_t rfd_size = le16_to_cpu(rx.size);
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001729
1730 if (size > rfd_size) {
1731 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1732 "(%zu bytes); data truncated\n", rfd_size, size);
1733 size = rfd_size;
1734 }
Stefan Weil792f1d62011-04-30 22:40:07 +02001735#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
ths663e8e52007-04-02 12:35:34 +00001736 if (size < 64) {
1737 rfd_status |= 0x0080;
1738 }
Stefan Weil792f1d62011-04-30 22:40:07 +02001739#endif
Stefan Weilaac443e2009-09-19 12:11:36 +02001740 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1741 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001742 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1743 offsetof(eepro100_rx_t, status), rfd_status);
1744 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1745 offsetof(eepro100_rx_t, count), size);
ths663e8e52007-04-02 12:35:34 +00001746 /* Early receive interrupt not supported. */
Stefan Weile7493b22010-03-02 22:37:59 +01001747#if 0
1748 eepro100_er_interrupt(s);
1749#endif
ths663e8e52007-04-02 12:35:34 +00001750 /* Receive CRC Transfer not supported. */
Stefan Weilced52962010-03-02 22:37:49 +01001751 if (s->configuration[18] & BIT(2)) {
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001752 missing("Receive CRC Transfer");
1753 return -1;
1754 }
ths663e8e52007-04-02 12:35:34 +00001755 /* TODO: check stripping enable bit. */
Stefan Weile7493b22010-03-02 22:37:59 +01001756#if 0
1757 assert(!(s->configuration[17] & BIT(0)));
1758#endif
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001759 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1760 sizeof(eepro100_rx_t), buf, size);
ths663e8e52007-04-02 12:35:34 +00001761 s->statistics.rx_good_frames++;
1762 eepro100_fr_interrupt(s);
1763 s->ru_offset = le32_to_cpu(rx.link);
Stefan Weilced52962010-03-02 22:37:49 +01001764 if (rfd_command & COMMAND_EL) {
ths663e8e52007-04-02 12:35:34 +00001765 /* EL bit is set, so this was the last frame. */
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001766 logout("receive: Running out of frames\n");
1767 set_ru_state(s, ru_suspended);
ths663e8e52007-04-02 12:35:34 +00001768 }
Stefan Weilced52962010-03-02 22:37:49 +01001769 if (rfd_command & COMMAND_S) {
ths663e8e52007-04-02 12:35:34 +00001770 /* S bit is set. */
1771 set_ru_state(s, ru_suspended);
1772 }
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001773 return size;
ths663e8e52007-04-02 12:35:34 +00001774}
1775
Juan Quintela151b2982009-10-19 15:37:57 +02001776static const VMStateDescription vmstate_eepro100 = {
1777 .version_id = 3,
1778 .minimum_version_id = 2,
1779 .minimum_version_id_old = 2,
1780 .fields = (VMStateField []) {
1781 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1782 VMSTATE_UNUSED(32),
1783 VMSTATE_BUFFER(mult, EEPRO100State),
1784 VMSTATE_BUFFER(mem, EEPRO100State),
1785 /* Save all members of struct between scb_stat and mem. */
1786 VMSTATE_UINT8(scb_stat, EEPRO100State),
1787 VMSTATE_UINT8(int_stat, EEPRO100State),
1788 VMSTATE_UNUSED(3*4),
1789 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1790 VMSTATE_UNUSED(19*4),
1791 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1792 /* The eeprom should be saved and restored by its own routines. */
1793 VMSTATE_UINT32(device, EEPRO100State),
1794 /* TODO check device. */
Juan Quintela151b2982009-10-19 15:37:57 +02001795 VMSTATE_UINT32(cu_base, EEPRO100State),
1796 VMSTATE_UINT32(cu_offset, EEPRO100State),
1797 VMSTATE_UINT32(ru_base, EEPRO100State),
1798 VMSTATE_UINT32(ru_offset, EEPRO100State),
1799 VMSTATE_UINT32(statsaddr, EEPRO100State),
Stefan Weilba42b642009-10-30 13:36:21 +01001800 /* Save eepro100_stats_t statistics. */
Juan Quintela151b2982009-10-19 15:37:57 +02001801 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1807 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1808 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1809 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1815 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1816 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1817 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1818 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1819 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1820 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1821 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
Juan Quintela151b2982009-10-19 15:37:57 +02001822 /* Configuration bytes. */
1823 VMSTATE_BUFFER(configuration, EEPRO100State),
1824 VMSTATE_END_OF_LIST()
Stefan Weilaac443e2009-09-19 12:11:36 +02001825 }
Juan Quintela151b2982009-10-19 15:37:57 +02001826};
ths663e8e52007-04-02 12:35:34 +00001827
Mark McLoughline00e3652009-11-25 18:49:16 +00001828static void nic_cleanup(VLANClientState *nc)
aliguorib946a152009-04-17 17:11:08 +00001829{
Mark McLoughline00e3652009-11-25 18:49:16 +00001830 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
aliguorib946a152009-04-17 17:11:08 +00001831
Mark McLoughline00e3652009-11-25 18:49:16 +00001832 s->nic = NULL;
aliguorib946a152009-04-17 17:11:08 +00001833}
1834
Stefan Weilc4c270e2009-09-19 13:02:09 +02001835static int pci_nic_uninit(PCIDevice *pci_dev)
aliguorib946a152009-04-17 17:11:08 +00001836{
Stefan Weilc4c270e2009-09-19 13:02:09 +02001837 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
aliguorib946a152009-04-17 17:11:08 +00001838
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001839 memory_region_destroy(&s->mmio_bar);
1840 memory_region_destroy(&s->io_bar);
1841 memory_region_destroy(&s->flash_bar);
Alex Williamson0be71e32010-06-25 11:09:07 -06001842 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
Alex Williamson5fce2b32010-06-25 11:09:21 -06001843 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
Mark McLoughline00e3652009-11-25 18:49:16 +00001844 qemu_del_vlan_client(&s->nic->nc);
aliguorib946a152009-04-17 17:11:08 +00001845 return 0;
1846}
1847
Mark McLoughline00e3652009-11-25 18:49:16 +00001848static NetClientInfo net_eepro100_info = {
1849 .type = NET_CLIENT_TYPE_NIC,
1850 .size = sizeof(NICState),
1851 .can_receive = nic_can_receive,
1852 .receive = nic_receive,
1853 .cleanup = nic_cleanup,
1854};
1855
Stefan Weil558c8632010-04-06 13:44:03 +02001856static int e100_nic_init(PCIDevice *pci_dev)
ths663e8e52007-04-02 12:35:34 +00001857{
Juan Quintela273a2142009-08-24 18:42:37 +02001858 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
Anthony Liguori40021f02011-12-04 12:22:06 -06001859 E100PCIDeviceInfo *info = eepro100_get_class(s);
ths663e8e52007-04-02 12:35:34 +00001860
Stefan Weilaac443e2009-09-19 12:11:36 +02001861 TRACE(OTHER, logout("\n"));
ths663e8e52007-04-02 12:35:34 +00001862
Anthony Liguori40021f02011-12-04 12:22:06 -06001863 s->device = info->device;
ths663e8e52007-04-02 12:35:34 +00001864
Anthony Liguori40021f02011-12-04 12:22:06 -06001865 e100_pci_reset(s);
ths663e8e52007-04-02 12:35:34 +00001866
1867 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1868 * i82559 and later support 64 or 256 word EEPROM. */
Alex Williamson5fce2b32010-06-25 11:09:21 -06001869 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
ths663e8e52007-04-02 12:35:34 +00001870
1871 /* Handler for memory-mapped I/O */
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001872 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1873 PCI_MEM_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001874 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001875 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1876 PCI_IO_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001877 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001878 /* FIXME: flash aliases to mmio?! */
1879 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1880 PCI_FLASH_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001881 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
ths663e8e52007-04-02 12:35:34 +00001882
Gerd Hoffmann508ef932009-10-21 15:25:36 +02001883 qemu_macaddr_default_if_unset(&s->conf.macaddr);
Stefan Weilce0e58b2010-03-02 22:37:41 +01001884 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
ths663e8e52007-04-02 12:35:34 +00001885
1886 nic_reset(s);
1887
Mark McLoughline00e3652009-11-25 18:49:16 +00001888 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
Anthony Liguorif79f2bf2011-12-04 11:17:51 -06001889 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
ths663e8e52007-04-02 12:35:34 +00001890
Mark McLoughline00e3652009-11-25 18:49:16 +00001891 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1892 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
ths663e8e52007-04-02 12:35:34 +00001893
Jan Kiszkaa08d4362009-06-27 09:25:07 +02001894 qemu_register_reset(nic_reset, s);
ths663e8e52007-04-02 12:35:34 +00001895
Anthony Liguori7267c092011-08-20 22:09:37 -05001896 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
Juan Quintela151b2982009-10-19 15:37:57 +02001897 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
Mark McLoughline00e3652009-11-25 18:49:16 +00001898 s->vmstate->name = s->nic->nc.model;
Alex Williamson0be71e32010-06-25 11:09:07 -06001899 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
Stefan Weil4e9df062009-10-31 13:38:33 +01001900
Gleb Natapov1ca4d092010-12-08 13:35:05 +02001901 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1902
Gerd Hoffmann81a322d2009-08-14 10:36:05 +02001903 return 0;
ths663e8e52007-04-02 12:35:34 +00001904}
1905
Stefan Weil558c8632010-04-06 13:44:03 +02001906static E100PCIDeviceInfo e100_devices[] = {
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001907 {
Anthony Liguori39bffca2011-12-07 21:34:16 -06001908 .name = "i82550",
1909 .desc = "Intel i82550 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001910 .device = i82550,
1911 /* TODO: check device id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001912 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02001913 /* Revision ID: 0x0c, 0x0d, 0x0e. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001914 .revision = 0x0e,
Stefan Weil558c8632010-04-06 13:44:03 +02001915 /* TODO: check size of statistical counters. */
1916 .stats_size = 80,
1917 /* TODO: check extended tcb support. */
1918 .has_extended_tcb_support = true,
1919 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001920 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001921 .name = "i82551",
1922 .desc = "Intel i82551 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001923 .device = i82551,
Anthony Liguori40021f02011-12-04 12:22:06 -06001924 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02001925 /* Revision ID: 0x0f, 0x10. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001926 .revision = 0x0f,
Stefan Weil558c8632010-04-06 13:44:03 +02001927 /* TODO: check size of statistical counters. */
1928 .stats_size = 80,
1929 .has_extended_tcb_support = true,
1930 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001931 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001932 .name = "i82557a",
1933 .desc = "Intel i82557A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001934 .device = i82557A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001935 .device_id = PCI_DEVICE_ID_INTEL_82557,
1936 .revision = 0x01,
Stefan Weil558c8632010-04-06 13:44:03 +02001937 .power_management = false,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001938 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001939 .name = "i82557b",
1940 .desc = "Intel i82557B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001941 .device = i82557B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001942 .device_id = PCI_DEVICE_ID_INTEL_82557,
1943 .revision = 0x02,
Stefan Weil558c8632010-04-06 13:44:03 +02001944 .power_management = false,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001945 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001946 .name = "i82557c",
1947 .desc = "Intel i82557C Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001948 .device = i82557C,
Anthony Liguori40021f02011-12-04 12:22:06 -06001949 .device_id = PCI_DEVICE_ID_INTEL_82557,
1950 .revision = 0x03,
Stefan Weil558c8632010-04-06 13:44:03 +02001951 .power_management = false,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001952 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001953 .name = "i82558a",
1954 .desc = "Intel i82558A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001955 .device = i82558A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001956 .device_id = PCI_DEVICE_ID_INTEL_82557,
1957 .revision = 0x04,
Stefan Weil558c8632010-04-06 13:44:03 +02001958 .stats_size = 76,
1959 .has_extended_tcb_support = true,
1960 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001961 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001962 .name = "i82558b",
1963 .desc = "Intel i82558B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001964 .device = i82558B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001965 .device_id = PCI_DEVICE_ID_INTEL_82557,
1966 .revision = 0x05,
Stefan Weil558c8632010-04-06 13:44:03 +02001967 .stats_size = 76,
1968 .has_extended_tcb_support = true,
1969 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001970 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001971 .name = "i82559a",
1972 .desc = "Intel i82559A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001973 .device = i82559A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001974 .device_id = PCI_DEVICE_ID_INTEL_82557,
1975 .revision = 0x06,
Stefan Weil558c8632010-04-06 13:44:03 +02001976 .stats_size = 80,
1977 .has_extended_tcb_support = true,
1978 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001979 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001980 .name = "i82559b",
1981 .desc = "Intel i82559B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001982 .device = i82559B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001983 .device_id = PCI_DEVICE_ID_INTEL_82557,
1984 .revision = 0x07,
Stefan Weil558c8632010-04-06 13:44:03 +02001985 .stats_size = 80,
1986 .has_extended_tcb_support = true,
1987 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001988 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001989 .name = "i82559c",
1990 .desc = "Intel i82559C Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001991 .device = i82559C,
Anthony Liguori40021f02011-12-04 12:22:06 -06001992 .device_id = PCI_DEVICE_ID_INTEL_82557,
Stefan Weil558c8632010-04-06 13:44:03 +02001993#if 0
Anthony Liguori40021f02011-12-04 12:22:06 -06001994 .revision = 0x08,
Stefan Weil558c8632010-04-06 13:44:03 +02001995#endif
1996 /* TODO: Windows wants revision id 0x0c. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001997 .revision = 0x0c,
Isaku Yamahataad035022011-05-25 10:58:00 +09001998#if EEPROM_SIZE > 0
Anthony Liguori40021f02011-12-04 12:22:06 -06001999 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
2000 .subsystem_id = 0x0040,
Isaku Yamahataad035022011-05-25 10:58:00 +09002001#endif
Stefan Weil558c8632010-04-06 13:44:03 +02002002 .stats_size = 80,
2003 .has_extended_tcb_support = true,
2004 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02002005 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002006 .name = "i82559er",
2007 .desc = "Intel i82559ER Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02002008 .device = i82559ER,
Anthony Liguori40021f02011-12-04 12:22:06 -06002009 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2010 .revision = 0x09,
Stefan Weil558c8632010-04-06 13:44:03 +02002011 .stats_size = 80,
2012 .has_extended_tcb_support = true,
2013 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02002014 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002015 .name = "i82562",
2016 .desc = "Intel i82562 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02002017 .device = i82562,
2018 /* TODO: check device id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06002019 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02002020 /* TODO: wrong revision id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06002021 .revision = 0x0e,
Stefan Weil558c8632010-04-06 13:44:03 +02002022 .stats_size = 80,
2023 .has_extended_tcb_support = true,
2024 .power_management = true,
Stefan Weildb667a12010-04-06 13:44:04 +02002025 },{
2026 /* Toshiba Tecra 8200. */
Anthony Liguori39bffca2011-12-07 21:34:16 -06002027 .name = "i82801",
2028 .desc = "Intel i82801 Ethernet",
Stefan Weildb667a12010-04-06 13:44:04 +02002029 .device = i82801,
Anthony Liguori40021f02011-12-04 12:22:06 -06002030 .device_id = 0x2449,
2031 .revision = 0x03,
Stefan Weildb667a12010-04-06 13:44:04 +02002032 .stats_size = 80,
2033 .has_extended_tcb_support = true,
2034 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02002035 }
2036};
2037
Anthony Liguori40021f02011-12-04 12:22:06 -06002038static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2039{
2040 E100PCIDeviceInfo *info = NULL;
2041 int i;
2042
2043 /* This is admittedly awkward but also temporary. QOM allows for
2044 * parameterized typing and for subclassing both of which would suitable
2045 * handle what's going on here. But class_data is already being used as
2046 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2047 * right now. Once we merge the final QOM series, we can come back here and
2048 * do this in a much more elegant fashion.
2049 */
2050 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002051 if (strcmp(e100_devices[i].name, typename) == 0) {
Anthony Liguori40021f02011-12-04 12:22:06 -06002052 info = &e100_devices[i];
2053 break;
2054 }
2055 }
2056 assert(info != NULL);
2057
2058 return info;
2059}
2060
2061static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2062{
2063 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2064}
2065
Anthony Liguori39bffca2011-12-07 21:34:16 -06002066static Property e100_properties[] = {
2067 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2068 DEFINE_PROP_END_OF_LIST(),
2069};
2070
Anthony Liguori40021f02011-12-04 12:22:06 -06002071static void eepro100_class_init(ObjectClass *klass, void *data)
2072{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002073 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06002074 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2075 E100PCIDeviceInfo *info;
2076
2077 info = eepro100_get_class_by_name(object_class_get_name(klass));
2078
Anthony Liguori39bffca2011-12-07 21:34:16 -06002079 dc->props = e100_properties;
2080 dc->desc = info->desc;
Anthony Liguori40021f02011-12-04 12:22:06 -06002081 k->vendor_id = PCI_VENDOR_ID_INTEL;
2082 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2083 k->romfile = "pxe-eepro100.rom";
2084 k->init = e100_nic_init;
2085 k->exit = pci_nic_uninit;
2086 k->device_id = info->device_id;
2087 k->revision = info->revision;
2088 k->subsystem_vendor_id = info->subsystem_vendor_id;
2089 k->subsystem_id = info->subsystem_id;
2090}
2091
Paul Brook9d07d752009-05-14 22:35:07 +01002092static void eepro100_register_devices(void)
2093{
Stefan Weil558c8632010-04-06 13:44:03 +02002094 size_t i;
2095 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002096 TypeInfo type_info = {};
2097 E100PCIDeviceInfo *info = &e100_devices[i];
Anthony Liguori40021f02011-12-04 12:22:06 -06002098
Anthony Liguori39bffca2011-12-07 21:34:16 -06002099 type_info.name = info->name;
2100 type_info.parent = TYPE_PCI_DEVICE;
2101 type_info.class_init = eepro100_class_init;
2102 type_info.instance_size = sizeof(EEPRO100State);
Anthony Liguori40021f02011-12-04 12:22:06 -06002103
Anthony Liguori39bffca2011-12-07 21:34:16 -06002104 type_register(&type_info);
Stefan Weil558c8632010-04-06 13:44:03 +02002105 }
Paul Brook9d07d752009-05-14 22:35:07 +01002106}
2107
2108device_init(eepro100_register_devices)