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bellard80cabfa2004-03-14 12:20:30 +00001/*
aliguori81174da2008-08-11 14:17:04 +00002 * QEMU 16550A UART emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard80cabfa2004-03-14 12:20:30 +00004 * Copyright (c) 2003-2004 Fabrice Bellard
aliguori81174da2008-08-11 14:17:04 +00005 * Copyright (c) 2008 Citrix Systems, Inc.
ths5fafdf22007-09-16 21:08:06 +00006 *
bellard80cabfa2004-03-14 12:20:30 +00007 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
26#include "qemu-char.h"
27#include "isa.h"
28#include "pc.h"
aurel326936bfe2008-05-04 21:42:00 +000029#include "qemu-timer.h"
Markus Armbruster666daa62010-06-02 18:48:27 +020030#include "sysemu.h"
bellard80cabfa2004-03-14 12:20:30 +000031
32//#define DEBUG_SERIAL
33
34#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
35
36#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
37#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
38#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
39#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
40
41#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
42#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
43
44#define UART_IIR_MSI 0x00 /* Modem status interrupt */
45#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
46#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
47#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
aliguori81174da2008-08-11 14:17:04 +000048#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
49
50#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
51#define UART_IIR_FE 0xC0 /* Fifo enabled */
bellard80cabfa2004-03-14 12:20:30 +000052
53/*
54 * These are the definitions for the Modem Control Register
55 */
56#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
57#define UART_MCR_OUT2 0x08 /* Out2 complement */
58#define UART_MCR_OUT1 0x04 /* Out1 complement */
59#define UART_MCR_RTS 0x02 /* RTS complement */
60#define UART_MCR_DTR 0x01 /* DTR complement */
61
62/*
63 * These are the definitions for the Modem Status Register
64 */
65#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
66#define UART_MSR_RI 0x40 /* Ring Indicator */
67#define UART_MSR_DSR 0x20 /* Data Set Ready */
68#define UART_MSR_CTS 0x10 /* Clear to Send */
69#define UART_MSR_DDCD 0x08 /* Delta DCD */
70#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
71#define UART_MSR_DDSR 0x02 /* Delta DSR */
72#define UART_MSR_DCTS 0x01 /* Delta CTS */
73#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
74
75#define UART_LSR_TEMT 0x40 /* Transmitter empty */
76#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
77#define UART_LSR_BI 0x10 /* Break interrupt indicator */
78#define UART_LSR_FE 0x08 /* Frame error indicator */
79#define UART_LSR_PE 0x04 /* Parity error indicator */
80#define UART_LSR_OE 0x02 /* Overrun error indicator */
81#define UART_LSR_DR 0x01 /* Receiver data ready */
aliguori81174da2008-08-11 14:17:04 +000082#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
bellard80cabfa2004-03-14 12:20:30 +000083
aliguori81174da2008-08-11 14:17:04 +000084/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
85
86#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
87#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
88#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
89#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
90
91#define UART_FCR_DMS 0x08 /* DMA Mode Select */
92#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
93#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
94#define UART_FCR_FE 0x01 /* FIFO Enable */
95
96#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
97
98#define XMIT_FIFO 0
99#define RECV_FIFO 1
100#define MAX_XMIT_RETRY 4
101
Michal Novotnyb6601142010-09-13 14:32:32 +0200102#ifdef DEBUG_SERIAL
103#define DPRINTF(fmt, ...) \
Stefan Weil46411f82010-09-13 21:21:57 +0200104do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
Michal Novotnyb6601142010-09-13 14:32:32 +0200105#else
106#define DPRINTF(fmt, ...) \
Stefan Weil46411f82010-09-13 21:21:57 +0200107do {} while (0)
Michal Novotnyb6601142010-09-13 14:32:32 +0200108#endif
109
Juan Quintela2b321d62009-09-23 01:18:59 +0200110typedef struct SerialFIFO {
aliguori81174da2008-08-11 14:17:04 +0000111 uint8_t data[UART_FIFO_LENGTH];
112 uint8_t count;
113 uint8_t itl; /* Interrupt Trigger Level */
114 uint8_t tail;
115 uint8_t head;
Juan Quintela2b321d62009-09-23 01:18:59 +0200116} SerialFIFO;
aurel326936bfe2008-05-04 21:42:00 +0000117
bellardb41a2cd2004-03-14 21:46:48 +0000118struct SerialState {
bellard508d92d2006-08-26 18:00:36 +0000119 uint16_t divider;
bellard80cabfa2004-03-14 12:20:30 +0000120 uint8_t rbr; /* receive register */
aliguori81174da2008-08-11 14:17:04 +0000121 uint8_t thr; /* transmit holding register */
122 uint8_t tsr; /* transmit shift register */
bellard80cabfa2004-03-14 12:20:30 +0000123 uint8_t ier;
124 uint8_t iir; /* read only */
125 uint8_t lcr;
126 uint8_t mcr;
127 uint8_t lsr; /* read only */
bellard3e749fe2006-04-12 20:42:42 +0000128 uint8_t msr; /* read only */
bellard80cabfa2004-03-14 12:20:30 +0000129 uint8_t scr;
aliguori81174da2008-08-11 14:17:04 +0000130 uint8_t fcr;
Juan Quintela747791f2009-09-10 03:04:46 +0200131 uint8_t fcr_vmstate; /* we can't write directly this value
132 it has side effects */
bellard80cabfa2004-03-14 12:20:30 +0000133 /* NOTE: this hidden state is necessary for tx irq generation as
134 it can be reset while reading iir */
135 int thr_ipending;
pbrookd537cf62007-04-07 18:14:41 +0000136 qemu_irq irq;
bellard82c643f2004-07-14 17:28:13 +0000137 CharDriverState *chr;
bellardf8d179e2005-11-08 22:30:36 +0000138 int last_break_enable;
bellarde5d13e22005-11-23 21:11:49 +0000139 int it_shift;
aurel32b6cd0ea2008-05-04 21:42:11 +0000140 int baudbase;
aliguori81174da2008-08-11 14:17:04 +0000141 int tsr_retry;
Gerd Hoffmann9826fd52012-02-23 13:45:23 +0100142 uint32_t wakeup;
aliguori81174da2008-08-11 14:17:04 +0000143
144 uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
145 SerialFIFO recv_fifo;
146 SerialFIFO xmit_fifo;
147
148 struct QEMUTimer *fifo_timeout_timer;
149 int timeout_ipending; /* timeout interrupt pending state */
150 struct QEMUTimer *transmit_timer;
151
152
153 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
154 int poll_msl;
155
156 struct QEMUTimer *modem_status_poll;
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700157 MemoryRegion io;
bellardb41a2cd2004-03-14 21:46:48 +0000158};
bellard80cabfa2004-03-14 12:20:30 +0000159
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200160typedef struct ISASerialState {
161 ISADevice dev;
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200162 uint32_t index;
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200163 uint32_t iobase;
164 uint32_t isairq;
165 SerialState state;
166} ISASerialState;
167
aliguori81174da2008-08-11 14:17:04 +0000168static void serial_receive1(void *opaque, const uint8_t *buf, int size);
169
170static void fifo_clear(SerialState *s, int fifo)
171{
172 SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
173 memset(f->data, 0, UART_FIFO_LENGTH);
174 f->count = 0;
175 f->head = 0;
176 f->tail = 0;
177}
178
179static int fifo_put(SerialState *s, int fifo, uint8_t chr)
180{
181 SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
182
Justin T. Gibbs71e605f2010-02-10 14:35:54 -0700183 /* Receive overruns do not overwrite FIFO contents. */
184 if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
aliguori81174da2008-08-11 14:17:04 +0000185
Justin T. Gibbs71e605f2010-02-10 14:35:54 -0700186 f->data[f->head++] = chr;
187
188 if (f->head == UART_FIFO_LENGTH)
189 f->head = 0;
190 }
191
192 if (f->count < UART_FIFO_LENGTH)
193 f->count++;
194 else if (fifo == RECV_FIFO)
195 s->lsr |= UART_LSR_OE;
aliguori81174da2008-08-11 14:17:04 +0000196
197 return 1;
198}
199
200static uint8_t fifo_get(SerialState *s, int fifo)
201{
202 SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
203 uint8_t c;
204
205 if(f->count == 0)
206 return 0;
207
208 c = f->data[f->tail++];
209 if (f->tail == UART_FIFO_LENGTH)
210 f->tail = 0;
211 f->count--;
212
213 return c;
214}
balrogb2a51602008-02-10 13:40:52 +0000215
bellardb41a2cd2004-03-14 21:46:48 +0000216static void serial_update_irq(SerialState *s)
bellard80cabfa2004-03-14 12:20:30 +0000217{
aliguori81174da2008-08-11 14:17:04 +0000218 uint8_t tmp_iir = UART_IIR_NO_INT;
219
aliguori81174da2008-08-11 14:17:04 +0000220 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
221 tmp_iir = UART_IIR_RLSI;
balrog5628a622008-09-17 00:21:05 +0000222 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
balrogc9a33052008-09-20 01:15:04 +0000223 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
224 * this is not in the specification but is observed on existing
225 * hardware. */
aliguori81174da2008-08-11 14:17:04 +0000226 tmp_iir = UART_IIR_CTI;
Juergen Lock2d6ee8e2009-09-12 18:52:22 +0200227 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
228 (!(s->fcr & UART_FCR_FE) ||
229 s->recv_fifo.count >= s->recv_fifo.itl)) {
230 tmp_iir = UART_IIR_RDI;
aliguori81174da2008-08-11 14:17:04 +0000231 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
232 tmp_iir = UART_IIR_THRI;
233 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
234 tmp_iir = UART_IIR_MSI;
235 }
236
237 s->iir = tmp_iir | (s->iir & 0xF0);
238
239 if (tmp_iir != UART_IIR_NO_INT) {
pbrookd537cf62007-04-07 18:14:41 +0000240 qemu_irq_raise(s->irq);
bellard80cabfa2004-03-14 12:20:30 +0000241 } else {
pbrookd537cf62007-04-07 18:14:41 +0000242 qemu_irq_lower(s->irq);
bellard80cabfa2004-03-14 12:20:30 +0000243 }
244}
245
bellardf8d179e2005-11-08 22:30:36 +0000246static void serial_update_parameters(SerialState *s)
247{
aliguori81174da2008-08-11 14:17:04 +0000248 int speed, parity, data_bits, stop_bits, frame_size;
bellard2122c512005-11-10 23:58:33 +0000249 QEMUSerialSetParams ssp;
bellardf8d179e2005-11-08 22:30:36 +0000250
aliguori81174da2008-08-11 14:17:04 +0000251 if (s->divider == 0)
252 return;
253
Stefan Weil718b8ae2009-10-26 21:51:41 +0100254 /* Start bit. */
aliguori81174da2008-08-11 14:17:04 +0000255 frame_size = 1;
bellardf8d179e2005-11-08 22:30:36 +0000256 if (s->lcr & 0x08) {
Stefan Weil718b8ae2009-10-26 21:51:41 +0100257 /* Parity bit. */
258 frame_size++;
bellardf8d179e2005-11-08 22:30:36 +0000259 if (s->lcr & 0x10)
260 parity = 'E';
261 else
262 parity = 'O';
263 } else {
264 parity = 'N';
265 }
ths5fafdf22007-09-16 21:08:06 +0000266 if (s->lcr & 0x04)
bellardf8d179e2005-11-08 22:30:36 +0000267 stop_bits = 2;
268 else
269 stop_bits = 1;
aliguori81174da2008-08-11 14:17:04 +0000270
bellardf8d179e2005-11-08 22:30:36 +0000271 data_bits = (s->lcr & 0x03) + 5;
aliguori81174da2008-08-11 14:17:04 +0000272 frame_size += data_bits + stop_bits;
aurel32b6cd0ea2008-05-04 21:42:11 +0000273 speed = s->baudbase / s->divider;
bellard2122c512005-11-10 23:58:33 +0000274 ssp.speed = speed;
275 ssp.parity = parity;
276 ssp.data_bits = data_bits;
277 ssp.stop_bits = stop_bits;
Juan Quintela6ee093c2009-09-10 03:04:26 +0200278 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
Anthony Liguori41084f12011-08-15 11:17:34 -0500279 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
Michal Novotnyb6601142010-09-13 14:32:32 +0200280
281 DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
bellardf8d179e2005-11-08 22:30:36 +0000282 speed, parity, data_bits, stop_bits);
bellardf8d179e2005-11-08 22:30:36 +0000283}
284
aliguori81174da2008-08-11 14:17:04 +0000285static void serial_update_msl(SerialState *s)
286{
287 uint8_t omsr;
288 int flags;
289
290 qemu_del_timer(s->modem_status_poll);
291
Anthony Liguori41084f12011-08-15 11:17:34 -0500292 if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
aliguori81174da2008-08-11 14:17:04 +0000293 s->poll_msl = -1;
294 return;
295 }
296
297 omsr = s->msr;
298
299 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
300 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
301 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
302 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
303
304 if (s->msr != omsr) {
305 /* Set delta bits */
306 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
307 /* UART_MSR_TERI only if change was from 1 -> 0 */
308 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
309 s->msr &= ~UART_MSR_TERI;
310 serial_update_irq(s);
311 }
312
313 /* The real 16550A apparently has a 250ns response latency to line status changes.
314 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
315
316 if (s->poll_msl)
Paolo Bonzini74475452011-03-11 16:47:48 +0100317 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
aliguori81174da2008-08-11 14:17:04 +0000318}
319
320static void serial_xmit(void *opaque)
321{
322 SerialState *s = opaque;
Paolo Bonzini74475452011-03-11 16:47:48 +0100323 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
aliguori81174da2008-08-11 14:17:04 +0000324
325 if (s->tsr_retry <= 0) {
326 if (s->fcr & UART_FCR_FE) {
327 s->tsr = fifo_get(s,XMIT_FIFO);
328 if (!s->xmit_fifo.count)
329 s->lsr |= UART_LSR_THRE;
Anthony Liguori67c53222012-04-01 14:03:21 -0500330 } else if ((s->lsr & UART_LSR_THRE)) {
331 return;
aliguori81174da2008-08-11 14:17:04 +0000332 } else {
333 s->tsr = s->thr;
334 s->lsr |= UART_LSR_THRE;
Anthony Liguoridfe844c2012-04-01 14:18:30 -0500335 s->lsr &= ~UART_LSR_TEMT;
aliguori81174da2008-08-11 14:17:04 +0000336 }
337 }
338
339 if (s->mcr & UART_MCR_LOOP) {
340 /* in loopback mode, say that we just received a char */
341 serial_receive1(s, &s->tsr, 1);
Anthony Liguori2cc6e0a2011-08-15 11:17:28 -0500342 } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
Anthony Liguori67c53222012-04-01 14:03:21 -0500343 if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
aliguori81174da2008-08-11 14:17:04 +0000344 s->tsr_retry++;
345 qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time);
346 return;
347 } else if (s->poll_msl < 0) {
348 /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
349 drop any further failed writes instantly, until we get one that goes through.
350 This is to prevent guests that log to unconnected pipes or pty's from stalling. */
351 s->tsr_retry = -1;
352 }
353 }
354 else {
355 s->tsr_retry = 0;
356 }
357
Paolo Bonzini74475452011-03-11 16:47:48 +0100358 s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
aliguori81174da2008-08-11 14:17:04 +0000359 if (!(s->lsr & UART_LSR_THRE))
360 qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
361
362 if (s->lsr & UART_LSR_THRE) {
363 s->lsr |= UART_LSR_TEMT;
364 s->thr_ipending = 1;
365 serial_update_irq(s);
366 }
367}
368
369
bellardb41a2cd2004-03-14 21:46:48 +0000370static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
bellard80cabfa2004-03-14 12:20:30 +0000371{
bellardb41a2cd2004-03-14 21:46:48 +0000372 SerialState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000373
bellard80cabfa2004-03-14 12:20:30 +0000374 addr &= 7;
Michal Novotnyb6601142010-09-13 14:32:32 +0200375 DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
bellard80cabfa2004-03-14 12:20:30 +0000376 switch(addr) {
377 default:
378 case 0:
379 if (s->lcr & UART_LCR_DLAB) {
380 s->divider = (s->divider & 0xff00) | val;
bellardf8d179e2005-11-08 22:30:36 +0000381 serial_update_parameters(s);
bellard80cabfa2004-03-14 12:20:30 +0000382 } else {
aliguori81174da2008-08-11 14:17:04 +0000383 s->thr = (uint8_t) val;
384 if(s->fcr & UART_FCR_FE) {
Aurelien Jarno2f4f22b2010-03-06 20:23:09 +0100385 fifo_put(s, XMIT_FIFO, s->thr);
386 s->thr_ipending = 0;
387 s->lsr &= ~UART_LSR_TEMT;
388 s->lsr &= ~UART_LSR_THRE;
389 serial_update_irq(s);
aurel326936bfe2008-05-04 21:42:00 +0000390 } else {
Aurelien Jarno2f4f22b2010-03-06 20:23:09 +0100391 s->thr_ipending = 0;
392 s->lsr &= ~UART_LSR_THRE;
393 serial_update_irq(s);
balrogb2a51602008-02-10 13:40:52 +0000394 }
aliguori81174da2008-08-11 14:17:04 +0000395 serial_xmit(s);
bellard80cabfa2004-03-14 12:20:30 +0000396 }
397 break;
398 case 1:
399 if (s->lcr & UART_LCR_DLAB) {
400 s->divider = (s->divider & 0x00ff) | (val << 8);
bellardf8d179e2005-11-08 22:30:36 +0000401 serial_update_parameters(s);
bellard80cabfa2004-03-14 12:20:30 +0000402 } else {
bellard60e336d2004-08-24 21:55:28 +0000403 s->ier = val & 0x0f;
aliguori81174da2008-08-11 14:17:04 +0000404 /* If the backend device is a real serial port, turn polling of the modem
405 status lines on physical port on or off depending on UART_IER_MSI state */
406 if (s->poll_msl >= 0) {
407 if (s->ier & UART_IER_MSI) {
408 s->poll_msl = 1;
409 serial_update_msl(s);
410 } else {
411 qemu_del_timer(s->modem_status_poll);
412 s->poll_msl = 0;
413 }
414 }
bellard60e336d2004-08-24 21:55:28 +0000415 if (s->lsr & UART_LSR_THRE) {
416 s->thr_ipending = 1;
aliguori81174da2008-08-11 14:17:04 +0000417 serial_update_irq(s);
bellard60e336d2004-08-24 21:55:28 +0000418 }
bellard80cabfa2004-03-14 12:20:30 +0000419 }
420 break;
421 case 2:
aliguori81174da2008-08-11 14:17:04 +0000422 val = val & 0xFF;
423
424 if (s->fcr == val)
425 break;
426
427 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
428 if ((val ^ s->fcr) & UART_FCR_FE)
429 val |= UART_FCR_XFR | UART_FCR_RFR;
430
431 /* FIFO clear */
432
433 if (val & UART_FCR_RFR) {
434 qemu_del_timer(s->fifo_timeout_timer);
435 s->timeout_ipending=0;
436 fifo_clear(s,RECV_FIFO);
437 }
438
439 if (val & UART_FCR_XFR) {
440 fifo_clear(s,XMIT_FIFO);
441 }
442
443 if (val & UART_FCR_FE) {
444 s->iir |= UART_IIR_FE;
445 /* Set RECV_FIFO trigger Level */
446 switch (val & 0xC0) {
447 case UART_FCR_ITL_1:
448 s->recv_fifo.itl = 1;
449 break;
450 case UART_FCR_ITL_2:
451 s->recv_fifo.itl = 4;
452 break;
453 case UART_FCR_ITL_3:
454 s->recv_fifo.itl = 8;
455 break;
456 case UART_FCR_ITL_4:
457 s->recv_fifo.itl = 14;
458 break;
459 }
460 } else
461 s->iir &= ~UART_IIR_FE;
462
463 /* Set fcr - or at least the bits in it that are supposed to "stick" */
464 s->fcr = val & 0xC9;
465 serial_update_irq(s);
bellard80cabfa2004-03-14 12:20:30 +0000466 break;
467 case 3:
bellardf8d179e2005-11-08 22:30:36 +0000468 {
469 int break_enable;
470 s->lcr = val;
471 serial_update_parameters(s);
472 break_enable = (val >> 6) & 1;
473 if (break_enable != s->last_break_enable) {
474 s->last_break_enable = break_enable;
Anthony Liguori41084f12011-08-15 11:17:34 -0500475 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
bellard2122c512005-11-10 23:58:33 +0000476 &break_enable);
bellardf8d179e2005-11-08 22:30:36 +0000477 }
478 }
bellard80cabfa2004-03-14 12:20:30 +0000479 break;
480 case 4:
aliguori81174da2008-08-11 14:17:04 +0000481 {
482 int flags;
483 int old_mcr = s->mcr;
484 s->mcr = val & 0x1f;
485 if (val & UART_MCR_LOOP)
486 break;
487
488 if (s->poll_msl >= 0 && old_mcr != s->mcr) {
489
Anthony Liguori41084f12011-08-15 11:17:34 -0500490 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
aliguori81174da2008-08-11 14:17:04 +0000491
492 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
493
494 if (val & UART_MCR_RTS)
495 flags |= CHR_TIOCM_RTS;
496 if (val & UART_MCR_DTR)
497 flags |= CHR_TIOCM_DTR;
498
Anthony Liguori41084f12011-08-15 11:17:34 -0500499 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
aliguori81174da2008-08-11 14:17:04 +0000500 /* Update the modem status after a one-character-send wait-time, since there may be a response
501 from the device/computer at the other end of the serial line */
Paolo Bonzini74475452011-03-11 16:47:48 +0100502 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
aliguori81174da2008-08-11 14:17:04 +0000503 }
504 }
bellard80cabfa2004-03-14 12:20:30 +0000505 break;
506 case 5:
507 break;
508 case 6:
bellard80cabfa2004-03-14 12:20:30 +0000509 break;
510 case 7:
511 s->scr = val;
512 break;
513 }
514}
515
bellardb41a2cd2004-03-14 21:46:48 +0000516static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
bellard80cabfa2004-03-14 12:20:30 +0000517{
bellardb41a2cd2004-03-14 21:46:48 +0000518 SerialState *s = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000519 uint32_t ret;
520
521 addr &= 7;
522 switch(addr) {
523 default:
524 case 0:
525 if (s->lcr & UART_LCR_DLAB) {
ths5fafdf22007-09-16 21:08:06 +0000526 ret = s->divider & 0xff;
bellard80cabfa2004-03-14 12:20:30 +0000527 } else {
aliguori81174da2008-08-11 14:17:04 +0000528 if(s->fcr & UART_FCR_FE) {
529 ret = fifo_get(s,RECV_FIFO);
530 if (s->recv_fifo.count == 0)
531 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
532 else
Paolo Bonzini74475452011-03-11 16:47:48 +0100533 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
aliguori81174da2008-08-11 14:17:04 +0000534 s->timeout_ipending = 0;
535 } else {
536 ret = s->rbr;
537 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
538 }
bellardb41a2cd2004-03-14 21:46:48 +0000539 serial_update_irq(s);
balrogb2a51602008-02-10 13:40:52 +0000540 if (!(s->mcr & UART_MCR_LOOP)) {
541 /* in loopback mode, don't receive any data */
542 qemu_chr_accept_input(s->chr);
543 }
bellard80cabfa2004-03-14 12:20:30 +0000544 }
545 break;
546 case 1:
547 if (s->lcr & UART_LCR_DLAB) {
548 ret = (s->divider >> 8) & 0xff;
549 } else {
550 ret = s->ier;
551 }
552 break;
553 case 2:
554 ret = s->iir;
Aurelien Jarnocdee7bd2010-03-06 22:19:53 +0100555 if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
bellard80cabfa2004-03-14 12:20:30 +0000556 s->thr_ipending = 0;
Justin T. Gibbs71e605f2010-02-10 14:35:54 -0700557 serial_update_irq(s);
558 }
bellard80cabfa2004-03-14 12:20:30 +0000559 break;
560 case 3:
561 ret = s->lcr;
562 break;
563 case 4:
564 ret = s->mcr;
565 break;
566 case 5:
567 ret = s->lsr;
Justin T. Gibbs71e605f2010-02-10 14:35:54 -0700568 /* Clear break and overrun interrupts */
569 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
570 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
aliguori81174da2008-08-11 14:17:04 +0000571 serial_update_irq(s);
572 }
bellard80cabfa2004-03-14 12:20:30 +0000573 break;
574 case 6:
575 if (s->mcr & UART_MCR_LOOP) {
576 /* in loopback, the modem output pins are connected to the
577 inputs */
578 ret = (s->mcr & 0x0c) << 4;
579 ret |= (s->mcr & 0x02) << 3;
580 ret |= (s->mcr & 0x01) << 5;
581 } else {
aliguori81174da2008-08-11 14:17:04 +0000582 if (s->poll_msl >= 0)
583 serial_update_msl(s);
bellard80cabfa2004-03-14 12:20:30 +0000584 ret = s->msr;
aliguori81174da2008-08-11 14:17:04 +0000585 /* Clear delta bits & msr int after read, if they were set */
586 if (s->msr & UART_MSR_ANY_DELTA) {
587 s->msr &= 0xF0;
588 serial_update_irq(s);
589 }
bellard80cabfa2004-03-14 12:20:30 +0000590 }
591 break;
592 case 7:
593 ret = s->scr;
594 break;
595 }
Michal Novotnyb6601142010-09-13 14:32:32 +0200596 DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
bellard80cabfa2004-03-14 12:20:30 +0000597 return ret;
598}
599
bellard82c643f2004-07-14 17:28:13 +0000600static int serial_can_receive(SerialState *s)
bellard80cabfa2004-03-14 12:20:30 +0000601{
aliguori81174da2008-08-11 14:17:04 +0000602 if(s->fcr & UART_FCR_FE) {
603 if(s->recv_fifo.count < UART_FIFO_LENGTH)
604 /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
605 advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
606 effectively overriding the ITL that the guest has set. */
607 return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
608 else
609 return 0;
610 } else {
bellard80cabfa2004-03-14 12:20:30 +0000611 return !(s->lsr & UART_LSR_DR);
aliguori81174da2008-08-11 14:17:04 +0000612 }
bellard80cabfa2004-03-14 12:20:30 +0000613}
614
bellard82c643f2004-07-14 17:28:13 +0000615static void serial_receive_break(SerialState *s)
bellard80cabfa2004-03-14 12:20:30 +0000616{
bellard80cabfa2004-03-14 12:20:30 +0000617 s->rbr = 0;
Jason Wessel40ff1622009-05-18 10:00:27 -0500618 /* When the LSR_DR is set a null byte is pushed into the fifo */
619 fifo_put(s, RECV_FIFO, '\0');
bellard80cabfa2004-03-14 12:20:30 +0000620 s->lsr |= UART_LSR_BI | UART_LSR_DR;
bellardb41a2cd2004-03-14 21:46:48 +0000621 serial_update_irq(s);
bellard80cabfa2004-03-14 12:20:30 +0000622}
623
aliguori81174da2008-08-11 14:17:04 +0000624/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
625static void fifo_timeout_int (void *opaque) {
626 SerialState *s = opaque;
627 if (s->recv_fifo.count) {
628 s->timeout_ipending = 1;
629 serial_update_irq(s);
630 }
631}
632
bellardb41a2cd2004-03-14 21:46:48 +0000633static int serial_can_receive1(void *opaque)
bellard80cabfa2004-03-14 12:20:30 +0000634{
bellardb41a2cd2004-03-14 21:46:48 +0000635 SerialState *s = opaque;
636 return serial_can_receive(s);
637}
bellard80cabfa2004-03-14 12:20:30 +0000638
bellardb41a2cd2004-03-14 21:46:48 +0000639static void serial_receive1(void *opaque, const uint8_t *buf, int size)
640{
641 SerialState *s = opaque;
Gerd Hoffmann9826fd52012-02-23 13:45:23 +0100642
643 if (s->wakeup) {
644 qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
645 }
aliguori81174da2008-08-11 14:17:04 +0000646 if(s->fcr & UART_FCR_FE) {
647 int i;
648 for (i = 0; i < size; i++) {
649 fifo_put(s, RECV_FIFO, buf[i]);
650 }
651 s->lsr |= UART_LSR_DR;
652 /* call the timeout receive callback in 4 char transmit time */
Paolo Bonzini74475452011-03-11 16:47:48 +0100653 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
aliguori81174da2008-08-11 14:17:04 +0000654 } else {
Justin T. Gibbs71e605f2010-02-10 14:35:54 -0700655 if (s->lsr & UART_LSR_DR)
656 s->lsr |= UART_LSR_OE;
aliguori81174da2008-08-11 14:17:04 +0000657 s->rbr = buf[0];
658 s->lsr |= UART_LSR_DR;
659 }
660 serial_update_irq(s);
bellardb41a2cd2004-03-14 21:46:48 +0000661}
662
bellard82c643f2004-07-14 17:28:13 +0000663static void serial_event(void *opaque, int event)
664{
665 SerialState *s = opaque;
Michal Novotnyb6601142010-09-13 14:32:32 +0200666 DPRINTF("event %x\n", event);
bellard82c643f2004-07-14 17:28:13 +0000667 if (event == CHR_EVENT_BREAK)
668 serial_receive_break(s);
669}
670
Juan Quintelad4bfa4d2009-09-29 22:48:22 +0200671static void serial_pre_save(void *opaque)
bellard8738a8d2005-11-06 15:48:04 +0000672{
Juan Quintelad4bfa4d2009-09-29 22:48:22 +0200673 SerialState *s = opaque;
Juan Quintela747791f2009-09-10 03:04:46 +0200674 s->fcr_vmstate = s->fcr;
bellard8738a8d2005-11-06 15:48:04 +0000675}
676
Juan Quintelae59fb372009-09-29 22:48:21 +0200677static int serial_post_load(void *opaque, int version_id)
Juan Quintela747791f2009-09-10 03:04:46 +0200678{
679 SerialState *s = opaque;
680
Juan Quintela4c18ce92009-10-16 15:39:58 +0200681 if (version_id < 3) {
682 s->fcr_vmstate = 0;
683 }
Juan Quintela747791f2009-09-10 03:04:46 +0200684 /* Initialize fcr via setter to perform essential side-effects */
685 serial_ioport_write(s, 0x02, s->fcr_vmstate);
Michal Novotny9a7c4872010-09-15 15:35:53 +0200686 serial_update_parameters(s);
Juan Quintela747791f2009-09-10 03:04:46 +0200687 return 0;
688}
689
690static const VMStateDescription vmstate_serial = {
691 .name = "serial",
692 .version_id = 3,
693 .minimum_version_id = 2,
694 .pre_save = serial_pre_save,
Juan Quintela747791f2009-09-10 03:04:46 +0200695 .post_load = serial_post_load,
696 .fields = (VMStateField []) {
697 VMSTATE_UINT16_V(divider, SerialState, 2),
698 VMSTATE_UINT8(rbr, SerialState),
699 VMSTATE_UINT8(ier, SerialState),
700 VMSTATE_UINT8(iir, SerialState),
701 VMSTATE_UINT8(lcr, SerialState),
702 VMSTATE_UINT8(mcr, SerialState),
703 VMSTATE_UINT8(lsr, SerialState),
704 VMSTATE_UINT8(msr, SerialState),
705 VMSTATE_UINT8(scr, SerialState),
706 VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
707 VMSTATE_END_OF_LIST()
708 }
709};
710
balrogb2a51602008-02-10 13:40:52 +0000711static void serial_reset(void *opaque)
712{
713 SerialState *s = opaque;
714
balrogb2a51602008-02-10 13:40:52 +0000715 s->rbr = 0;
716 s->ier = 0;
717 s->iir = UART_IIR_NO_INT;
718 s->lcr = 0;
balrogb2a51602008-02-10 13:40:52 +0000719 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
720 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
Stefan Weil718b8ae2009-10-26 21:51:41 +0100721 /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
aliguori81174da2008-08-11 14:17:04 +0000722 s->divider = 0x0C;
723 s->mcr = UART_MCR_OUT2;
balrogb2a51602008-02-10 13:40:52 +0000724 s->scr = 0;
aliguori81174da2008-08-11 14:17:04 +0000725 s->tsr_retry = 0;
Stefan Weil718b8ae2009-10-26 21:51:41 +0100726 s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
aliguori81174da2008-08-11 14:17:04 +0000727 s->poll_msl = 0;
728
729 fifo_clear(s,RECV_FIFO);
730 fifo_clear(s,XMIT_FIFO);
731
Paolo Bonzini74475452011-03-11 16:47:48 +0100732 s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
balrogb2a51602008-02-10 13:40:52 +0000733
734 s->thr_ipending = 0;
735 s->last_break_enable = 0;
736 qemu_irq_lower(s->irq);
737}
738
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200739static void serial_init_core(SerialState *s)
aliguori81174da2008-08-11 14:17:04 +0000740{
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200741 if (!s->chr) {
Aurelien Jarno387f4a52009-09-15 01:16:28 +0200742 fprintf(stderr, "Can't create serial device, empty char device\n");
743 exit(1);
744 }
745
Paolo Bonzini74475452011-03-11 16:47:48 +0100746 s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
aliguori81174da2008-08-11 14:17:04 +0000747
Paolo Bonzini74475452011-03-11 16:47:48 +0100748 s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
749 s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
aliguori81174da2008-08-11 14:17:04 +0000750
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200751 qemu_register_reset(serial_reset, s);
aliguori81174da2008-08-11 14:17:04 +0000752
aurel32b47543c2009-01-18 14:28:10 +0000753 qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
754 serial_event, s);
aliguori81174da2008-08-11 14:17:04 +0000755}
756
Stefan Weil038eaf82009-10-31 11:28:11 +0100757/* Change the main reference oscillator frequency. */
758void serial_set_frequency(SerialState *s, uint32_t frequency)
759{
760 s->baudbase = frequency;
761 serial_update_parameters(s);
762}
763
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200764static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
765static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
766
Richard Hendersona941ae42011-08-10 15:28:18 -0700767static const MemoryRegionPortio serial_portio[] = {
768 { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write },
769 PORTIO_END_OF_LIST()
770};
771
772static const MemoryRegionOps serial_io_ops = {
773 .old_portio = serial_portio
774};
775
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200776static int serial_isa_initfn(ISADevice *dev)
777{
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200778 static int index;
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200779 ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
780 SerialState *s = &isa->state;
781
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200782 if (isa->index == -1)
783 isa->index = index;
784 if (isa->index >= MAX_SERIAL_PORTS)
785 return -1;
786 if (isa->iobase == -1)
787 isa->iobase = isa_serial_io[isa->index];
788 if (isa->isairq == -1)
789 isa->isairq = isa_serial_irq[isa->index];
790 index++;
791
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200792 s->baudbase = 115200;
793 isa_init_irq(dev, &s->irq, isa->isairq);
794 serial_init_core(s);
Jan Kiszka1cc9f512010-05-15 13:32:41 +0200795 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200796
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700797 memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
798 isa_register_ioport(dev, &s->io, isa->iobase);
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200799 return 0;
800}
801
Jan Kiszka1cc9f512010-05-15 13:32:41 +0200802static const VMStateDescription vmstate_isa_serial = {
803 .name = "serial",
804 .version_id = 3,
805 .minimum_version_id = 2,
806 .fields = (VMStateField []) {
807 VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
808 VMSTATE_END_OF_LIST()
809 }
810};
811
aurel32b6cd0ea2008-05-04 21:42:11 +0000812SerialState *serial_init(int base, qemu_irq irq, int baudbase,
813 CharDriverState *chr)
bellardb41a2cd2004-03-14 21:46:48 +0000814{
815 SerialState *s;
816
Anthony Liguori7267c092011-08-20 22:09:37 -0500817 s = g_malloc0(sizeof(SerialState));
balrogb2a51602008-02-10 13:40:52 +0000818
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200819 s->irq = irq;
820 s->baudbase = baudbase;
821 s->chr = chr;
822 serial_init_core(s);
aurel326936bfe2008-05-04 21:42:00 +0000823
Alex Williamson0be71e32010-06-25 11:09:07 -0600824 vmstate_register(NULL, base, &vmstate_serial, s);
bellard8738a8d2005-11-06 15:48:04 +0000825
bellardb41a2cd2004-03-14 21:46:48 +0000826 register_ioport_write(base, 8, 1, serial_ioport_write, s);
827 register_ioport_read(base, 8, 1, serial_ioport_read, s);
bellardb41a2cd2004-03-14 21:46:48 +0000828 return s;
bellard80cabfa2004-03-14 12:20:30 +0000829}
bellarde5d13e22005-11-23 21:11:49 +0000830
831/* Memory mapped interface */
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700832static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
833 unsigned size)
bellarde5d13e22005-11-23 21:11:49 +0000834{
835 SerialState *s = opaque;
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700836 return serial_ioport_read(s, addr >> s->it_shift);
bellarde5d13e22005-11-23 21:11:49 +0000837}
838
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700839static void serial_mm_write(void *opaque, target_phys_addr_t addr,
840 uint64_t value, unsigned size)
bellarde5d13e22005-11-23 21:11:49 +0000841{
842 SerialState *s = opaque;
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700843 value &= ~0u >> (32 - (size * 8));
pbrook8da3ff12008-12-01 18:59:50 +0000844 serial_ioport_write(s, addr >> s->it_shift, value);
bellarde5d13e22005-11-23 21:11:49 +0000845}
846
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700847static const MemoryRegionOps serial_mm_ops[3] = {
848 [DEVICE_NATIVE_ENDIAN] = {
849 .read = serial_mm_read,
850 .write = serial_mm_write,
851 .endianness = DEVICE_NATIVE_ENDIAN,
852 },
853 [DEVICE_LITTLE_ENDIAN] = {
854 .read = serial_mm_read,
855 .write = serial_mm_write,
856 .endianness = DEVICE_LITTLE_ENDIAN,
857 },
858 [DEVICE_BIG_ENDIAN] = {
859 .read = serial_mm_read,
860 .write = serial_mm_write,
861 .endianness = DEVICE_BIG_ENDIAN,
862 },
bellarde5d13e22005-11-23 21:11:49 +0000863};
864
Richard Henderson39186d82011-08-11 16:07:16 -0700865SerialState *serial_mm_init(MemoryRegion *address_space,
866 target_phys_addr_t base, int it_shift,
867 qemu_irq irq, int baudbase,
868 CharDriverState *chr, enum device_endian end)
bellarde5d13e22005-11-23 21:11:49 +0000869{
870 SerialState *s;
bellarde5d13e22005-11-23 21:11:49 +0000871
Anthony Liguori7267c092011-08-20 22:09:37 -0500872 s = g_malloc0(sizeof(SerialState));
aliguori81174da2008-08-11 14:17:04 +0000873
bellarde5d13e22005-11-23 21:11:49 +0000874 s->it_shift = it_shift;
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200875 s->irq = irq;
876 s->baudbase = baudbase;
877 s->chr = chr;
bellarde5d13e22005-11-23 21:11:49 +0000878
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200879 serial_init_core(s);
Alex Williamson0be71e32010-06-25 11:09:07 -0600880 vmstate_register(NULL, base, &vmstate_serial, s);
bellarde5d13e22005-11-23 21:11:49 +0000881
Richard Henderson8e8ffc42011-08-11 16:18:59 -0700882 memory_region_init_io(&s->io, &serial_mm_ops[end], s,
883 "serial", 8 << it_shift);
Richard Henderson39186d82011-08-11 16:07:16 -0700884 memory_region_add_subregion(address_space, base, &s->io);
Richard Henderson2ff0c7c2011-08-11 16:07:15 -0700885
aliguori81174da2008-08-11 14:17:04 +0000886 serial_update_msl(s);
bellarde5d13e22005-11-23 21:11:49 +0000887 return s;
888}
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200889
Anthony Liguori39bffca2011-12-07 21:34:16 -0600890static Property serial_isa_properties[] = {
891 DEFINE_PROP_UINT32("index", ISASerialState, index, -1),
892 DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1),
893 DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1),
894 DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
Gerd Hoffmann9826fd52012-02-23 13:45:23 +0100895 DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600896 DEFINE_PROP_END_OF_LIST(),
897};
898
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600899static void serial_isa_class_initfn(ObjectClass *klass, void *data)
900{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600901 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600902 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
903 ic->init = serial_isa_initfn;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600904 dc->vmsd = &vmstate_isa_serial;
905 dc->props = serial_isa_properties;
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600906}
907
Anthony Liguori39bffca2011-12-07 21:34:16 -0600908static TypeInfo serial_isa_info = {
909 .name = "isa-serial",
910 .parent = TYPE_ISA_DEVICE,
911 .instance_size = sizeof(ISASerialState),
912 .class_init = serial_isa_class_initfn,
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200913};
914
Andreas Färber83f7d432012-02-09 15:20:55 +0100915static void serial_register_types(void)
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200916{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600917 type_register_static(&serial_isa_info);
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200918}
919
Andreas Färber83f7d432012-02-09 15:20:55 +0100920type_init(serial_register_types)