bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM helper routines |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4 | * Copyright (c) 2005-2007 CodeSourcery, LLC |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 18 | */ |
Blue Swirl | 3e45717 | 2011-07-13 12:44:15 +0000 | [diff] [blame] | 19 | #include "cpu.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 20 | #include "exec/helper-proto.h" |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 21 | #include "internals.h" |
Paolo Bonzini | f08b617 | 2014-03-28 19:42:10 +0100 | [diff] [blame] | 22 | #include "exec/cpu_ldst.h" |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 23 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 24 | #define SIGNBIT (uint32_t)0x80000000 |
| 25 | #define SIGNBIT64 ((uint64_t)1 << 63) |
| 26 | |
Blue Swirl | 1ce94f8 | 2012-09-04 20:08:34 +0000 | [diff] [blame] | 27 | static void raise_exception(CPUARMState *env, int tt) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 28 | { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 29 | ARMCPU *cpu = arm_env_get_cpu(env); |
| 30 | CPUState *cs = CPU(cpu); |
| 31 | |
| 32 | cs->exception_index = tt; |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 33 | cpu_loop_exit(cs); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 34 | } |
| 35 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 36 | uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 37 | uint32_t rn, uint32_t maxindex) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 38 | { |
| 39 | uint32_t val; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 40 | uint32_t tmp; |
| 41 | int index; |
| 42 | int shift; |
| 43 | uint64_t *table; |
| 44 | table = (uint64_t *)&env->vfp.regs[rn]; |
| 45 | val = 0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 46 | for (shift = 0; shift < 32; shift += 8) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 47 | index = (ireg >> shift) & 0xff; |
| 48 | if (index < maxindex) { |
pbrook | 3018f25 | 2008-09-22 00:52:42 +0000 | [diff] [blame] | 49 | tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 50 | val |= tmp << shift; |
| 51 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 52 | val |= def & (0xff << shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 53 | } |
| 54 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 55 | return val; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 56 | } |
| 57 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 58 | #if !defined(CONFIG_USER_ONLY) |
| 59 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 60 | /* try to fill the TLB and return an exception if error. If retaddr is |
Andreas Färber | d5a11fe | 2013-08-27 00:28:06 +0200 | [diff] [blame] | 61 | * NULL, it means that the function was called in C code (i.e. not |
| 62 | * from generated code or from helper.c) |
| 63 | */ |
| 64 | void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, |
Blue Swirl | 2050396 | 2012-04-09 14:20:20 +0000 | [diff] [blame] | 65 | uintptr_t retaddr) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 66 | { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 67 | int ret; |
| 68 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 69 | ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 70 | if (unlikely(ret)) { |
Andreas Färber | d5a11fe | 2013-08-27 00:28:06 +0200 | [diff] [blame] | 71 | ARMCPU *cpu = ARM_CPU(cs); |
| 72 | CPUARMState *env = &cpu->env; |
| 73 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 74 | if (retaddr) { |
| 75 | /* now we have a real cpu fault */ |
Andreas Färber | 3f38f30 | 2013-09-01 16:51:34 +0200 | [diff] [blame] | 76 | cpu_restore_state(cs, retaddr); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 77 | } |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 78 | raise_exception(env, cs->exception_index); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 79 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 80 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 81 | #endif |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 82 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 83 | uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 84 | { |
| 85 | uint32_t res = a + b; |
| 86 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) |
| 87 | env->QF = 1; |
| 88 | return res; |
| 89 | } |
| 90 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 91 | uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 92 | { |
| 93 | uint32_t res = a + b; |
| 94 | if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) { |
| 95 | env->QF = 1; |
| 96 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); |
| 97 | } |
| 98 | return res; |
| 99 | } |
| 100 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 101 | uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 102 | { |
| 103 | uint32_t res = a - b; |
| 104 | if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) { |
| 105 | env->QF = 1; |
| 106 | res = ~(((int32_t)a >> 31) ^ SIGNBIT); |
| 107 | } |
| 108 | return res; |
| 109 | } |
| 110 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 111 | uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 112 | { |
| 113 | uint32_t res; |
| 114 | if (val >= 0x40000000) { |
| 115 | res = ~SIGNBIT; |
| 116 | env->QF = 1; |
| 117 | } else if (val <= (int32_t)0xc0000000) { |
| 118 | res = SIGNBIT; |
| 119 | env->QF = 1; |
| 120 | } else { |
| 121 | res = val << 1; |
| 122 | } |
| 123 | return res; |
| 124 | } |
| 125 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 126 | uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 127 | { |
| 128 | uint32_t res = a + b; |
| 129 | if (res < a) { |
| 130 | env->QF = 1; |
| 131 | res = ~0; |
| 132 | } |
| 133 | return res; |
| 134 | } |
| 135 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 136 | uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 137 | { |
| 138 | uint32_t res = a - b; |
| 139 | if (res > a) { |
| 140 | env->QF = 1; |
| 141 | res = 0; |
| 142 | } |
| 143 | return res; |
| 144 | } |
| 145 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 146 | /* Signed saturation. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 147 | static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 148 | { |
| 149 | int32_t top; |
| 150 | uint32_t mask; |
| 151 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 152 | top = val >> shift; |
| 153 | mask = (1u << shift) - 1; |
| 154 | if (top > 0) { |
| 155 | env->QF = 1; |
| 156 | return mask; |
| 157 | } else if (top < -1) { |
| 158 | env->QF = 1; |
| 159 | return ~mask; |
| 160 | } |
| 161 | return val; |
| 162 | } |
| 163 | |
| 164 | /* Unsigned saturation. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 165 | static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 166 | { |
| 167 | uint32_t max; |
| 168 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 169 | max = (1u << shift) - 1; |
| 170 | if (val < 0) { |
| 171 | env->QF = 1; |
| 172 | return 0; |
| 173 | } else if (val > max) { |
| 174 | env->QF = 1; |
| 175 | return max; |
| 176 | } |
| 177 | return val; |
| 178 | } |
| 179 | |
| 180 | /* Signed saturate. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 181 | uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 182 | { |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 183 | return do_ssat(env, x, shift); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | /* Dual halfword signed saturate. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 187 | uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 188 | { |
| 189 | uint32_t res; |
| 190 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 191 | res = (uint16_t)do_ssat(env, (int16_t)x, shift); |
| 192 | res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 193 | return res; |
| 194 | } |
| 195 | |
| 196 | /* Unsigned saturate. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 197 | uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 198 | { |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 199 | return do_usat(env, x, shift); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | /* Dual halfword unsigned saturate. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 203 | uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 204 | { |
| 205 | uint32_t res; |
| 206 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 207 | res = (uint16_t)do_usat(env, (int16_t)x, shift); |
| 208 | res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 209 | return res; |
| 210 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 211 | |
Blue Swirl | 1ce94f8 | 2012-09-04 20:08:34 +0000 | [diff] [blame] | 212 | void HELPER(wfi)(CPUARMState *env) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 213 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 214 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
| 215 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 216 | cs->exception_index = EXCP_HLT; |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 217 | cs->halted = 1; |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 218 | cpu_loop_exit(cs); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Peter Maydell | 72c1d3a | 2014-03-10 14:56:30 +0000 | [diff] [blame] | 221 | void HELPER(wfe)(CPUARMState *env) |
| 222 | { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 223 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
| 224 | |
Peter Maydell | 72c1d3a | 2014-03-10 14:56:30 +0000 | [diff] [blame] | 225 | /* Don't actually halt the CPU, just yield back to top |
| 226 | * level loop |
| 227 | */ |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 228 | cs->exception_index = EXCP_YIELD; |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 229 | cpu_loop_exit(cs); |
Peter Maydell | 72c1d3a | 2014-03-10 14:56:30 +0000 | [diff] [blame] | 230 | } |
| 231 | |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 232 | /* Raise an internal-to-QEMU exception. This is limited to only |
| 233 | * those EXCP values which are special cases for QEMU to interrupt |
| 234 | * execution and not to be used for exceptions which are passed to |
| 235 | * the guest (those must all have syndrome information and thus should |
| 236 | * use exception_with_syndrome). |
| 237 | */ |
| 238 | void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 239 | { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 240 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
| 241 | |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 242 | assert(excp_is_internal(excp)); |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 243 | cs->exception_index = excp; |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 244 | cpu_loop_exit(cs); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 245 | } |
| 246 | |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 247 | /* Raise an exception with the specified syndrome register value */ |
| 248 | void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, |
| 249 | uint32_t syndrome) |
| 250 | { |
| 251 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
| 252 | |
| 253 | assert(!excp_is_internal(excp)); |
| 254 | cs->exception_index = excp; |
| 255 | env->exception.syndrome = syndrome; |
| 256 | cpu_loop_exit(cs); |
| 257 | } |
| 258 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 259 | uint32_t HELPER(cpsr_read)(CPUARMState *env) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 260 | { |
Peter Maydell | 4051e12 | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 261 | return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 262 | } |
| 263 | |
Blue Swirl | 1ce94f8 | 2012-09-04 20:08:34 +0000 | [diff] [blame] | 264 | void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 265 | { |
| 266 | cpsr_write(env, val, mask); |
| 267 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 268 | |
| 269 | /* Access to user mode registers from privileged modes. */ |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 270 | uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 271 | { |
| 272 | uint32_t val; |
| 273 | |
| 274 | if (regno == 13) { |
| 275 | val = env->banked_r13[0]; |
| 276 | } else if (regno == 14) { |
| 277 | val = env->banked_r14[0]; |
| 278 | } else if (regno >= 8 |
| 279 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 280 | val = env->usr_regs[regno - 8]; |
| 281 | } else { |
| 282 | val = env->regs[regno]; |
| 283 | } |
| 284 | return val; |
| 285 | } |
| 286 | |
Blue Swirl | 1ce94f8 | 2012-09-04 20:08:34 +0000 | [diff] [blame] | 287 | void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 288 | { |
| 289 | if (regno == 13) { |
| 290 | env->banked_r13[0] = val; |
| 291 | } else if (regno == 14) { |
| 292 | env->banked_r14[0] = val; |
| 293 | } else if (regno >= 8 |
| 294 | && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 295 | env->usr_regs[regno - 8] = val; |
| 296 | } else { |
| 297 | env->regs[regno] = val; |
| 298 | } |
| 299 | } |
| 300 | |
Peter Maydell | 8bcbf37 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 301 | void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome) |
Peter Maydell | f59df3f | 2014-02-20 10:35:52 +0000 | [diff] [blame] | 302 | { |
| 303 | const ARMCPRegInfo *ri = rip; |
| 304 | switch (ri->accessfn(env, ri)) { |
| 305 | case CP_ACCESS_OK: |
| 306 | return; |
| 307 | case CP_ACCESS_TRAP: |
Peter Maydell | 8bcbf37 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 308 | env->exception.syndrome = syndrome; |
| 309 | break; |
Peter Maydell | f59df3f | 2014-02-20 10:35:52 +0000 | [diff] [blame] | 310 | case CP_ACCESS_TRAP_UNCATEGORIZED: |
Peter Maydell | 8bcbf37 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 311 | env->exception.syndrome = syn_uncategorized(); |
Peter Maydell | f59df3f | 2014-02-20 10:35:52 +0000 | [diff] [blame] | 312 | break; |
| 313 | default: |
| 314 | g_assert_not_reached(); |
| 315 | } |
| 316 | raise_exception(env, EXCP_UDEF); |
| 317 | } |
| 318 | |
Peter Maydell | 4b6a83f | 2012-06-20 11:57:06 +0000 | [diff] [blame] | 319 | void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) |
| 320 | { |
| 321 | const ARMCPRegInfo *ri = rip; |
Peter Maydell | c4241c7 | 2014-02-20 10:35:54 +0000 | [diff] [blame] | 322 | |
| 323 | ri->writefn(env, ri, value); |
Peter Maydell | 4b6a83f | 2012-06-20 11:57:06 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) |
| 327 | { |
| 328 | const ARMCPRegInfo *ri = rip; |
Peter Maydell | c4241c7 | 2014-02-20 10:35:54 +0000 | [diff] [blame] | 329 | |
| 330 | return ri->readfn(env, ri); |
Peter Maydell | 4b6a83f | 2012-06-20 11:57:06 +0000 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) |
| 334 | { |
| 335 | const ARMCPRegInfo *ri = rip; |
Peter Maydell | c4241c7 | 2014-02-20 10:35:54 +0000 | [diff] [blame] | 336 | |
| 337 | ri->writefn(env, ri, value); |
Peter Maydell | 4b6a83f | 2012-06-20 11:57:06 +0000 | [diff] [blame] | 338 | } |
| 339 | |
| 340 | uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) |
| 341 | { |
| 342 | const ARMCPRegInfo *ri = rip; |
Peter Maydell | c4241c7 | 2014-02-20 10:35:54 +0000 | [diff] [blame] | 343 | |
| 344 | return ri->readfn(env, ri); |
Peter Maydell | 4b6a83f | 2012-06-20 11:57:06 +0000 | [diff] [blame] | 345 | } |
| 346 | |
Peter Maydell | 9cfa0b4 | 2014-02-26 17:20:06 +0000 | [diff] [blame] | 347 | void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) |
| 348 | { |
| 349 | /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. |
| 350 | * Note that SPSel is never OK from EL0; we rely on handle_msr_i() |
| 351 | * to catch that case at translate time. |
| 352 | */ |
| 353 | if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { |
| 354 | raise_exception(env, EXCP_UDEF); |
| 355 | } |
| 356 | |
| 357 | switch (op) { |
| 358 | case 0x05: /* SPSel */ |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 359 | update_spsel(env, imm); |
Peter Maydell | 9cfa0b4 | 2014-02-26 17:20:06 +0000 | [diff] [blame] | 360 | break; |
| 361 | case 0x1e: /* DAIFSet */ |
| 362 | env->daif |= (imm << 6) & PSTATE_DAIF; |
| 363 | break; |
| 364 | case 0x1f: /* DAIFClear */ |
| 365 | env->daif &= ~((imm << 6) & PSTATE_DAIF); |
| 366 | break; |
| 367 | default: |
| 368 | g_assert_not_reached(); |
| 369 | } |
| 370 | } |
| 371 | |
Peter Maydell | 7ea47fe | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 372 | void HELPER(clear_pstate_ss)(CPUARMState *env) |
| 373 | { |
| 374 | env->pstate &= ~PSTATE_SS; |
| 375 | } |
| 376 | |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 377 | void HELPER(exception_return)(CPUARMState *env) |
| 378 | { |
Edgar E. Iglesias | db6c3cd | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 379 | int cur_el = arm_current_pl(env); |
| 380 | unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); |
Edgar E. Iglesias | 2a923c4 | 2014-05-27 17:09:52 +0100 | [diff] [blame] | 381 | uint32_t spsr = env->banked_spsr[spsr_idx]; |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 382 | int new_el, i; |
| 383 | |
Edgar E. Iglesias | 9208b96 | 2014-08-04 14:41:54 +0100 | [diff] [blame] | 384 | aarch64_save_sp(env, cur_el); |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 385 | |
| 386 | env->exclusive_addr = -1; |
| 387 | |
Peter Maydell | 3a29820 | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 388 | /* We must squash the PSTATE.SS bit to zero unless both of the |
| 389 | * following hold: |
| 390 | * 1. debug exceptions are currently disabled |
| 391 | * 2. singlestep will be active in the EL we return to |
| 392 | * We check 1 here and 2 after we've done the pstate/cpsr write() to |
| 393 | * transition to the EL we're going to. |
| 394 | */ |
| 395 | if (arm_generate_debug_exceptions(env)) { |
| 396 | spsr &= ~PSTATE_SS; |
| 397 | } |
| 398 | |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 399 | if (spsr & PSTATE_nRW) { |
Edgar E. Iglesias | db6c3cd | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 400 | /* TODO: We currently assume EL1/2/3 are running in AArch64. */ |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 401 | env->aarch64 = 0; |
| 402 | new_el = 0; |
| 403 | env->uncached_cpsr = 0x10; |
| 404 | cpsr_write(env, spsr, ~0); |
Peter Maydell | 3a29820 | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 405 | if (!arm_singlestep_active(env)) { |
| 406 | env->uncached_cpsr &= ~PSTATE_SS; |
| 407 | } |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 408 | for (i = 0; i < 15; i++) { |
| 409 | env->regs[i] = env->xregs[i]; |
| 410 | } |
| 411 | |
Edgar E. Iglesias | 6947f05 | 2014-05-27 17:09:51 +0100 | [diff] [blame] | 412 | env->regs[15] = env->elr_el[1] & ~0x1; |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 413 | } else { |
| 414 | new_el = extract32(spsr, 2, 2); |
Edgar E. Iglesias | 7ab6c10 | 2014-05-27 17:09:53 +0100 | [diff] [blame] | 415 | if (new_el > cur_el |
| 416 | || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) { |
| 417 | /* Disallow return to an EL which is unimplemented or higher |
| 418 | * than the current one. |
| 419 | */ |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 420 | goto illegal_return; |
| 421 | } |
| 422 | if (extract32(spsr, 1, 1)) { |
| 423 | /* Return with reserved M[1] bit set */ |
| 424 | goto illegal_return; |
| 425 | } |
| 426 | if (new_el == 0 && (spsr & PSTATE_SP)) { |
Edgar E. Iglesias | 37f0806 | 2014-05-01 15:24:46 +0100 | [diff] [blame] | 427 | /* Return to EL0 with M[0] bit set */ |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 428 | goto illegal_return; |
| 429 | } |
| 430 | env->aarch64 = 1; |
| 431 | pstate_write(env, spsr); |
Peter Maydell | 3a29820 | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 432 | if (!arm_singlestep_active(env)) { |
| 433 | env->pstate &= ~PSTATE_SS; |
| 434 | } |
Edgar E. Iglesias | 98ea561 | 2014-08-04 14:41:54 +0100 | [diff] [blame] | 435 | aarch64_restore_sp(env, new_el); |
Edgar E. Iglesias | db6c3cd | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 436 | env->pc = env->elr_el[cur_el]; |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | return; |
| 440 | |
| 441 | illegal_return: |
| 442 | /* Illegal return events of various kinds have architecturally |
| 443 | * mandated behaviour: |
| 444 | * restore NZCV and DAIF from SPSR_ELx |
| 445 | * set PSTATE.IL |
| 446 | * restore PC from ELR_ELx |
| 447 | * no change to exception level, execution state or stack pointer |
| 448 | */ |
| 449 | env->pstate |= PSTATE_IL; |
Edgar E. Iglesias | db6c3cd | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 450 | env->pc = env->elr_el[cur_el]; |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 451 | spsr &= PSTATE_NZCV | PSTATE_DAIF; |
| 452 | spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); |
| 453 | pstate_write(env, spsr); |
Peter Maydell | 3a29820 | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 454 | if (!arm_singlestep_active(env)) { |
| 455 | env->pstate &= ~PSTATE_SS; |
| 456 | } |
Rob Herring | 52e60cd | 2014-04-15 19:18:44 +0100 | [diff] [blame] | 457 | } |
| 458 | |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 459 | /* ??? Flag setting arithmetic is awkward because we need to do comparisons. |
| 460 | The only way to do that in TCG is a conditional branch, which clobbers |
| 461 | all our temporaries. For now implement these as helper functions. */ |
| 462 | |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 463 | /* Similarly for variable shift instructions. */ |
| 464 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 465 | uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 466 | { |
| 467 | int shift = i & 0xff; |
| 468 | if (shift >= 32) { |
| 469 | if (shift == 32) |
| 470 | env->CF = x & 1; |
| 471 | else |
| 472 | env->CF = 0; |
| 473 | return 0; |
| 474 | } else if (shift != 0) { |
| 475 | env->CF = (x >> (32 - shift)) & 1; |
| 476 | return x << shift; |
| 477 | } |
| 478 | return x; |
| 479 | } |
| 480 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 481 | uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 482 | { |
| 483 | int shift = i & 0xff; |
| 484 | if (shift >= 32) { |
| 485 | if (shift == 32) |
| 486 | env->CF = (x >> 31) & 1; |
| 487 | else |
| 488 | env->CF = 0; |
| 489 | return 0; |
| 490 | } else if (shift != 0) { |
| 491 | env->CF = (x >> (shift - 1)) & 1; |
| 492 | return x >> shift; |
| 493 | } |
| 494 | return x; |
| 495 | } |
| 496 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 497 | uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 498 | { |
| 499 | int shift = i & 0xff; |
| 500 | if (shift >= 32) { |
| 501 | env->CF = (x >> 31) & 1; |
| 502 | return (int32_t)x >> 31; |
| 503 | } else if (shift != 0) { |
| 504 | env->CF = (x >> (shift - 1)) & 1; |
| 505 | return (int32_t)x >> shift; |
| 506 | } |
| 507 | return x; |
| 508 | } |
| 509 | |
Blue Swirl | 9ef3927 | 2012-09-04 20:19:15 +0000 | [diff] [blame] | 510 | uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 511 | { |
| 512 | int shift1, shift; |
| 513 | shift1 = i & 0xff; |
| 514 | shift = shift1 & 0x1f; |
| 515 | if (shift == 0) { |
| 516 | if (shift1 != 0) |
| 517 | env->CF = (x >> 31) & 1; |
| 518 | return x; |
| 519 | } else { |
| 520 | env->CF = (x >> (shift - 1)) & 1; |
| 521 | return ((uint32_t)x >> shift) | (x << (32 - shift)); |
| 522 | } |
| 523 | } |