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Andreas Färberf20f9df2013-07-07 12:07:54 +02001/*
2 * x86 gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
Chetan Pantd9ff33a2020-10-23 12:28:01 +000010 * version 2.1 of the License, or (at your option) any later version.
Andreas Färberf20f9df2013-07-07 12:07:54 +020011 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
Peter Maydellb6a0aa02016-01-26 18:17:03 +000020#include "qemu/osdep.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010021#include "cpu.h"
Andreas Färber5b50e792013-06-29 04:18:45 +020022#include "exec/gdbstub.h"
Andreas Färberf20f9df2013-07-07 12:07:54 +020023
24#ifdef TARGET_X86_64
25static const int gpr_map[16] = {
26 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
27 8, 9, 10, 11, 12, 13, 14, 15
28};
29#else
30#define gpr_map gpr_map32
31#endif
32static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
33
Doug Gale7b0f97b2019-01-24 00:34:57 -033034/*
35 * Keep these in sync with assignment to
36 * gdb_num_core_regs in target/i386/cpu.c
37 * and with the machine description
38 */
39
40/*
41 * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
42 */
43
44/*
45 * general regs -----> 8 or 16
46 */
47#define IDX_NB_IP 1
48#define IDX_NB_FLAGS 1
49#define IDX_NB_SEG (6 + 3)
50#define IDX_NB_CTL 6
51#define IDX_NB_FP 16
52/*
53 * fpu regs ----------> 8 or 16
54 */
55#define IDX_NB_MXCSR 1
56/*
57 * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
58 */
59
Andreas Färberf20f9df2013-07-07 12:07:54 +020060#define IDX_IP_REG CPU_NB_REGS
Doug Gale7b0f97b2019-01-24 00:34:57 -033061#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
62#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
63#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
64#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
65#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
Andreas Färberf20f9df2013-07-07 12:07:54 +020066#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
67
Doug Gale7b0f97b2019-01-24 00:34:57 -033068#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
69#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
70#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
71#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
72#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
73#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
74
75#ifdef TARGET_X86_64
76#define GDB_FORCE_64 1
77#else
78#define GDB_FORCE_64 0
79#endif
80
Claudio Fontana4d81e282021-03-22 14:27:55 +010081static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val)
82{
83 if ((hflags & HF_CS64_MASK) || GDB_FORCE_64) {
84 return gdb_get_reg64(buf, val);
85 }
86 return gdb_get_reg32(buf, val);
87}
88
89static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)
90{
91 if (hflags & HF_CS64_MASK) {
92 *val = ldq_p(buf);
93 return 8;
94 }
95 *val = ldl_p(buf);
96 return 4;
97}
Doug Gale7b0f97b2019-01-24 00:34:57 -033098
Alex Bennéea010bdb2020-03-16 17:21:41 +000099int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
Andreas Färberf20f9df2013-07-07 12:07:54 +0200100{
Andreas Färber5b50e792013-06-29 04:18:45 +0200101 X86CPU *cpu = X86_CPU(cs);
102 CPUX86State *env = &cpu->env;
103
Doug Gale7b0f97b2019-01-24 00:34:57 -0330104 uint64_t tpr;
105
Doug Evanse3592bc2016-11-03 23:35:32 +0000106 /* N.B. GDB can't deal with changes in registers or sizes in the middle
107 of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
108 as if we're on a 64-bit cpu. */
109
Andreas Färberf20f9df2013-07-07 12:07:54 +0200110 if (n < CPU_NB_REGS) {
Doug Evanse3592bc2016-11-03 23:35:32 +0000111 if (TARGET_LONG_BITS == 64) {
112 if (env->hflags & HF_CS64_MASK) {
113 return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
114 } else if (n < CPU_NB_REGS32) {
115 return gdb_get_reg64(mem_buf,
116 env->regs[gpr_map[n]] & 0xffffffffUL);
117 } else {
Alex Bennéeb7b87562020-03-16 17:21:40 +0000118 return gdb_get_regl(mem_buf, 0);
Doug Evanse3592bc2016-11-03 23:35:32 +0000119 }
120 } else {
Andreas Färber986a2992013-07-07 13:05:05 +0200121 return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200122 }
123 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
Alex Bennéeb7b87562020-03-16 17:21:40 +0000124 floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
125 int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
Peter Xubbc40fe2020-04-14 21:06:25 +0100126 len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high));
Alex Bennéeb7b87562020-03-16 17:21:40 +0000127 return len;
Andreas Färberf20f9df2013-07-07 12:07:54 +0200128 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
129 n -= IDX_XMM_REGS;
Doug Evanse3592bc2016-11-03 23:35:32 +0000130 if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
Alex Bennéeb7b87562020-03-16 17:21:40 +0000131 return gdb_get_reg128(mem_buf,
132 env->xmm_regs[n].ZMM_Q(0),
133 env->xmm_regs[n].ZMM_Q(1));
Andreas Färberf20f9df2013-07-07 12:07:54 +0200134 }
135 } else {
136 switch (n) {
137 case IDX_IP_REG:
Doug Evanse3592bc2016-11-03 23:35:32 +0000138 if (TARGET_LONG_BITS == 64) {
139 if (env->hflags & HF_CS64_MASK) {
140 return gdb_get_reg64(mem_buf, env->eip);
141 } else {
142 return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
143 }
Andreas Färberf20f9df2013-07-07 12:07:54 +0200144 } else {
Andreas Färber986a2992013-07-07 13:05:05 +0200145 return gdb_get_reg32(mem_buf, env->eip);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200146 }
147 case IDX_FLAGS_REG:
Andreas Färber986a2992013-07-07 13:05:05 +0200148 return gdb_get_reg32(mem_buf, env->eflags);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200149
150 case IDX_SEG_REGS:
Andreas Färber986a2992013-07-07 13:05:05 +0200151 return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200152 case IDX_SEG_REGS + 1:
Andreas Färber986a2992013-07-07 13:05:05 +0200153 return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200154 case IDX_SEG_REGS + 2:
Andreas Färber986a2992013-07-07 13:05:05 +0200155 return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200156 case IDX_SEG_REGS + 3:
Andreas Färber986a2992013-07-07 13:05:05 +0200157 return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200158 case IDX_SEG_REGS + 4:
Andreas Färber986a2992013-07-07 13:05:05 +0200159 return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200160 case IDX_SEG_REGS + 5:
Andreas Färber986a2992013-07-07 13:05:05 +0200161 return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330162 case IDX_SEG_REGS + 6:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100163 return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330164 case IDX_SEG_REGS + 7:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100165 return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330166
167 case IDX_SEG_REGS + 8:
168#ifdef TARGET_X86_64
Claudio Fontana4d81e282021-03-22 14:27:55 +0100169 return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330170#else
171 return gdb_get_reg32(mem_buf, 0);
172#endif
173
Andreas Färberf20f9df2013-07-07 12:07:54 +0200174 case IDX_FP_REGS + 8:
Andreas Färber986a2992013-07-07 13:05:05 +0200175 return gdb_get_reg32(mem_buf, env->fpuc);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200176 case IDX_FP_REGS + 9:
Andreas Färber986a2992013-07-07 13:05:05 +0200177 return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
178 (env->fpstt & 0x7) << 11);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200179 case IDX_FP_REGS + 10:
Andreas Färber986a2992013-07-07 13:05:05 +0200180 return gdb_get_reg32(mem_buf, 0); /* ftag */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200181 case IDX_FP_REGS + 11:
Andreas Färber986a2992013-07-07 13:05:05 +0200182 return gdb_get_reg32(mem_buf, 0); /* fiseg */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200183 case IDX_FP_REGS + 12:
Andreas Färber986a2992013-07-07 13:05:05 +0200184 return gdb_get_reg32(mem_buf, 0); /* fioff */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200185 case IDX_FP_REGS + 13:
Andreas Färber986a2992013-07-07 13:05:05 +0200186 return gdb_get_reg32(mem_buf, 0); /* foseg */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200187 case IDX_FP_REGS + 14:
Andreas Färber986a2992013-07-07 13:05:05 +0200188 return gdb_get_reg32(mem_buf, 0); /* fooff */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200189 case IDX_FP_REGS + 15:
Andreas Färber986a2992013-07-07 13:05:05 +0200190 return gdb_get_reg32(mem_buf, 0); /* fop */
Andreas Färberf20f9df2013-07-07 12:07:54 +0200191
192 case IDX_MXCSR_REG:
Joseph Myers418b0f92020-06-25 23:58:31 +0000193 update_mxcsr_from_sse_status(env);
Andreas Färber986a2992013-07-07 13:05:05 +0200194 return gdb_get_reg32(mem_buf, env->mxcsr);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330195
196 case IDX_CTL_CR0_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100197 return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330198 case IDX_CTL_CR2_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100199 return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330200 case IDX_CTL_CR3_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100201 return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330202 case IDX_CTL_CR4_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100203 return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330204 case IDX_CTL_CR8_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100205#ifndef CONFIG_USER_ONLY
Doug Gale7b0f97b2019-01-24 00:34:57 -0330206 tpr = cpu_get_apic_tpr(cpu->apic_state);
207#else
208 tpr = 0;
209#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100210 return gdb_read_reg_cs64(env->hflags, mem_buf, tpr);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330211
212 case IDX_CTL_EFER_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100213 return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200214 }
215 }
216 return 0;
217}
218
Philippe Mathieu-Daudéc117e5b2021-01-10 00:34:27 +0100219static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf)
Andreas Färberf20f9df2013-07-07 12:07:54 +0200220{
Andreas Färber5b50e792013-06-29 04:18:45 +0200221 CPUX86State *env = &cpu->env;
Andreas Färberf20f9df2013-07-07 12:07:54 +0200222 uint16_t selector = ldl_p(mem_buf);
223
224 if (selector != env->segs[sreg].selector) {
225#if defined(CONFIG_USER_ONLY)
226 cpu_x86_load_seg(env, sreg, selector);
227#else
228 unsigned int limit, flags;
229 target_ulong base;
230
231 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
Paolo Bonzinib98dbc92014-05-15 16:07:04 +0200232 int dpl = (env->eflags & VM_MASK) ? 3 : 0;
Andreas Färberf20f9df2013-07-07 12:07:54 +0200233 base = selector << 4;
234 limit = 0xffff;
Paolo Bonzinib98dbc92014-05-15 16:07:04 +0200235 flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
236 DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200237 } else {
238 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
239 &flags)) {
240 return 4;
241 }
242 }
243 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
244#endif
245 }
246 return 4;
247}
248
Andreas Färber5b50e792013-06-29 04:18:45 +0200249int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
Andreas Färberf20f9df2013-07-07 12:07:54 +0200250{
Andreas Färber5b50e792013-06-29 04:18:45 +0200251 X86CPU *cpu = X86_CPU(cs);
252 CPUX86State *env = &cpu->env;
Claudio Fontana4d81e282021-03-22 14:27:55 +0100253 target_ulong tmp;
254 int len;
Andreas Färberf20f9df2013-07-07 12:07:54 +0200255
Doug Evanse3592bc2016-11-03 23:35:32 +0000256 /* N.B. GDB can't deal with changes in registers or sizes in the middle
257 of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
258 as if we're on a 64-bit cpu. */
259
Andreas Färberf20f9df2013-07-07 12:07:54 +0200260 if (n < CPU_NB_REGS) {
Doug Evanse3592bc2016-11-03 23:35:32 +0000261 if (TARGET_LONG_BITS == 64) {
262 if (env->hflags & HF_CS64_MASK) {
263 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
264 } else if (n < CPU_NB_REGS32) {
265 env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
266 }
Andreas Färberf20f9df2013-07-07 12:07:54 +0200267 return sizeof(target_ulong);
268 } else if (n < CPU_NB_REGS32) {
269 n = gpr_map32[n];
270 env->regs[n] &= ~0xffffffffUL;
271 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
272 return 4;
273 }
274 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
Alex Bennéeb7b87562020-03-16 17:21:40 +0000275 floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
276 fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
277 fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
Andreas Färberf20f9df2013-07-07 12:07:54 +0200278 return 10;
279 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
280 n -= IDX_XMM_REGS;
Doug Evanse3592bc2016-11-03 23:35:32 +0000281 if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
Eduardo Habkost19cbd872015-11-26 17:14:32 -0200282 env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
283 env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200284 return 16;
285 }
286 } else {
287 switch (n) {
288 case IDX_IP_REG:
Doug Evanse3592bc2016-11-03 23:35:32 +0000289 if (TARGET_LONG_BITS == 64) {
290 if (env->hflags & HF_CS64_MASK) {
291 env->eip = ldq_p(mem_buf);
292 } else {
293 env->eip = ldq_p(mem_buf) & 0xffffffffUL;
294 }
Andreas Färberf20f9df2013-07-07 12:07:54 +0200295 return 8;
296 } else {
297 env->eip &= ~0xffffffffUL;
298 env->eip |= (uint32_t)ldl_p(mem_buf);
299 return 4;
300 }
301 case IDX_FLAGS_REG:
302 env->eflags = ldl_p(mem_buf);
303 return 4;
304
305 case IDX_SEG_REGS:
Andreas Färber5b50e792013-06-29 04:18:45 +0200306 return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200307 case IDX_SEG_REGS + 1:
Andreas Färber5b50e792013-06-29 04:18:45 +0200308 return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200309 case IDX_SEG_REGS + 2:
Andreas Färber5b50e792013-06-29 04:18:45 +0200310 return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200311 case IDX_SEG_REGS + 3:
Andreas Färber5b50e792013-06-29 04:18:45 +0200312 return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200313 case IDX_SEG_REGS + 4:
Andreas Färber5b50e792013-06-29 04:18:45 +0200314 return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
Andreas Färberf20f9df2013-07-07 12:07:54 +0200315 case IDX_SEG_REGS + 5:
Andreas Färber5b50e792013-06-29 04:18:45 +0200316 return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330317 case IDX_SEG_REGS + 6:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100318 return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330319 case IDX_SEG_REGS + 7:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100320 return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330321 case IDX_SEG_REGS + 8:
mkdolata@us.ibm.com5a071922020-01-07 14:26:07 +0100322#ifdef TARGET_X86_64
Claudio Fontana4d81e282021-03-22 14:27:55 +0100323 return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330324#endif
mkdolata@us.ibm.com5a071922020-01-07 14:26:07 +0100325 return 4;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330326
Andreas Färberf20f9df2013-07-07 12:07:54 +0200327 case IDX_FP_REGS + 8:
Pavel Dovgalyuk5bde1402014-09-17 12:05:19 +0400328 cpu_set_fpuc(env, ldl_p(mem_buf));
Andreas Färberf20f9df2013-07-07 12:07:54 +0200329 return 4;
330 case IDX_FP_REGS + 9:
331 tmp = ldl_p(mem_buf);
332 env->fpstt = (tmp >> 11) & 7;
333 env->fpus = tmp & ~0x3800;
334 return 4;
335 case IDX_FP_REGS + 10: /* ftag */
336 return 4;
337 case IDX_FP_REGS + 11: /* fiseg */
338 return 4;
339 case IDX_FP_REGS + 12: /* fioff */
340 return 4;
341 case IDX_FP_REGS + 13: /* foseg */
342 return 4;
343 case IDX_FP_REGS + 14: /* fooff */
344 return 4;
345 case IDX_FP_REGS + 15: /* fop */
346 return 4;
347
348 case IDX_MXCSR_REG:
Richard Henderson4e47e392014-02-24 14:59:54 -0800349 cpu_set_mxcsr(env, ldl_p(mem_buf));
Andreas Färberf20f9df2013-07-07 12:07:54 +0200350 return 4;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330351
352 case IDX_CTL_CR0_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100353 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100354#ifndef CONFIG_USER_ONLY
Claudio Fontana4d81e282021-03-22 14:27:55 +0100355 cpu_x86_update_cr0(env, tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100356#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100357 return len;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330358
359 case IDX_CTL_CR2_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100360 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100361#ifndef CONFIG_USER_ONLY
Claudio Fontana4d81e282021-03-22 14:27:55 +0100362 env->cr[2] = tmp;
Claudio Fontana1852f092021-03-22 14:27:56 +0100363#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100364 return len;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330365
366 case IDX_CTL_CR3_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100367 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100368#ifndef CONFIG_USER_ONLY
Claudio Fontana4d81e282021-03-22 14:27:55 +0100369 cpu_x86_update_cr3(env, tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100370#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100371 return len;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330372
373 case IDX_CTL_CR4_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100374 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100375#ifndef CONFIG_USER_ONLY
Claudio Fontana4d81e282021-03-22 14:27:55 +0100376 cpu_x86_update_cr4(env, tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100377#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100378 return len;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330379
380 case IDX_CTL_CR8_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100381 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
382#ifndef CONFIG_USER_ONLY
383 cpu_set_apic_tpr(cpu->apic_state, tmp);
Doug Gale7b0f97b2019-01-24 00:34:57 -0330384#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100385 return len;
Doug Gale7b0f97b2019-01-24 00:34:57 -0330386
387 case IDX_CTL_EFER_REG:
Claudio Fontana4d81e282021-03-22 14:27:55 +0100388 len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100389#ifndef CONFIG_USER_ONLY
Claudio Fontana4d81e282021-03-22 14:27:55 +0100390 cpu_load_efer(env, tmp);
Claudio Fontana1852f092021-03-22 14:27:56 +0100391#endif
Claudio Fontana4d81e282021-03-22 14:27:55 +0100392 return len;
Andreas Färberf20f9df2013-07-07 12:07:54 +0200393 }
394 }
395 /* Unrecognised register. */
396 return 0;
397}