blob: 920d7596e3669567507cabcdfb12fcddbfffa07f [file] [log] [blame]
Paolo Bonzinicb9c3772012-12-06 12:15:58 +01001#ifndef HW_FLASH_H
2#define HW_FLASH_H 1
3
pbrook87ecb682007-11-17 17:14:51 +00004/* NOR flash devices */
Avi Kivitycfe5f012011-08-04 15:55:30 +03005
Paolo Bonzini022c62c2012-12-17 18:19:49 +01006#include "exec/memory.h"
Avi Kivitycfe5f012011-08-04 15:55:30 +03007
Anthony Liguoric227f092009-10-01 16:12:16 -05008typedef struct pflash_t pflash_t;
pbrook87ecb682007-11-17 17:14:51 +00009
balrog88eeee02007-12-10 00:28:27 +000010/* pflash_cfi01.c */
Avi Kivitya8170e52012-10-23 12:30:10 +020011pflash_t *pflash_cfi01_register(hwaddr base,
Avi Kivitycfe5f012011-08-04 15:55:30 +030012 DeviceState *qdev, const char *name,
Avi Kivitya8170e52012-10-23 12:30:10 +020013 hwaddr size,
balrog88eeee02007-12-10 00:28:27 +000014 BlockDriverState *bs,
15 uint32_t sector_len, int nb_blocs, int width,
16 uint16_t id0, uint16_t id1,
Anthony Liguori01e04512011-08-25 14:39:18 -050017 uint16_t id2, uint16_t id3, int be);
balrog88eeee02007-12-10 00:28:27 +000018
19/* pflash_cfi02.c */
Avi Kivitya8170e52012-10-23 12:30:10 +020020pflash_t *pflash_cfi02_register(hwaddr base,
Avi Kivitycfe5f012011-08-04 15:55:30 +030021 DeviceState *qdev, const char *name,
Avi Kivitya8170e52012-10-23 12:30:10 +020022 hwaddr size,
balrogcf6d9112007-12-10 01:07:47 +000023 BlockDriverState *bs, uint32_t sector_len,
balrog4fbd24b2008-04-16 23:45:36 +000024 int nb_blocs, int nb_mappings, int width,
balrog88eeee02007-12-10 00:28:27 +000025 uint16_t id0, uint16_t id1,
balrog67250702008-04-16 23:37:15 +000026 uint16_t id2, uint16_t id3,
Anthony Liguori01e04512011-08-25 14:39:18 -050027 uint16_t unlock_addr0, uint16_t unlock_addr1,
28 int be);
pbrook87ecb682007-11-17 17:14:51 +000029
Avi Kivitycfe5f012011-08-04 15:55:30 +030030MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl);
31
pbrook87ecb682007-11-17 17:14:51 +000032/* nand.c */
Juha Riihimäkid4220382011-07-29 16:35:24 +010033DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
34void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
Juan Quintela51db57f2010-12-03 01:39:22 +010035 uint8_t ce, uint8_t wp, uint8_t gnd);
Juha Riihimäkid4220382011-07-29 16:35:24 +010036void nand_getpins(DeviceState *dev, int *rb);
37void nand_setio(DeviceState *dev, uint32_t value);
38uint32_t nand_getio(DeviceState *dev);
39uint32_t nand_getbuswidth(DeviceState *dev);
pbrook87ecb682007-11-17 17:14:51 +000040
41#define NAND_MFR_TOSHIBA 0x98
42#define NAND_MFR_SAMSUNG 0xec
43#define NAND_MFR_FUJITSU 0x04
44#define NAND_MFR_NATIONAL 0x8f
45#define NAND_MFR_RENESAS 0x07
46#define NAND_MFR_STMICRO 0x20
47#define NAND_MFR_HYNIX 0xad
48#define NAND_MFR_MICRON 0x2c
49
balrog7e7c5e42008-04-14 21:57:44 +000050/* onenand.c */
Juha Riihimäki500954e2011-08-28 16:22:17 +000051void *onenand_raw_otp(DeviceState *onenand_device);
balrog7e7c5e42008-04-14 21:57:44 +000052
pbrook87ecb682007-11-17 17:14:51 +000053/* ecc.c */
Paul Brookbc24a222009-05-10 01:44:56 +010054typedef struct {
pbrook87ecb682007-11-17 17:14:51 +000055 uint8_t cp; /* Column parity */
56 uint16_t lp[2]; /* Line parity */
57 uint16_t count;
Paul Brookbc24a222009-05-10 01:44:56 +010058} ECCState;
pbrook87ecb682007-11-17 17:14:51 +000059
Paul Brookbc24a222009-05-10 01:44:56 +010060uint8_t ecc_digest(ECCState *s, uint8_t sample);
61void ecc_reset(ECCState *s);
Dmitry Eremin-Solenikov34f9f0b2011-01-21 13:12:11 +030062extern VMStateDescription vmstate_ecc_state;
Paolo Bonzinicb9c3772012-12-06 12:15:58 +010063
64#endif