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Aurelien Jarno7b9cbad2010-03-14 23:30:19 +01001/*
2 * QEMU MIPS interrupt support
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
pbrook87ecb682007-11-17 17:14:51 +000023#include "hw.h"
Blue Swirlb970ea82010-03-27 07:26:16 +000024#include "mips_cpudevs.h"
ths4de9b242007-01-24 01:47:51 +000025#include "cpu.h"
26
pbrookd537cf62007-04-07 18:14:41 +000027static void cpu_mips_irq_request(void *opaque, int irq, int level)
ths4de9b242007-01-24 01:47:51 +000028{
Andreas Färber61c56c82012-03-14 01:38:23 +010029 CPUMIPSState *env = (CPUMIPSState *)opaque;
ths4de9b242007-01-24 01:47:51 +000030
ths39d51eb2007-03-18 12:43:40 +000031 if (irq < 0 || irq > 7)
ths4de9b242007-01-24 01:47:51 +000032 return;
33
ths4de9b242007-01-24 01:47:51 +000034 if (level) {
ths39d51eb2007-03-18 12:43:40 +000035 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
ths4de9b242007-01-24 01:47:51 +000036 } else {
thsa4bc3af2007-03-31 16:54:14 +000037 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
ths4de9b242007-01-24 01:47:51 +000038 }
Edgar E. Iglesias36388312010-07-24 13:40:05 +020039
40 if (env->CP0_Cause & CP0Ca_IP_mask) {
41 cpu_interrupt(env, CPU_INTERRUPT_HARD);
42 } else {
43 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
44 }
ths4de9b242007-01-24 01:47:51 +000045}
pbrookd537cf62007-04-07 18:14:41 +000046
Andreas Färber61c56c82012-03-14 01:38:23 +010047void cpu_mips_irq_init_cpu(CPUMIPSState *env)
pbrookd537cf62007-04-07 18:14:41 +000048{
49 qemu_irq *qi;
50 int i;
51
52 qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
53 for (i = 0; i < 8; i++) {
54 env->irq[i] = qi[i];
55 }
56}
Aurelien Jarno5dc5d9f2010-07-25 16:51:29 +020057
Andreas Färber61c56c82012-03-14 01:38:23 +010058void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
Aurelien Jarno5dc5d9f2010-07-25 16:51:29 +020059{
60 if (irq < 0 || irq > 2) {
61 return;
62 }
63
64 qemu_set_irq(env->irq[irq], level);
65}