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bellardc896fe22008-02-01 10:05:41 +00001Tiny Code Generator - Fabrice Bellard.
2
31) Introduction
4
5TCG (Tiny Code Generator) began as a generic backend for a C
6compiler. It was simplified to be used in QEMU. It also has its roots
7in the QOP code generator written by Paul Brook.
8
92) Definitions
10
Paolo Bonzinibf28a692016-10-06 15:10:10 +020011TCG receives RISC-like "TCG ops" and performs some optimizations on them,
12including liveness analysis and trivial constant expression
13evaluation. TCG ops are then implemented in the host CPU back end,
14also known as the TCG "target".
15
bellardc896fe22008-02-01 10:05:41 +000016The TCG "target" is the architecture for which we generate the
17code. It is of course not the same as the "target" of QEMU which is
18the emulated architecture. As TCG started as a generic C backend used
19for cross compiling, it is assumed that the TCG target is different
20from the host, although it is never the case for QEMU.
21
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +080022In this document, we use "guest" to specify what architecture we are
23emulating; "target" always means the TCG target, the machine on which
24we are running QEMU.
25
bellardc896fe22008-02-01 10:05:41 +000026A TCG "function" corresponds to a QEMU Translated Block (TB).
27
bellard0a6b7b72008-05-25 18:24:40 +000028A TCG "temporary" is a variable only live in a basic
29block. Temporaries are allocated explicitly in each function.
bellardc896fe22008-02-01 10:05:41 +000030
bellard0a6b7b72008-05-25 18:24:40 +000031A TCG "local temporary" is a variable only live in a function. Local
32temporaries are allocated explicitly in each function.
33
34A TCG "global" is a variable which is live in all the functions
35(equivalent of a C global variable). They are defined before the
36functions defined. A TCG global can be a memory location (e.g. a QEMU
37CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
38or a memory location which is stored in a register outside QEMU TBs
39(not implemented yet).
bellardc896fe22008-02-01 10:05:41 +000040
41A TCG "basic block" corresponds to a list of instructions terminated
42by a branch instruction.
43
Richard Henderson20022fa2014-03-18 08:21:44 -070044An operation with "undefined behavior" may result in a crash.
45
46An operation with "unspecified behavior" shall not crash. However,
47the result may be one of several possibilities so may be considered
48an "undefined result".
49
bellardc896fe22008-02-01 10:05:41 +0000503) Intermediate representation
51
523.1) Introduction
53
bellard0a6b7b72008-05-25 18:24:40 +000054TCG instructions operate on variables which are temporaries, local
55temporaries or globals. TCG instructions and variables are strongly
56typed. Two types are supported: 32 bit integers and 64 bit
57integers. Pointers are defined as an alias to 32 bit or 64 bit
58integers depending on the TCG target word size.
bellardc896fe22008-02-01 10:05:41 +000059
60Each instruction has a fixed number of output variable operands, input
61variable operands and always constant operands.
62
63The notable exception is the call instruction which has a variable
64number of outputs and inputs.
65
bellard0a6b7b72008-05-25 18:24:40 +000066In the textual form, output operands usually come first, followed by
67input operands, followed by constant operands. The output type is
68included in the instruction name. Constants are prefixed with a '$'.
bellardc896fe22008-02-01 10:05:41 +000069
70add_i32 t0, t1, t2 (t0 <- t1 + t2)
71
bellardc896fe22008-02-01 10:05:41 +0000723.2) Assumptions
73
74* Basic blocks
75
76- Basic blocks end after branches (e.g. brcond_i32 instruction),
77 goto_tb and exit_tb instructions.
aurel3286e840e2008-12-07 15:21:23 +000078- Basic blocks start after the end of a previous basic block, or at a
79 set_label instruction.
bellardc896fe22008-02-01 10:05:41 +000080
bellard0a6b7b72008-05-25 18:24:40 +000081After the end of a basic block, the content of temporaries is
82destroyed, but local temporaries and globals are preserved.
bellardc896fe22008-02-01 10:05:41 +000083
84* Floating point types are not supported yet
85
86* Pointers: depending on the TCG target, pointer size is 32 bit or 64
87 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
88 TCG_TYPE_I64.
89
90* Helpers:
91
92Using the tcg_gen_helper_x_y it is possible to call any function
Stefan Weilaa95e3a2011-01-07 21:34:50 +010093taking i32, i64 or pointer types. By default, before calling a helper,
Aurelien Jarnoa3f50542010-03-05 22:48:03 +010094all globals are stored at their canonical location and it is assumed
Aurelien Jarno78505272012-10-09 21:53:08 +020095that the function can modify them. By default, the helper is allowed to
96modify the CPU state or raise an exception.
97
98This can be overridden using the following function modifiers:
99- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
100 either directly or via an exception. They will not be saved to their
101 canonical locations before calling the helper.
102- TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
103 They will only be saved to their canonical location before calling helpers,
Emilio G. Cota2bc89632019-08-28 17:53:04 +0100104 but they won't be reloaded afterwards.
Aurelien Jarno78505272012-10-09 21:53:08 +0200105- TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
106 the return value is not used.
107
108Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS.
bellardc896fe22008-02-01 10:05:41 +0000109
110On some TCG targets (e.g. x86), several calling conventions are
111supported.
112
113* Branches:
114
Aurelien Jarno626cd052012-10-01 21:00:43 +0200115Use the instruction 'br' to jump to a label.
bellardc896fe22008-02-01 10:05:41 +0000116
1173.3) Code Optimizations
118
119When generating instructions, you can count on at least the following
120optimizations:
121
122- Single instructions are simplified, e.g.
123
124 and_i32 t0, t0, $0xffffffff
125
126 is suppressed.
127
128- A liveness analysis is done at the basic block level. The
bellard0a6b7b72008-05-25 18:24:40 +0000129 information is used to suppress moves from a dead variable to
bellardc896fe22008-02-01 10:05:41 +0000130 another one. It is also used to remove instructions which compute
131 dead results. The later is especially useful for condition code
bellard9804c8e2008-02-01 13:01:47 +0000132 optimization in QEMU.
bellardc896fe22008-02-01 10:05:41 +0000133
134 In the following example:
135
136 add_i32 t0, t1, t2
137 add_i32 t0, t0, $1
138 mov_i32 t0, $1
139
140 only the last instruction is kept.
141
bellardc896fe22008-02-01 10:05:41 +00001423.4) Instruction Reference
143
144********* Function call
145
146* call <ret> <params> ptr
147
148call function 'ptr' (pointer type)
149
150<ret> optional 32 bit or 64 bit return value
151<params> optional 32 bit or 64 bit parameters
152
153********* Jumps/Labels
154
bellardc896fe22008-02-01 10:05:41 +0000155* set_label $label
156
157Define label 'label' at the current program point.
158
159* br $label
160
161Jump to label.
162
Richard Henderson5a696f62012-09-21 17:18:09 -0700163* brcond_i32/i64 t0, t1, cond, label
bellardc896fe22008-02-01 10:05:41 +0000164
165Conditional jump if t0 cond t1 is true. cond can be:
166 TCG_COND_EQ
167 TCG_COND_NE
168 TCG_COND_LT /* signed */
169 TCG_COND_GE /* signed */
170 TCG_COND_LE /* signed */
171 TCG_COND_GT /* signed */
172 TCG_COND_LTU /* unsigned */
173 TCG_COND_GEU /* unsigned */
174 TCG_COND_LEU /* unsigned */
175 TCG_COND_GTU /* unsigned */
176
177********* Arithmetic
178
179* add_i32/i64 t0, t1, t2
180
181t0=t1+t2
182
183* sub_i32/i64 t0, t1, t2
184
185t0=t1-t2
186
pbrook390efc52008-05-11 14:35:37 +0000187* neg_i32/i64 t0, t1
188
189t0=-t1 (two's complement)
190
bellardc896fe22008-02-01 10:05:41 +0000191* mul_i32/i64 t0, t1, t2
192
193t0=t1*t2
194
195* div_i32/i64 t0, t1, t2
196
197t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
198
199* divu_i32/i64 t0, t1, t2
200
201t0=t1/t2 (unsigned). Undefined behavior if division by zero.
202
203* rem_i32/i64 t0, t1, t2
204
205t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
206
207* remu_i32/i64 t0, t1, t2
208
209t0=t1%t2 (unsigned). Undefined behavior if division by zero.
210
bellardc896fe22008-02-01 10:05:41 +0000211********* Logical
212
aurel325e854042008-03-12 21:40:02 +0000213* and_i32/i64 t0, t1, t2
214
bellardc896fe22008-02-01 10:05:41 +0000215t0=t1&t2
216
217* or_i32/i64 t0, t1, t2
218
219t0=t1|t2
220
221* xor_i32/i64 t0, t1, t2
222
223t0=t1^t2
224
bellard0a6b7b72008-05-25 18:24:40 +0000225* not_i32/i64 t0, t1
226
227t0=~t1
228
aurel32f24cb332008-10-21 11:28:59 +0000229* andc_i32/i64 t0, t1, t2
230
231t0=t1&~t2
232
233* eqv_i32/i64 t0, t1, t2
234
Richard Henderson8d625cf2010-03-19 13:02:02 -0700235t0=~(t1^t2), or equivalently, t0=t1^~t2
aurel32f24cb332008-10-21 11:28:59 +0000236
237* nand_i32/i64 t0, t1, t2
238
239t0=~(t1&t2)
240
241* nor_i32/i64 t0, t1, t2
242
243t0=~(t1|t2)
244
245* orc_i32/i64 t0, t1, t2
246
247t0=t1|~t2
248
Richard Henderson0e28d002016-11-16 09:23:28 +0100249* clz_i32/i64 t0, t1, t2
250
251t0 = t1 ? clz(t1) : t2
252
253* ctz_i32/i64 t0, t1, t2
254
255t0 = t1 ? ctz(t1) : t2
256
aurel3215824572008-11-03 07:08:36 +0000257********* Shifts/Rotates
bellardc896fe22008-02-01 10:05:41 +0000258
259* shl_i32/i64 t0, t1, t2
260
Richard Henderson20022fa2014-03-18 08:21:44 -0700261t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000262
263* shr_i32/i64 t0, t1, t2
264
Richard Henderson20022fa2014-03-18 08:21:44 -0700265t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000266
267* sar_i32/i64 t0, t1, t2
268
Richard Henderson20022fa2014-03-18 08:21:44 -0700269t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000270
aurel3215824572008-11-03 07:08:36 +0000271* rotl_i32/i64 t0, t1, t2
272
Richard Henderson20022fa2014-03-18 08:21:44 -0700273Rotation of t2 bits to the left.
274Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
aurel3215824572008-11-03 07:08:36 +0000275
276* rotr_i32/i64 t0, t1, t2
277
Richard Henderson20022fa2014-03-18 08:21:44 -0700278Rotation of t2 bits to the right.
279Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
aurel3215824572008-11-03 07:08:36 +0000280
bellardc896fe22008-02-01 10:05:41 +0000281********* Misc
282
283* mov_i32/i64 t0, t1
284
285t0 = t1
286
287Move t1 to t0 (both operands must have the same type).
288
289* ext8s_i32/i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000290ext8u_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000291ext16s_i32/i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000292ext16u_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000293ext32s_i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000294ext32u_i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000295
pbrook86831432008-05-11 12:22:01 +00002968, 16 or 32 bit sign/zero extension (both operands must have the same type)
bellardc896fe22008-02-01 10:05:41 +0000297
aurel324ad4ce12009-03-13 09:35:26 +0000298* bswap16_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000299
Aurelien Jarno837d9872010-04-10 03:36:21 +020030016 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
301bytes are set to zero.
bellardc896fe22008-02-01 10:05:41 +0000302
aurel324ad4ce12009-03-13 09:35:26 +0000303* bswap32_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000304
Aurelien Jarno837d9872010-04-10 03:36:21 +020030532 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
306the four high order bytes are set to zero.
bellardc896fe22008-02-01 10:05:41 +0000307
aurel324ad4ce12009-03-13 09:35:26 +0000308* bswap64_i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000309
31064 bit byte swap
311
bellard5ff9d6a2008-02-04 00:37:54 +0000312* discard_i32/i64 t0
313
314Indicate that the value of t0 won't be used later. It is useful to
315force dead code elimination.
316
Edgar E. Iglesias3a34dfd2011-01-20 12:16:57 +0100317* deposit_i32/i64 dest, t1, t2, pos, len
Richard Hendersonb7767f02011-01-10 19:23:42 -0800318
319Deposit T2 as a bitfield into T1, placing the result in DEST.
Edgar E. Iglesias3a34dfd2011-01-20 12:16:57 +0100320The bitfield is described by POS/LEN, which are immediate values:
Richard Hendersonb7767f02011-01-10 19:23:42 -0800321
322 LEN - the length of the bitfield
323 POS - the position of the first bit, counting from the LSB
324
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500325For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
326at bit 8. This operation would be equivalent to
Richard Hendersonb7767f02011-01-10 19:23:42 -0800327
328 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
329
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500330* extract_i32/i64 dest, t1, pos, len
331* sextract_i32/i64 dest, t1, pos, len
332
333Extract a bitfield from T1, placing the result in DEST.
334The bitfield is described by POS/LEN, which are immediate values,
335as above for deposit. For extract_*, the result will be extended
336to the left with zeros; for sextract_*, the result will be extended
337to the left with copies of the bitfield sign bit at pos + len - 1.
338
339For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
340at bit 8. This operation would be equivalent to
341
342 dest = (t1 << 20) >> 28
343
344(using an arithmetic right shift).
345
Richard Hendersonfce12962019-02-25 10:29:25 -0800346* extract2_i32/i64 dest, t1, t2, pos
347
348For N = {32,64}, extract an N-bit quantity from the concatenation
349of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander
350accepts 0 <= pos <= N as inputs. The backend code generator will
351not see either 0 or N as inputs for these opcodes.
352
Richard Henderson609ad702015-07-24 07:16:00 -0700353* extrl_i64_i32 t0, t1
Richard Henderson4bb7a412013-09-09 17:03:24 -0700354
Richard Henderson609ad702015-07-24 07:16:00 -0700355For 64-bit hosts only, extract the low 32-bits of input T1 and place it
356into 32-bit output T0. Depending on the host, this may be a simple move,
357or may require additional canonicalization.
358
359* extrh_i64_i32 t0, t1
360
361For 64-bit hosts only, extract the high 32-bits of input T1 and place it
362into 32-bit output T0. Depending on the host, this may be a simple shift,
363or may require additional canonicalization.
Richard Hendersonb7767f02011-01-10 19:23:42 -0800364
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800365********* Conditional moves
366
Richard Henderson5a696f62012-09-21 17:18:09 -0700367* setcond_i32/i64 dest, t1, t2, cond
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800368
369dest = (t1 cond t2)
370
371Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
372
Richard Henderson5a696f62012-09-21 17:18:09 -0700373* movcond_i32/i64 dest, c1, c2, v1, v2, cond
Richard Hendersonffc5ea02012-09-21 10:13:34 -0700374
375dest = (c1 cond c2 ? v1 : v2)
376
377Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2.
378
bellardc896fe22008-02-01 10:05:41 +0000379********* Type conversions
380
381* ext_i32_i64 t0, t1
382Convert t1 (32 bit) to t0 (64 bit) and does sign extension
383
384* extu_i32_i64 t0, t1
385Convert t1 (32 bit) to t0 (64 bit) and does zero extension
386
387* trunc_i64_i32 t0, t1
388Truncate t1 (64 bit) to t0 (32 bit)
389
pbrook36aa55d2008-09-21 13:48:32 +0000390* concat_i32_i64 t0, t1, t2
391Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
392from t2 (32 bit).
393
blueswir1945ca822008-09-21 18:32:28 +0000394* concat32_i64 t0, t1, t2
395Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
396from t2 (64 bit).
397
bellardc896fe22008-02-01 10:05:41 +0000398********* Load/Store
399
400* ld_i32/i64 t0, t1, offset
401ld8s_i32/i64 t0, t1, offset
402ld8u_i32/i64 t0, t1, offset
403ld16s_i32/i64 t0, t1, offset
404ld16u_i32/i64 t0, t1, offset
405ld32s_i64 t0, t1, offset
406ld32u_i64 t0, t1, offset
407
408t0 = read(t1 + offset)
409Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
410offset must be a constant.
411
412* st_i32/i64 t0, t1, offset
413st8_i32/i64 t0, t1, offset
414st16_i32/i64 t0, t1, offset
415st32_i64 t0, t1, offset
416
417write(t0, t1 + offset)
418Write 8, 16, 32 or 64 bits to host memory.
419
Aurelien Jarnob202d412012-10-09 21:53:08 +0200420All this opcodes assume that the pointed host memory doesn't correspond
421to a global. In the latter case the behaviour is unpredictable.
422
Richard Hendersond7156f72013-02-19 23:51:52 -0800423********* Multiword arithmetic support
424
425* add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
426* sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
427
428Similar to add/sub, except that the double-word inputs T1 and T2 are
429formed from two single-word arguments, and the double-word output T0
430is returned in two single-word outputs.
431
432* mulu2_i32/i64 t0_low, t0_high, t1, t2
433
434Similar to mul, except two unsigned inputs T1 and T2 yielding the full
435double-word product T0. The later is returned in two single-word outputs.
436
Richard Henderson4d3203f2013-02-19 23:51:53 -0800437* muls2_i32/i64 t0_low, t0_high, t1, t2
438
439Similar to mulu2, except the two inputs T1 and T2 are signed.
440
Richard Hendersond1030212018-04-17 07:18:01 -1000441* mulsh_i32/i64 t0, t1, t2
442* muluh_i32/i64 t0, t1, t2
443
444Provide the high part of a signed or unsigned multiply, respectively.
445If mulu2/muls2 are not provided by the backend, the tcg-op generator
446can obtain the same results can be obtained by emitting a pair of
447opcodes, mul+muluh/mulsh.
448
Pranith Kumarf65e19b2016-07-14 16:20:13 -0400449********* Memory Barrier support
450
451* mb <$arg>
452
453Generate a target memory barrier instruction to ensure memory ordering as being
454enforced by a corresponding guest memory barrier instruction. The ordering
455enforced by the backend may be stricter than the ordering required by the guest.
456It cannot be weaker. This opcode takes a constant argument which is required to
457generate the appropriate barrier instruction. The backend should take care to
458emit the target barrier instruction only when necessary i.e., for SMP guests and
459when MTTCG is enabled.
460
461The guest translators should generate this opcode for all guest instructions
462which have ordering side effects.
463
Philippe Mathieu-Daudéb208ac02017-07-28 19:46:04 -0300464Please see docs/devel/atomics.txt for more information on memory barriers.
Pranith Kumarf65e19b2016-07-14 16:20:13 -0400465
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800466********* 64-bit guest on 32-bit host support
Richard Hendersona38e6092010-01-07 10:07:35 -0800467
468The following opcodes are internal to TCG. Thus they are to be implemented by
46932-bit host code generators, but are not to be emitted by guest translators.
470They are emitted as needed by inline functions within "tcg-op.h".
471
Richard Henderson5a696f62012-09-21 17:18:09 -0700472* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
Richard Hendersona38e6092010-01-07 10:07:35 -0800473
474Similar to brcond, except that the 64-bit values T0 and T1
475are formed from two 32-bit arguments.
476
Richard Henderson5a696f62012-09-21 17:18:09 -0700477* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800478
479Similar to setcond, except that the 64-bit values T1 and T2 are
480formed from two 32-bit arguments. The result is a 32-bit value.
481
bellardc896fe22008-02-01 10:05:41 +0000482********* QEMU specific operations
483
Mike Frysinger759c90b2011-01-09 03:45:45 -0500484* exit_tb t0
bellardc896fe22008-02-01 10:05:41 +0000485
486Exit the current TB and return the value t0 (word type).
487
488* goto_tb index
489
490Exit the current TB and jump to the TB index 'index' (constant) if the
491current TB was linked to this TB. Otherwise execute the next
Max Filippov9bacf412012-09-21 04:18:07 +0400492instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
493at most once with each slot index per TB.
bellardc896fe22008-02-01 10:05:41 +0000494
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400495* lookup_and_goto_ptr tb_addr
496
497Look up a TB address ('tb_addr') and jump to it if valid. If not valid,
498jump to the TCG epilogue to go back to the exec loop.
499
500This operation is optional. If the TCG backend does not implement the
501goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0).
502
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700503* qemu_ld_i32/i64 t0, t1, flags, memidx
504* qemu_st_i32/i64 t0, t1, flags, memidx
bellardc896fe22008-02-01 10:05:41 +0000505
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700506Load data at the guest address t1 into t0, or store data in t0 at guest
507address t1. The _i32/_i64 size applies to the size of the input/output
508register t0 only. The address t1 is always sized according to the guest,
509and the width of the memory operation is controlled by flags.
Richard Henderson86feb1c2010-03-19 12:00:26 -0700510
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700511Both t0 and t1 may be split into little-endian ordered pairs of registers
512if dealing with 64-bit quantities on a 32-bit host.
bellardc896fe22008-02-01 10:05:41 +0000513
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700514The memidx selects the qemu tlb index to use (e.g. user or kernel access).
Tony Nguyen14776ab2019-08-24 04:10:58 +1000515The flags are the MemOp bits, selecting the sign, width, and endianness
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700516of the memory access.
bellardc896fe22008-02-01 10:05:41 +0000517
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700518For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
51964-bit memory access specified in flags.
520
Richard Hendersond2fd7452017-09-14 13:53:46 -0700521********* Host vector operations
522
523All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
524The former specifies the length of the vector in log2 64-bit units; the
525later specifies the length of the element (if applicable) in log2 8-bit units.
526E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
527
528* mov_vec v0, v1
529* ld_vec v0, t1
530* st_vec v0, t1
531
532 Move, load and store.
533
534* dup_vec v0, r1
535
536 Duplicate the low N bits of R1 into VECL/VECE copies across V0.
537
538* dupi_vec v0, c
539
540 Similarly, for a constant.
541 Smaller values will be replicated to host register size by the expanders.
542
543* dup2_vec v0, r1, r2
544
545 Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
546 only present for 32-bit hosts.
547
548* add_vec v0, v1, v2
549
550 v0 = v1 + v2, in elements across the vector.
551
552* sub_vec v0, v1, v2
553
554 Similarly, v0 = v1 - v2.
555
Richard Henderson37740302017-11-21 10:11:14 +0100556* mul_vec v0, v1, v2
557
558 Similarly, v0 = v1 * v2.
559
Richard Hendersond2fd7452017-09-14 13:53:46 -0700560* neg_vec v0, v1
561
562 Similarly, v0 = -v1.
563
Richard Hendersonbcefc902019-04-17 13:53:02 -1000564* abs_vec v0, v1
565
566 Similarly, v0 = v1 < 0 ? -v1 : v1, in elements across the vector.
567
Richard Hendersondd0a0fc2018-12-17 19:35:46 -0800568* smin_vec:
569* umin_vec:
570
571 Similarly, v0 = MIN(v1, v2), for signed and unsigned element types.
572
573* smax_vec:
574* umax_vec:
575
576 Similarly, v0 = MAX(v1, v2), for signed and unsigned element types.
577
Richard Henderson8afaf052018-12-17 18:01:47 -0800578* ssadd_vec:
579* sssub_vec:
580* usadd_vec:
581* ussub_vec:
582
583 Signed and unsigned saturating addition and subtraction. If the true
584 result is not representable within the element type, the element is
585 set to the minimum or maximum value for the type.
586
Richard Hendersond2fd7452017-09-14 13:53:46 -0700587* and_vec v0, v1, v2
588* or_vec v0, v1, v2
589* xor_vec v0, v1, v2
590* andc_vec v0, v1, v2
591* orc_vec v0, v1, v2
592* not_vec v0, v1
593
Emilio G. Cota1d349822018-03-05 17:13:30 -0500594 Similarly, logical operations with and without complement.
Richard Hendersond2fd7452017-09-14 13:53:46 -0700595 Note that VECE is unused.
596
Richard Hendersond0ec9792017-11-17 14:35:11 +0100597* shli_vec v0, v1, i2
598* shls_vec v0, v1, s2
599
600 Shift all elements from v1 by a scalar i2/s2. I.e.
601
602 for (i = 0; i < VECL/VECE; ++i) {
603 v0[i] = v1[i] << s2;
604 }
605
606* shri_vec v0, v1, i2
607* sari_vec v0, v1, i2
Richard Hendersonb0f7e742020-04-19 18:01:52 -0700608* rotli_vec v0, v1, i2
Richard Hendersond0ec9792017-11-17 14:35:11 +0100609* shrs_vec v0, v1, s2
610* sars_vec v0, v1, s2
611
Richard Hendersonb0f7e742020-04-19 18:01:52 -0700612 Similarly for logical and arithmetic right shift, and left rotate.
Richard Hendersond0ec9792017-11-17 14:35:11 +0100613
614* shlv_vec v0, v1, v2
615
616 Shift elements from v1 by elements from v2. I.e.
617
618 for (i = 0; i < VECL/VECE; ++i) {
619 v0[i] = v1[i] << v2[i];
620 }
621
622* shrv_vec v0, v1, v2
623* sarv_vec v0, v1, v2
Richard Henderson5d0ceda2020-04-19 19:47:59 -0700624* rotlv_vec v0, v1, v2
625* rotrv_vec v0, v1, v2
Richard Hendersond0ec9792017-11-17 14:35:11 +0100626
Richard Henderson5d0ceda2020-04-19 19:47:59 -0700627 Similarly for logical and arithmetic right shift, and rotates.
Richard Hendersond0ec9792017-11-17 14:35:11 +0100628
Richard Henderson212be172017-11-17 20:47:42 +0100629* cmp_vec v0, v1, v2, cond
630
631 Compare vectors by element, storing -1 for true and 0 for false.
632
Richard Henderson38dc1292019-04-30 11:02:23 -0700633* bitsel_vec v0, v1, v2, v3
634
635 Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
636
Richard Hendersonf75da292019-04-30 13:01:12 -0700637* cmpsel_vec v0, c1, c2, v3, v4, cond
638
639 Select elements based on comparison results:
640 for (i = 0; i < n; ++i) {
641 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i].
642 }
643
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700644*********
bellardc896fe22008-02-01 10:05:41 +0000645
646Note 1: Some shortcuts are defined when the last operand is known to be
647a constant (e.g. addi for add, movi for mov).
648
649Note 2: When using TCG, the opcodes must never be generated directly
650as some of them may not be available as "real" opcodes. Always use the
651function tcg_gen_xxx(args).
652
6534) Backend
654
Paolo Bonzini139c1832020-02-04 12:41:01 +0100655tcg-target.h contains the target specific definitions. tcg-target.c.inc
Peter Maydellce151102016-02-23 14:49:41 +0000656contains the target specific code; it is #included by tcg/tcg.c, rather
657than being a standalone C file.
bellardc896fe22008-02-01 10:05:41 +0000658
6594.1) Assumptions
660
661The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
66264 bit. It is expected that the pointer has the same size as the word.
663
664On a 32 bit target, all 64 bit operations are converted to 32 bits. A
665few specific operations must be implemented to allow it (see add2_i32,
666sub2_i32, brcond2_i32).
667
Stefan Weilcb8d4c82016-03-23 15:59:57 +0100668On a 64 bit target, the values are transferred between 32 and 64-bit
Aurelien Jarno870ad152015-07-27 12:41:45 +0200669registers using the following ops:
670- trunc_shr_i64_i32
671- ext_i32_i64
672- extu_i32_i64
673
674They ensure that the values are correctly truncated or extended when
675moved from a 32-bit to a 64-bit register or vice-versa. Note that the
676trunc_shr_i64_i32 is an optional op. It is not necessary to implement
677it if all the following conditions are met:
678- 64-bit registers can hold 32-bit values
679- 32-bit values in a 64-bit register do not need to stay zero or
680 sign extended
681- all 32-bit TCG ops ignore the high part of 64-bit registers
682
bellardc896fe22008-02-01 10:05:41 +0000683Floating point operations are not supported in this version. A
684previous incarnation of the code generator had full support of them,
685but it is better to concentrate on integer operations first.
686
bellardc896fe22008-02-01 10:05:41 +00006874.2) Constraints
688
689GCC like constraints are used to define the constraints of every
690instruction. Memory constraints are not supported in this
691version. Aliases are specified in the input operands as for GCC.
692
pbrook0c5f3c82008-11-04 13:17:17 +0000693The same register may be used for both an input and an output, even when
694they are not explicitly aliased. If an op expands to multiple target
695instructions then care must be taken to avoid clobbering input values.
Richard Henderson17280ff2016-11-18 17:41:24 +0100696GCC style "early clobber" outputs are supported, with '&'.
pbrook0c5f3c82008-11-04 13:17:17 +0000697
bellardc896fe22008-02-01 10:05:41 +0000698A target can define specific register or constant constraints. If an
699operation uses a constant input constraint which does not allow all
700constants, it must also accept registers in order to have a fallback.
Richard Henderson17280ff2016-11-18 17:41:24 +0100701The constraint 'i' is defined generically to accept any constant.
702The constraint 'r' is not defined generically, but is consistently
703used by each backend to indicate all registers.
bellardc896fe22008-02-01 10:05:41 +0000704
705The movi_i32 and movi_i64 operations must accept any constants.
706
707The mov_i32 and mov_i64 operations must accept any registers of the
708same type.
709
Richard Henderson17280ff2016-11-18 17:41:24 +0100710The ld/st/sti instructions must accept signed 32 bit constant offsets.
711This can be implemented by reserving a specific register in which to
712compute the address if the offset is too big.
bellardc896fe22008-02-01 10:05:41 +0000713
714The ld/st instructions must accept any destination (ld) or source (st)
715register.
716
Richard Henderson17280ff2016-11-18 17:41:24 +0100717The sti instruction may fail if it cannot store the given constant.
718
bellardc896fe22008-02-01 10:05:41 +00007194.3) Function call assumptions
720
721- The only supported types for parameters and return value are: 32 and
722 64 bit integers and pointer.
723- The stack grows downwards.
724- The first N parameters are passed in registers.
725- The next parameters are passed on the stack by storing them as words.
726- Some registers are clobbered during the call.
727- The function can return 0 or 1 value in registers. On a 32 bit
728 target, functions must be able to return 2 values in registers for
729 64 bit return type.
730
aurel3286e840e2008-12-07 15:21:23 +00007315) Recommended coding rules for best performance
bellard0a6b7b72008-05-25 18:24:40 +0000732
733- Use globals to represent the parts of the QEMU CPU state which are
734 often modified, e.g. the integer registers and the condition
735 codes. TCG will be able to use host registers to store them.
736
737- Avoid globals stored in fixed registers. They must be used only to
738 store the pointer to the CPU state and possibly to store a pointer
aurel3286e840e2008-12-07 15:21:23 +0000739 to a register window.
bellard0a6b7b72008-05-25 18:24:40 +0000740
741- Use temporaries. Use local temporaries only when really needed,
742 e.g. when you need to use a value after a jump. Local temporaries
743 introduce a performance hit in the current TCG implementation: their
744 content is saved to memory at end of each basic block.
745
746- Free temporaries and local temporaries when they are no longer used
747 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
748 should free it after it is used. Freeing temporaries does not yield
749 a better generated code, but it reduces the memory usage of TCG and
750 the speed of the translation.
751
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800752- Don't hesitate to use helpers for complicated or seldom used guest
Stefan Weilaa95e3a2011-01-07 21:34:50 +0100753 instructions. There is little performance advantage in using TCG to
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800754 implement guest instructions taking more than about twenty TCG
Peter Maydell107a47c2011-06-22 15:40:06 +0100755 instructions. Note that this rule of thumb is more applicable to
756 helpers doing complex logic or arithmetic, where the C compiler has
757 scope to do a good job of optimisation; it is less relevant where
758 the instruction is mostly doing loads and stores, and in those cases
759 inline TCG may still be faster for longer sequences.
760
761- The hard limit on the number of TCG instructions you can generate
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800762 per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
Peter Maydell107a47c2011-06-22 15:40:06 +0100763 you cannot exceed this without risking a buffer overrun.
bellard0a6b7b72008-05-25 18:24:40 +0000764
765- Use the 'discard' instruction if you know that TCG won't be able to
766 prove that a given global is "dead" at a given program point. The
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800767 x86 guest uses it to improve the condition codes optimisation.