Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Exynos4210 UART Emulation |
| 3 | * |
| 4 | * Copyright (C) 2011 Samsung Electronics Co Ltd. |
| 5 | * Maksim Kozlov, <m.kozlov@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 15 | * for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | * |
| 20 | */ |
| 21 | |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 22 | #include "hw/sysbus.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 23 | #include "sysemu/sysemu.h" |
Paolo Bonzini | dccfcd0 | 2013-04-08 16:55:25 +0200 | [diff] [blame] | 24 | #include "sysemu/char.h" |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 25 | |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 26 | #include "hw/arm/exynos4210.h" |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 27 | |
| 28 | #undef DEBUG_UART |
| 29 | #undef DEBUG_UART_EXTEND |
| 30 | #undef DEBUG_IRQ |
| 31 | #undef DEBUG_Rx_DATA |
| 32 | #undef DEBUG_Tx_DATA |
| 33 | |
| 34 | #define DEBUG_UART 0 |
| 35 | #define DEBUG_UART_EXTEND 0 |
| 36 | #define DEBUG_IRQ 0 |
| 37 | #define DEBUG_Rx_DATA 0 |
| 38 | #define DEBUG_Tx_DATA 0 |
| 39 | |
| 40 | #if DEBUG_UART |
| 41 | #define PRINT_DEBUG(fmt, args...) \ |
| 42 | do { \ |
| 43 | fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
| 44 | } while (0) |
| 45 | |
| 46 | #if DEBUG_UART_EXTEND |
| 47 | #define PRINT_DEBUG_EXTEND(fmt, args...) \ |
| 48 | do { \ |
| 49 | fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
| 50 | } while (0) |
| 51 | #else |
| 52 | #define PRINT_DEBUG_EXTEND(fmt, args...) \ |
| 53 | do {} while (0) |
| 54 | #endif /* EXTEND */ |
| 55 | |
| 56 | #else |
| 57 | #define PRINT_DEBUG(fmt, args...) \ |
| 58 | do {} while (0) |
| 59 | #define PRINT_DEBUG_EXTEND(fmt, args...) \ |
| 60 | do {} while (0) |
| 61 | #endif |
| 62 | |
| 63 | #define PRINT_ERROR(fmt, args...) \ |
| 64 | do { \ |
| 65 | fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
| 66 | } while (0) |
| 67 | |
| 68 | /* |
| 69 | * Offsets for UART registers relative to SFR base address |
| 70 | * for UARTn |
| 71 | * |
| 72 | */ |
| 73 | #define ULCON 0x0000 /* Line Control */ |
| 74 | #define UCON 0x0004 /* Control */ |
| 75 | #define UFCON 0x0008 /* FIFO Control */ |
| 76 | #define UMCON 0x000C /* Modem Control */ |
| 77 | #define UTRSTAT 0x0010 /* Tx/Rx Status */ |
| 78 | #define UERSTAT 0x0014 /* UART Error Status */ |
| 79 | #define UFSTAT 0x0018 /* FIFO Status */ |
| 80 | #define UMSTAT 0x001C /* Modem Status */ |
| 81 | #define UTXH 0x0020 /* Transmit Buffer */ |
| 82 | #define URXH 0x0024 /* Receive Buffer */ |
| 83 | #define UBRDIV 0x0028 /* Baud Rate Divisor */ |
| 84 | #define UFRACVAL 0x002C /* Divisor Fractional Value */ |
| 85 | #define UINTP 0x0030 /* Interrupt Pending */ |
| 86 | #define UINTSP 0x0034 /* Interrupt Source Pending */ |
| 87 | #define UINTM 0x0038 /* Interrupt Mask */ |
| 88 | |
| 89 | /* |
| 90 | * for indexing register in the uint32_t array |
| 91 | * |
| 92 | * 'reg' - register offset (see offsets definitions above) |
| 93 | * |
| 94 | */ |
| 95 | #define I_(reg) (reg / sizeof(uint32_t)) |
| 96 | |
| 97 | typedef struct Exynos4210UartReg { |
| 98 | const char *name; /* the only reason is the debug output */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 99 | hwaddr offset; |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 100 | uint32_t reset_value; |
| 101 | } Exynos4210UartReg; |
| 102 | |
| 103 | static Exynos4210UartReg exynos4210_uart_regs[] = { |
| 104 | {"ULCON", ULCON, 0x00000000}, |
| 105 | {"UCON", UCON, 0x00003000}, |
| 106 | {"UFCON", UFCON, 0x00000000}, |
| 107 | {"UMCON", UMCON, 0x00000000}, |
| 108 | {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */ |
| 109 | {"UERSTAT", UERSTAT, 0x00000000}, /* RO */ |
| 110 | {"UFSTAT", UFSTAT, 0x00000000}, /* RO */ |
| 111 | {"UMSTAT", UMSTAT, 0x00000000}, /* RO */ |
| 112 | {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/ |
| 113 | {"URXH", URXH, 0x00000000}, /* RO */ |
| 114 | {"UBRDIV", UBRDIV, 0x00000000}, |
| 115 | {"UFRACVAL", UFRACVAL, 0x00000000}, |
| 116 | {"UINTP", UINTP, 0x00000000}, |
| 117 | {"UINTSP", UINTSP, 0x00000000}, |
| 118 | {"UINTM", UINTM, 0x00000000}, |
| 119 | }; |
| 120 | |
| 121 | #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C |
| 122 | |
| 123 | /* UART FIFO Control */ |
| 124 | #define UFCON_FIFO_ENABLE 0x1 |
| 125 | #define UFCON_Rx_FIFO_RESET 0x2 |
| 126 | #define UFCON_Tx_FIFO_RESET 0x4 |
| 127 | #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8 |
| 128 | #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT) |
| 129 | #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4 |
| 130 | #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) |
| 131 | |
| 132 | /* Uart FIFO Status */ |
| 133 | #define UFSTAT_Rx_FIFO_COUNT 0xff |
| 134 | #define UFSTAT_Rx_FIFO_FULL 0x100 |
| 135 | #define UFSTAT_Rx_FIFO_ERROR 0x200 |
| 136 | #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16 |
| 137 | #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT) |
| 138 | #define UFSTAT_Tx_FIFO_FULL_SHIFT 24 |
| 139 | #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT) |
| 140 | |
| 141 | /* UART Interrupt Source Pending */ |
| 142 | #define UINTSP_RXD 0x1 /* Receive interrupt */ |
| 143 | #define UINTSP_ERROR 0x2 /* Error interrupt */ |
| 144 | #define UINTSP_TXD 0x4 /* Transmit interrupt */ |
| 145 | #define UINTSP_MODEM 0x8 /* Modem interrupt */ |
| 146 | |
| 147 | /* UART Line Control */ |
| 148 | #define ULCON_IR_MODE_SHIFT 6 |
| 149 | #define ULCON_PARITY_SHIFT 3 |
| 150 | #define ULCON_STOP_BIT_SHIFT 1 |
| 151 | |
| 152 | /* UART Tx/Rx Status */ |
| 153 | #define UTRSTAT_TRANSMITTER_EMPTY 0x4 |
| 154 | #define UTRSTAT_Tx_BUFFER_EMPTY 0x2 |
| 155 | #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1 |
| 156 | |
| 157 | /* UART Error Status */ |
| 158 | #define UERSTAT_OVERRUN 0x1 |
| 159 | #define UERSTAT_PARITY 0x2 |
| 160 | #define UERSTAT_FRAME 0x4 |
| 161 | #define UERSTAT_BREAK 0x8 |
| 162 | |
| 163 | typedef struct { |
| 164 | uint8_t *data; |
| 165 | uint32_t sp, rp; /* store and retrieve pointers */ |
| 166 | uint32_t size; |
| 167 | } Exynos4210UartFIFO; |
| 168 | |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 169 | #define TYPE_EXYNOS4210_UART "exynos4210.uart" |
| 170 | #define EXYNOS4210_UART(obj) \ |
| 171 | OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART) |
| 172 | |
| 173 | typedef struct Exynos4210UartState { |
| 174 | SysBusDevice parent_obj; |
| 175 | |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 176 | MemoryRegion iomem; |
| 177 | |
| 178 | uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)]; |
| 179 | Exynos4210UartFIFO rx; |
| 180 | Exynos4210UartFIFO tx; |
| 181 | |
| 182 | CharDriverState *chr; |
| 183 | qemu_irq irq; |
| 184 | |
| 185 | uint32_t channel; |
| 186 | |
| 187 | } Exynos4210UartState; |
| 188 | |
| 189 | |
| 190 | #if DEBUG_UART |
| 191 | /* Used only for debugging inside PRINT_DEBUG_... macros */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 192 | static const char *exynos4210_uart_regname(hwaddr offset) |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 193 | { |
| 194 | |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 195 | int i; |
| 196 | |
Stefan Weil | c46b07f | 2013-12-07 14:48:06 +0100 | [diff] [blame] | 197 | for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 198 | if (offset == exynos4210_uart_regs[i].offset) { |
| 199 | return exynos4210_uart_regs[i].name; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | return NULL; |
| 204 | } |
| 205 | #endif |
| 206 | |
| 207 | |
| 208 | static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch) |
| 209 | { |
| 210 | q->data[q->sp] = ch; |
| 211 | q->sp = (q->sp + 1) % q->size; |
| 212 | } |
| 213 | |
| 214 | static uint8_t fifo_retrieve(Exynos4210UartFIFO *q) |
| 215 | { |
| 216 | uint8_t ret = q->data[q->rp]; |
| 217 | q->rp = (q->rp + 1) % q->size; |
| 218 | return ret; |
| 219 | } |
| 220 | |
| 221 | static int fifo_elements_number(Exynos4210UartFIFO *q) |
| 222 | { |
| 223 | if (q->sp < q->rp) { |
| 224 | return q->size - q->rp + q->sp; |
| 225 | } |
| 226 | |
| 227 | return q->sp - q->rp; |
| 228 | } |
| 229 | |
| 230 | static int fifo_empty_elements_number(Exynos4210UartFIFO *q) |
| 231 | { |
| 232 | return q->size - fifo_elements_number(q); |
| 233 | } |
| 234 | |
| 235 | static void fifo_reset(Exynos4210UartFIFO *q) |
| 236 | { |
| 237 | if (q->data != NULL) { |
| 238 | g_free(q->data); |
| 239 | q->data = NULL; |
| 240 | } |
| 241 | |
| 242 | q->data = (uint8_t *)g_malloc0(q->size); |
| 243 | |
| 244 | q->sp = 0; |
| 245 | q->rp = 0; |
| 246 | } |
| 247 | |
| 248 | static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s) |
| 249 | { |
| 250 | uint32_t level = 0; |
| 251 | uint32_t reg; |
| 252 | |
Daniel P. Berrange | b85f62d | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 253 | reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 254 | UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; |
| 255 | |
| 256 | switch (s->channel) { |
| 257 | case 0: |
| 258 | level = reg * 32; |
| 259 | break; |
| 260 | case 1: |
| 261 | case 4: |
| 262 | level = reg * 8; |
| 263 | break; |
| 264 | case 2: |
| 265 | case 3: |
| 266 | level = reg * 2; |
| 267 | break; |
| 268 | default: |
| 269 | level = 0; |
| 270 | PRINT_ERROR("Wrong UART channel number: %d\n", s->channel); |
| 271 | } |
| 272 | |
| 273 | return level; |
| 274 | } |
| 275 | |
| 276 | static void exynos4210_uart_update_irq(Exynos4210UartState *s) |
| 277 | { |
| 278 | /* |
| 279 | * The Tx interrupt is always requested if the number of data in the |
| 280 | * transmit FIFO is smaller than the trigger level. |
| 281 | */ |
Daniel P. Berrange | b85f62d | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 282 | if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 283 | |
Daniel P. Berrange | b85f62d | 2012-04-13 11:39:06 +0000 | [diff] [blame] | 284 | uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 285 | UFSTAT_Tx_FIFO_COUNT_SHIFT; |
| 286 | |
| 287 | if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { |
| 288 | s->reg[I_(UINTSP)] |= UINTSP_TXD; |
| 289 | } |
| 290 | } |
| 291 | |
| 292 | s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; |
| 293 | |
| 294 | if (s->reg[I_(UINTP)]) { |
| 295 | qemu_irq_raise(s->irq); |
| 296 | |
| 297 | #if DEBUG_IRQ |
| 298 | fprintf(stderr, "UART%d: IRQ has been raised: %08x\n", |
| 299 | s->channel, s->reg[I_(UINTP)]); |
| 300 | #endif |
| 301 | |
| 302 | } else { |
| 303 | qemu_irq_lower(s->irq); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | static void exynos4210_uart_update_parameters(Exynos4210UartState *s) |
| 308 | { |
| 309 | int speed, parity, data_bits, stop_bits, frame_size; |
| 310 | QEMUSerialSetParams ssp; |
| 311 | uint64_t uclk_rate; |
| 312 | |
| 313 | if (s->reg[I_(UBRDIV)] == 0) { |
| 314 | return; |
| 315 | } |
| 316 | |
| 317 | frame_size = 1; /* start bit */ |
| 318 | if (s->reg[I_(ULCON)] & 0x20) { |
| 319 | frame_size++; /* parity bit */ |
| 320 | if (s->reg[I_(ULCON)] & 0x28) { |
| 321 | parity = 'E'; |
| 322 | } else { |
| 323 | parity = 'O'; |
| 324 | } |
| 325 | } else { |
| 326 | parity = 'N'; |
| 327 | } |
| 328 | |
| 329 | if (s->reg[I_(ULCON)] & 0x4) { |
| 330 | stop_bits = 2; |
| 331 | } else { |
| 332 | stop_bits = 1; |
| 333 | } |
| 334 | |
| 335 | data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; |
| 336 | |
| 337 | frame_size += data_bits + stop_bits; |
| 338 | |
| 339 | uclk_rate = 24000000; |
| 340 | |
| 341 | speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + |
| 342 | (s->reg[I_(UFRACVAL)] & 0x7) + 16); |
| 343 | |
| 344 | ssp.speed = speed; |
| 345 | ssp.parity = parity; |
| 346 | ssp.data_bits = data_bits; |
| 347 | ssp.stop_bits = stop_bits; |
| 348 | |
| 349 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
| 350 | |
| 351 | PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n", |
| 352 | s->channel, speed, parity, data_bits, stop_bits); |
| 353 | } |
| 354 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 355 | static void exynos4210_uart_write(void *opaque, hwaddr offset, |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 356 | uint64_t val, unsigned size) |
| 357 | { |
| 358 | Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 359 | uint8_t ch; |
| 360 | |
| 361 | PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel, |
| 362 | offset, exynos4210_uart_regname(offset), (long long unsigned int)val); |
| 363 | |
| 364 | switch (offset) { |
| 365 | case ULCON: |
| 366 | case UBRDIV: |
| 367 | case UFRACVAL: |
| 368 | s->reg[I_(offset)] = val; |
| 369 | exynos4210_uart_update_parameters(s); |
| 370 | break; |
| 371 | case UFCON: |
| 372 | s->reg[I_(UFCON)] = val; |
| 373 | if (val & UFCON_Rx_FIFO_RESET) { |
| 374 | fifo_reset(&s->rx); |
| 375 | s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; |
| 376 | PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel); |
| 377 | } |
| 378 | if (val & UFCON_Tx_FIFO_RESET) { |
| 379 | fifo_reset(&s->tx); |
| 380 | s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; |
| 381 | PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel); |
| 382 | } |
| 383 | break; |
| 384 | |
| 385 | case UTXH: |
| 386 | if (s->chr) { |
| 387 | s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | |
| 388 | UTRSTAT_Tx_BUFFER_EMPTY); |
| 389 | ch = (uint8_t)val; |
| 390 | qemu_chr_fe_write(s->chr, &ch, 1); |
| 391 | #if DEBUG_Tx_DATA |
| 392 | fprintf(stderr, "%c", ch); |
| 393 | #endif |
| 394 | s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | |
| 395 | UTRSTAT_Tx_BUFFER_EMPTY; |
| 396 | s->reg[I_(UINTSP)] |= UINTSP_TXD; |
| 397 | exynos4210_uart_update_irq(s); |
| 398 | } |
| 399 | break; |
| 400 | |
| 401 | case UINTP: |
| 402 | s->reg[I_(UINTP)] &= ~val; |
| 403 | s->reg[I_(UINTSP)] &= ~val; |
| 404 | PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n", |
| 405 | s->channel, offset, s->reg[I_(UINTP)]); |
| 406 | exynos4210_uart_update_irq(s); |
| 407 | break; |
| 408 | case UTRSTAT: |
| 409 | case UERSTAT: |
| 410 | case UFSTAT: |
| 411 | case UMSTAT: |
| 412 | case URXH: |
| 413 | PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n", |
| 414 | s->channel, exynos4210_uart_regname(offset), offset); |
| 415 | break; |
| 416 | case UINTSP: |
| 417 | s->reg[I_(UINTSP)] &= ~val; |
| 418 | break; |
| 419 | case UINTM: |
| 420 | s->reg[I_(UINTM)] = val; |
| 421 | exynos4210_uart_update_irq(s); |
| 422 | break; |
| 423 | case UCON: |
| 424 | case UMCON: |
| 425 | default: |
| 426 | s->reg[I_(offset)] = val; |
| 427 | break; |
| 428 | } |
| 429 | } |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 430 | static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset, |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 431 | unsigned size) |
| 432 | { |
| 433 | Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 434 | uint32_t res; |
| 435 | |
| 436 | switch (offset) { |
| 437 | case UERSTAT: /* Read Only */ |
| 438 | res = s->reg[I_(UERSTAT)]; |
| 439 | s->reg[I_(UERSTAT)] = 0; |
| 440 | return res; |
| 441 | case UFSTAT: /* Read Only */ |
| 442 | s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; |
| 443 | if (fifo_empty_elements_number(&s->rx) == 0) { |
| 444 | s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; |
| 445 | s->reg[I_(UFSTAT)] &= ~0xff; |
| 446 | } |
| 447 | return s->reg[I_(UFSTAT)]; |
| 448 | case URXH: |
| 449 | if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { |
| 450 | if (fifo_elements_number(&s->rx)) { |
| 451 | res = fifo_retrieve(&s->rx); |
| 452 | #if DEBUG_Rx_DATA |
| 453 | fprintf(stderr, "%c", res); |
| 454 | #endif |
| 455 | if (!fifo_elements_number(&s->rx)) { |
| 456 | s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; |
| 457 | } else { |
| 458 | s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 459 | } |
| 460 | } else { |
| 461 | s->reg[I_(UINTSP)] |= UINTSP_ERROR; |
| 462 | exynos4210_uart_update_irq(s); |
| 463 | res = 0; |
| 464 | } |
| 465 | } else { |
| 466 | s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; |
| 467 | res = s->reg[I_(URXH)]; |
| 468 | } |
| 469 | return res; |
| 470 | case UTXH: |
| 471 | PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n", |
| 472 | s->channel, exynos4210_uart_regname(offset), offset); |
| 473 | break; |
| 474 | default: |
| 475 | return s->reg[I_(offset)]; |
| 476 | } |
| 477 | |
| 478 | return 0; |
| 479 | } |
| 480 | |
| 481 | static const MemoryRegionOps exynos4210_uart_ops = { |
| 482 | .read = exynos4210_uart_read, |
| 483 | .write = exynos4210_uart_write, |
| 484 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 485 | .valid = { |
| 486 | .max_access_size = 4, |
| 487 | .unaligned = false |
| 488 | }, |
| 489 | }; |
| 490 | |
| 491 | static int exynos4210_uart_can_receive(void *opaque) |
| 492 | { |
| 493 | Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 494 | |
| 495 | return fifo_empty_elements_number(&s->rx); |
| 496 | } |
| 497 | |
| 498 | |
| 499 | static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) |
| 500 | { |
| 501 | Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 502 | int i; |
| 503 | |
| 504 | if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { |
| 505 | if (fifo_empty_elements_number(&s->rx) < size) { |
| 506 | for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) { |
| 507 | fifo_store(&s->rx, buf[i]); |
| 508 | } |
| 509 | s->reg[I_(UINTSP)] |= UINTSP_ERROR; |
| 510 | s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 511 | } else { |
| 512 | for (i = 0; i < size; i++) { |
| 513 | fifo_store(&s->rx, buf[i]); |
| 514 | } |
| 515 | s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 516 | } |
| 517 | /* XXX: Around here we maybe should check Rx trigger level */ |
| 518 | s->reg[I_(UINTSP)] |= UINTSP_RXD; |
| 519 | } else { |
| 520 | s->reg[I_(URXH)] = buf[0]; |
| 521 | s->reg[I_(UINTSP)] |= UINTSP_RXD; |
| 522 | s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; |
| 523 | } |
| 524 | |
| 525 | exynos4210_uart_update_irq(s); |
| 526 | } |
| 527 | |
| 528 | |
| 529 | static void exynos4210_uart_event(void *opaque, int event) |
| 530 | { |
| 531 | Exynos4210UartState *s = (Exynos4210UartState *)opaque; |
| 532 | |
| 533 | if (event == CHR_EVENT_BREAK) { |
| 534 | /* When the RxDn is held in logic 0, then a null byte is pushed into the |
| 535 | * fifo */ |
| 536 | fifo_store(&s->rx, '\0'); |
| 537 | s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; |
| 538 | exynos4210_uart_update_irq(s); |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | |
| 543 | static void exynos4210_uart_reset(DeviceState *dev) |
| 544 | { |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 545 | Exynos4210UartState *s = EXYNOS4210_UART(dev); |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 546 | int i; |
| 547 | |
Stefan Weil | c46b07f | 2013-12-07 14:48:06 +0100 | [diff] [blame] | 548 | for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) { |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 549 | s->reg[I_(exynos4210_uart_regs[i].offset)] = |
| 550 | exynos4210_uart_regs[i].reset_value; |
| 551 | } |
| 552 | |
| 553 | fifo_reset(&s->rx); |
| 554 | fifo_reset(&s->tx); |
| 555 | |
| 556 | PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); |
| 557 | } |
| 558 | |
| 559 | static const VMStateDescription vmstate_exynos4210_uart_fifo = { |
| 560 | .name = "exynos4210.uart.fifo", |
| 561 | .version_id = 1, |
| 562 | .minimum_version_id = 1, |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 563 | .fields = (VMStateField[]) { |
| 564 | VMSTATE_UINT32(sp, Exynos4210UartFIFO), |
| 565 | VMSTATE_UINT32(rp, Exynos4210UartFIFO), |
| 566 | VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size), |
| 567 | VMSTATE_END_OF_LIST() |
| 568 | } |
| 569 | }; |
| 570 | |
| 571 | static const VMStateDescription vmstate_exynos4210_uart = { |
| 572 | .name = "exynos4210.uart", |
| 573 | .version_id = 1, |
| 574 | .minimum_version_id = 1, |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 575 | .fields = (VMStateField[]) { |
| 576 | VMSTATE_STRUCT(rx, Exynos4210UartState, 1, |
| 577 | vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), |
| 578 | VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState, |
| 579 | EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)), |
| 580 | VMSTATE_END_OF_LIST() |
| 581 | } |
| 582 | }; |
| 583 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 584 | DeviceState *exynos4210_uart_create(hwaddr addr, |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 585 | int fifo_size, |
| 586 | int channel, |
| 587 | CharDriverState *chr, |
| 588 | qemu_irq irq) |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 589 | { |
| 590 | DeviceState *dev; |
| 591 | SysBusDevice *bus; |
| 592 | |
| 593 | const char chr_name[] = "serial"; |
| 594 | char label[ARRAY_SIZE(chr_name) + 1]; |
| 595 | |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 596 | dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 597 | |
| 598 | if (!chr) { |
| 599 | if (channel >= MAX_SERIAL_PORTS) { |
| 600 | hw_error("Only %d serial ports are supported by QEMU.\n", |
| 601 | MAX_SERIAL_PORTS); |
| 602 | } |
| 603 | chr = serial_hds[channel]; |
| 604 | if (!chr) { |
| 605 | snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); |
| 606 | chr = qemu_chr_new(label, "null", NULL); |
| 607 | if (!(chr)) { |
| 608 | hw_error("Can't assign serial port to UART%d.\n", channel); |
| 609 | } |
| 610 | } |
| 611 | } |
| 612 | |
| 613 | qdev_prop_set_chr(dev, "chardev", chr); |
| 614 | qdev_prop_set_uint32(dev, "channel", channel); |
| 615 | qdev_prop_set_uint32(dev, "rx-size", fifo_size); |
| 616 | qdev_prop_set_uint32(dev, "tx-size", fifo_size); |
| 617 | |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 618 | bus = SYS_BUS_DEVICE(dev); |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 619 | qdev_init_nofail(dev); |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 620 | if (addr != (hwaddr)-1) { |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 621 | sysbus_mmio_map(bus, 0, addr); |
| 622 | } |
| 623 | sysbus_connect_irq(bus, 0, irq); |
| 624 | |
| 625 | return dev; |
| 626 | } |
| 627 | |
| 628 | static int exynos4210_uart_init(SysBusDevice *dev) |
| 629 | { |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 630 | Exynos4210UartState *s = EXYNOS4210_UART(dev); |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 631 | |
| 632 | /* memory mapping */ |
Paolo Bonzini | 300b1fc | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 633 | memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s, |
| 634 | "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE); |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 635 | sysbus_init_mmio(dev, &s->iomem); |
| 636 | |
| 637 | sysbus_init_irq(dev, &s->irq); |
| 638 | |
| 639 | qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive, |
| 640 | exynos4210_uart_receive, exynos4210_uart_event, s); |
| 641 | |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | static Property exynos4210_uart_properties[] = { |
| 646 | DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr), |
| 647 | DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), |
| 648 | DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), |
| 649 | DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), |
| 650 | DEFINE_PROP_END_OF_LIST(), |
| 651 | }; |
| 652 | |
| 653 | static void exynos4210_uart_class_init(ObjectClass *klass, void *data) |
| 654 | { |
| 655 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 656 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 657 | |
| 658 | k->init = exynos4210_uart_init; |
| 659 | dc->reset = exynos4210_uart_reset; |
| 660 | dc->props = exynos4210_uart_properties; |
| 661 | dc->vmsd = &vmstate_exynos4210_uart; |
| 662 | } |
| 663 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 664 | static const TypeInfo exynos4210_uart_info = { |
Andreas Färber | 61149ff | 2013-07-24 22:21:05 +0200 | [diff] [blame] | 665 | .name = TYPE_EXYNOS4210_UART, |
Maksim Kozlov | e5a4914 | 2012-02-16 09:56:05 +0000 | [diff] [blame] | 666 | .parent = TYPE_SYS_BUS_DEVICE, |
| 667 | .instance_size = sizeof(Exynos4210UartState), |
| 668 | .class_init = exynos4210_uart_class_init, |
| 669 | }; |
| 670 | |
| 671 | static void exynos4210_uart_register(void) |
| 672 | { |
| 673 | type_register_static(&exynos4210_uart_info); |
| 674 | } |
| 675 | |
| 676 | type_init(exynos4210_uart_register) |