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j_mayer4c9649a2007-04-05 06:58:33 +00001/*
2 * Alpha emulation cpu definitions for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer4c9649a2007-04-05 06:58:33 +00004 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
j_mayer4c9649a2007-04-05 06:58:33 +000018 */
19
20#if !defined (__CPU_ALPHA_H__)
21#define __CPU_ALPHA_H__
22
23#include "config.h"
Stefan Weil2c976292012-02-01 20:51:52 +010024#include "qemu-common.h"
j_mayer4c9649a2007-04-05 06:58:33 +000025
26#define TARGET_LONG_BITS 64
Paolo Bonzinid94f0a82014-03-28 17:48:12 +010027#define ALIGNED_ONLY
j_mayer4c9649a2007-04-05 06:58:33 +000028
Andreas Färber9349b4f2012-03-14 01:38:32 +010029#define CPUArchState struct CPUAlphaState
pbrookc2764712009-03-07 15:24:59 +000030
Paolo Bonzini022c62c2012-12-17 18:19:49 +010031#include "exec/cpu-defs.h"
j_mayer4c9649a2007-04-05 06:58:33 +000032
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020033#include "fpu/softfloat.h"
j_mayer4c9649a2007-04-05 06:58:33 +000034
j_mayerf071b4d2007-10-28 00:56:24 +000035#define ELF_MACHINE EM_ALPHA
j_mayer4c9649a2007-04-05 06:58:33 +000036
37#define ICACHE_LINE_SIZE 32
38#define DCACHE_LINE_SIZE 32
39
aurel32b09d9d42009-04-07 21:47:34 +000040#define TARGET_PAGE_BITS 13
j_mayer4c9649a2007-04-05 06:58:33 +000041
Richard Henderson76393642012-05-31 16:09:39 -070042#ifdef CONFIG_USER_ONLY
43/* ??? The kernel likes to give addresses in high memory. If the host has
44 more virtual address space than the guest, this can lead to impossible
45 allocations. Honor the long-standing assumption that only kernel addrs
46 are negative, but otherwise allow allocations anywhere. This could lead
47 to tricky emulation problems for programs doing tagged addressing, but
48 that's far fewer than encounter the impossible allocation problem. */
49#define TARGET_PHYS_ADDR_SPACE_BITS 63
50#define TARGET_VIRT_ADDR_SPACE_BITS 63
51#else
Richard Henderson52705892010-03-10 14:33:23 -080052/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
Richard Henderson76393642012-05-31 16:09:39 -070053#define TARGET_PHYS_ADDR_SPACE_BITS 44
54#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
55#endif
j_mayer4c9649a2007-04-05 06:58:33 +000056
57/* Alpha major type */
58enum {
59 ALPHA_EV3 = 1,
60 ALPHA_EV4 = 2,
61 ALPHA_SIM = 3,
62 ALPHA_LCA = 4,
63 ALPHA_EV5 = 5, /* 21164 */
64 ALPHA_EV45 = 6, /* 21064A */
65 ALPHA_EV56 = 7, /* 21164A */
66};
67
68/* EV4 minor type */
69enum {
70 ALPHA_EV4_2 = 0,
71 ALPHA_EV4_3 = 1,
72};
73
74/* LCA minor type */
75enum {
76 ALPHA_LCA_1 = 1, /* 21066 */
77 ALPHA_LCA_2 = 2, /* 20166 */
78 ALPHA_LCA_3 = 3, /* 21068 */
79 ALPHA_LCA_4 = 4, /* 21068 */
80 ALPHA_LCA_5 = 5, /* 21066A */
81 ALPHA_LCA_6 = 6, /* 21068A */
82};
83
84/* EV5 minor type */
85enum {
86 ALPHA_EV5_1 = 1, /* Rev BA, CA */
87 ALPHA_EV5_2 = 2, /* Rev DA, EA */
88 ALPHA_EV5_3 = 3, /* Pass 3 */
89 ALPHA_EV5_4 = 4, /* Pass 3.2 */
90 ALPHA_EV5_5 = 5, /* Pass 4 */
91};
92
93/* EV45 minor type */
94enum {
95 ALPHA_EV45_1 = 1, /* Pass 1 */
96 ALPHA_EV45_2 = 2, /* Pass 1.1 */
97 ALPHA_EV45_3 = 3, /* Pass 2 */
98};
99
100/* EV56 minor type */
101enum {
102 ALPHA_EV56_1 = 1, /* Pass 1 */
103 ALPHA_EV56_2 = 2, /* Pass 2 */
104};
105
106enum {
107 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
108 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
109 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
110 IMPLVER_21364 = 3, /* EV7 & EV79 */
111};
112
113enum {
114 AMASK_BWX = 0x00000001,
115 AMASK_FIX = 0x00000002,
116 AMASK_CIX = 0x00000004,
117 AMASK_MVI = 0x00000100,
118 AMASK_TRAP = 0x00000200,
119 AMASK_PREFETCH = 0x00001000,
120};
121
122enum {
123 VAX_ROUND_NORMAL = 0,
124 VAX_ROUND_CHOPPED,
125};
126
127enum {
128 IEEE_ROUND_NORMAL = 0,
129 IEEE_ROUND_DYNAMIC,
130 IEEE_ROUND_PLUS,
131 IEEE_ROUND_MINUS,
132 IEEE_ROUND_CHOPPED,
133};
134
135/* IEEE floating-point operations encoding */
136/* Trap mode */
137enum {
138 FP_TRAP_I = 0x0,
139 FP_TRAP_U = 0x1,
140 FP_TRAP_S = 0x4,
141 FP_TRAP_SU = 0x5,
142 FP_TRAP_SUI = 0x7,
143};
144
145/* Rounding mode */
146enum {
147 FP_ROUND_CHOPPED = 0x0,
148 FP_ROUND_MINUS = 0x1,
149 FP_ROUND_NORMAL = 0x2,
150 FP_ROUND_DYNAMIC = 0x3,
151};
152
Richard Hendersonba0e2762009-12-09 15:56:29 -0800153/* FPCR bits */
154#define FPCR_SUM (1ULL << 63)
155#define FPCR_INED (1ULL << 62)
156#define FPCR_UNFD (1ULL << 61)
157#define FPCR_UNDZ (1ULL << 60)
158#define FPCR_DYN_SHIFT 58
Richard Henderson8443eff2009-12-31 12:41:07 -0800159#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
160#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
161#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
162#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
Richard Hendersonba0e2762009-12-09 15:56:29 -0800163#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
164#define FPCR_IOV (1ULL << 57)
165#define FPCR_INE (1ULL << 56)
166#define FPCR_UNF (1ULL << 55)
167#define FPCR_OVF (1ULL << 54)
168#define FPCR_DZE (1ULL << 53)
169#define FPCR_INV (1ULL << 52)
170#define FPCR_OVFD (1ULL << 51)
171#define FPCR_DZED (1ULL << 50)
172#define FPCR_INVD (1ULL << 49)
173#define FPCR_DNZ (1ULL << 48)
174#define FPCR_DNOD (1ULL << 47)
175#define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
176 | FPCR_OVF | FPCR_DZE | FPCR_INV)
177
178/* The silly software trap enables implemented by the kernel emulation.
179 These are more or less architecturally required, since the real hardware
180 has read-as-zero bits in the FPCR when the features aren't implemented.
181 For the purposes of QEMU, we pretend the FPCR can hold everything. */
182#define SWCR_TRAP_ENABLE_INV (1ULL << 1)
183#define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
184#define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
185#define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
186#define SWCR_TRAP_ENABLE_INE (1ULL << 5)
187#define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
188#define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
189
190#define SWCR_MAP_DMZ (1ULL << 12)
191#define SWCR_MAP_UMZ (1ULL << 13)
192#define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
193
194#define SWCR_STATUS_INV (1ULL << 17)
195#define SWCR_STATUS_DZE (1ULL << 18)
196#define SWCR_STATUS_OVF (1ULL << 19)
197#define SWCR_STATUS_UNF (1ULL << 20)
198#define SWCR_STATUS_INE (1ULL << 21)
199#define SWCR_STATUS_DNO (1ULL << 22)
200#define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
201
202#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
203
Richard Henderson84178452011-05-20 13:11:25 -0700204/* MMU modes definitions */
j_mayer4c9649a2007-04-05 06:58:33 +0000205
Richard Henderson84178452011-05-20 13:11:25 -0700206/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
207 The Unix PALcode only exposes the kernel and user modes; presumably
208 executive and supervisor are used by VMS.
209
210 PALcode itself uses physical mode for code and kernel mode for data;
211 there are PALmode instructions that can access data via physical mode
212 or via an os-installed "alternate mode", which is one of the 4 above.
213
214 QEMU does not currently properly distinguish between code/data when
215 looking up addresses. To avoid having to address this issue, our
216 emulated PALcode will cheat and use the KSEG mapping for its code+data
217 rather than physical addresses.
218
219 Moreover, we're only emulating Unix PALcode, and not attempting VMS.
220
221 All of which allows us to drop all but kernel and user modes.
222 Elide the unused MMU modes to save space. */
223
224#define NB_MMU_MODES 2
225
226#define MMU_MODE0_SUFFIX _kernel
227#define MMU_MODE1_SUFFIX _user
228#define MMU_KERNEL_IDX 0
229#define MMU_USER_IDX 1
230
231typedef struct CPUAlphaState CPUAlphaState;
j_mayer6ebbf392007-10-14 07:07:08 +0000232
j_mayer4c9649a2007-04-05 06:58:33 +0000233struct CPUAlphaState {
234 uint64_t ir[31];
Richard Henderson8443eff2009-12-31 12:41:07 -0800235 float64 fir[31];
j_mayer4c9649a2007-04-05 06:58:33 +0000236 uint64_t pc;
j_mayer4c9649a2007-04-05 06:58:33 +0000237 uint64_t unique;
Richard Henderson6910b8f2010-04-07 15:42:26 -0700238 uint64_t lock_addr;
239 uint64_t lock_st_addr;
240 uint64_t lock_value;
Richard Henderson8443eff2009-12-31 12:41:07 -0800241 float_status fp_status;
242 /* The following fields make up the FPCR, but in FP_STATUS format. */
243 uint8_t fpcr_exc_status;
244 uint8_t fpcr_exc_mask;
245 uint8_t fpcr_dyn_round;
246 uint8_t fpcr_flush_to_zero;
Richard Henderson8443eff2009-12-31 12:41:07 -0800247 uint8_t fpcr_dnod;
248 uint8_t fpcr_undz;
249
Richard Henderson129d8aa2011-05-20 13:30:00 -0700250 /* The Internal Processor Registers. Some of these we assume always
251 exist for use in user-mode. */
252 uint8_t ps;
Richard Henderson8443eff2009-12-31 12:41:07 -0800253 uint8_t intr_flag;
Richard Henderson129d8aa2011-05-20 13:30:00 -0700254 uint8_t pal_mode;
Richard Henderson26b46092011-05-23 12:12:29 -0700255 uint8_t fen;
256
257 uint32_t pcc_ofs;
Richard Henderson129d8aa2011-05-20 13:30:00 -0700258
259 /* These pass data from the exception logic in the translator and
260 helpers to the OS entry point. This is used for both system
261 emulation and user-mode. */
262 uint64_t trap_arg0;
263 uint64_t trap_arg1;
264 uint64_t trap_arg2;
j_mayer4c9649a2007-04-05 06:58:33 +0000265
Richard Henderson26b46092011-05-23 12:12:29 -0700266#if !defined(CONFIG_USER_ONLY)
267 /* The internal data required by our emulation of the Unix PALcode. */
268 uint64_t exc_addr;
269 uint64_t palbr;
270 uint64_t ptbr;
271 uint64_t vptptr;
272 uint64_t sysval;
273 uint64_t usp;
274 uint64_t shadow[8];
275 uint64_t scratch[24];
276#endif
277
Richard Hendersonc781cf92011-04-28 10:40:08 -0700278 /* This alarm doesn't exist in real hardware; we wish it did. */
Richard Hendersonc781cf92011-04-28 10:40:08 -0700279 uint64_t alarm_expire;
280
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200281 /* Those resources are used only in QEMU core */
j_mayer4c9649a2007-04-05 06:58:33 +0000282 CPU_COMMON
283
j_mayer4c9649a2007-04-05 06:58:33 +0000284 int error_code;
j_mayer4c9649a2007-04-05 06:58:33 +0000285
286 uint32_t features;
287 uint32_t amask;
288 int implver;
j_mayer4c9649a2007-04-05 06:58:33 +0000289};
290
Andreas Färber494342b2012-10-15 17:44:21 +0200291#define cpu_list alpha_cpu_list
ths9467d442007-06-03 21:02:38 +0000292#define cpu_exec cpu_alpha_exec
293#define cpu_gen_code cpu_alpha_gen_code
294#define cpu_signal_handler cpu_alpha_signal_handler
295
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100296#include "exec/cpu-all.h"
Andreas Färber25ebd802012-04-06 19:46:48 +0200297#include "cpu-qom.h"
j_mayer4c9649a2007-04-05 06:58:33 +0000298
299enum {
300 FEATURE_ASN = 0x00000001,
301 FEATURE_SPS = 0x00000002,
302 FEATURE_VIRBND = 0x00000004,
303 FEATURE_TBCHK = 0x00000008,
304};
305
306enum {
Richard Henderson07b6c132011-05-20 14:04:57 -0700307 EXCP_RESET,
308 EXCP_MCHK,
309 EXCP_SMP_INTERRUPT,
310 EXCP_CLK_INTERRUPT,
311 EXCP_DEV_INTERRUPT,
312 EXCP_MMFAULT,
313 EXCP_UNALIGN,
314 EXCP_OPCDEC,
315 EXCP_ARITH,
316 EXCP_FEN,
317 EXCP_CALL_PAL,
318 /* For Usermode emulation. */
319 EXCP_STL_C,
320 EXCP_STQ_C,
j_mayer4c9649a2007-04-05 06:58:33 +0000321};
322
Richard Henderson6a80e082011-04-18 15:09:09 -0700323/* Alpha-specific interrupt pending bits. */
324#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
325#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
326#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
327
Richard Hendersona3b9af12011-04-18 15:59:21 -0700328/* OSF/1 Page table bits. */
329enum {
330 PTE_VALID = 0x0001,
331 PTE_FOR = 0x0002, /* used for page protection (fault on read) */
332 PTE_FOW = 0x0004, /* used for page protection (fault on write) */
333 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
334 PTE_ASM = 0x0010,
335 PTE_KRE = 0x0100,
336 PTE_URE = 0x0200,
337 PTE_KWE = 0x1000,
338 PTE_UWE = 0x2000
339};
340
Richard Hendersonea879fc2011-04-18 14:19:17 -0700341/* Hardware interrupt (entInt) constants. */
342enum {
343 INT_K_IP,
344 INT_K_CLK,
345 INT_K_MCHK,
346 INT_K_DEV,
347 INT_K_PERF,
348};
349
350/* Memory management (entMM) constants. */
351enum {
352 MM_K_TNV,
353 MM_K_ACV,
354 MM_K_FOR,
355 MM_K_FOE,
356 MM_K_FOW
357};
358
359/* Arithmetic exception (entArith) constants. */
360enum {
361 EXC_M_SWC = 1, /* Software completion */
362 EXC_M_INV = 2, /* Invalid operation */
363 EXC_M_DZE = 4, /* Division by zero */
364 EXC_M_FOV = 8, /* Overflow */
365 EXC_M_UNF = 16, /* Underflow */
366 EXC_M_INE = 32, /* Inexact result */
367 EXC_M_IOV = 64 /* Integer Overflow */
368};
369
370/* Processor status constants. */
371enum {
372 /* Low 3 bits are interrupt mask level. */
373 PS_INT_MASK = 7,
374
375 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
376 The Unix PALcode only uses bit 4. */
377 PS_USER_MODE = 8
378};
379
Andreas Färber4d5712f2012-03-14 01:38:21 +0100380static inline int cpu_mmu_index(CPUAlphaState *env)
Richard Hendersonea879fc2011-04-18 14:19:17 -0700381{
Richard Hendersonbba9bdc2011-05-20 14:14:44 -0700382 if (env->pal_mode) {
383 return MMU_KERNEL_IDX;
384 } else if (env->ps & PS_USER_MODE) {
385 return MMU_USER_IDX;
386 } else {
387 return MMU_KERNEL_IDX;
388 }
Richard Hendersonea879fc2011-04-18 14:19:17 -0700389}
j_mayer4c9649a2007-04-05 06:58:33 +0000390
391enum {
j_mayer4c9649a2007-04-05 06:58:33 +0000392 IR_V0 = 0,
393 IR_T0 = 1,
394 IR_T1 = 2,
395 IR_T2 = 3,
396 IR_T3 = 4,
397 IR_T4 = 5,
398 IR_T5 = 6,
399 IR_T6 = 7,
400 IR_T7 = 8,
401 IR_S0 = 9,
402 IR_S1 = 10,
403 IR_S2 = 11,
404 IR_S3 = 12,
405 IR_S4 = 13,
406 IR_S5 = 14,
407 IR_S6 = 15,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700408 IR_FP = IR_S6,
j_mayer4c9649a2007-04-05 06:58:33 +0000409 IR_A0 = 16,
410 IR_A1 = 17,
411 IR_A2 = 18,
412 IR_A3 = 19,
413 IR_A4 = 20,
414 IR_A5 = 21,
415 IR_T8 = 22,
416 IR_T9 = 23,
417 IR_T10 = 24,
418 IR_T11 = 25,
419 IR_RA = 26,
420 IR_T12 = 27,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700421 IR_PV = IR_T12,
j_mayer4c9649a2007-04-05 06:58:33 +0000422 IR_AT = 28,
423 IR_GP = 29,
424 IR_SP = 30,
425 IR_ZERO = 31,
426};
427
Andreas Färber0c282462012-10-15 17:33:32 +0200428void alpha_translate_init(void);
429
Andreas Färber5f5e3352012-10-15 17:52:00 +0200430AlphaCPU *cpu_alpha_init(const char *cpu_model);
431
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300432#define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
Andreas Färber5f5e3352012-10-15 17:52:00 +0200433
Andreas Färber494342b2012-10-15 17:44:21 +0200434void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
j_mayere96efcf2007-04-14 12:17:09 +0000435int cpu_alpha_exec(CPUAlphaState *s);
436/* you can call this signal handler from your SIGBUS and SIGSEGV
437 signal handlers to inform the virtual CPU of exceptions. non zero
438 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000439int cpu_alpha_signal_handler(int host_signum, void *pinfo,
j_mayere96efcf2007-04-14 12:17:09 +0000440 void *puc);
Andreas Färber75104542013-08-26 03:01:33 +0200441int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
442 int mmu_idx);
Blue Swirl20503962012-04-09 14:20:20 +0000443void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
444void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
445void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
aurel3295870352008-12-11 22:42:42 +0000446
Andreas Färber4d5712f2012-03-14 01:38:21 +0100447uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
448void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
Richard Henderson5b450402011-04-18 16:13:12 -0700449#ifndef CONFIG_USER_ONLY
Andreas Färber4d5712f2012-03-14 01:38:21 +0100450void swap_shadow_regs(CPUAlphaState *env);
Andreas Färberc658b942013-05-27 06:49:53 +0200451QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
452 bool is_write, bool is_exec,
453 int unused, unsigned size);
Richard Henderson5b450402011-04-18 16:13:12 -0700454#endif
j_mayer4c9649a2007-04-05 06:58:33 +0000455
Richard Hendersona18ad892011-05-23 12:30:22 -0700456/* Bits in TB->FLAGS that control how translation is processed. */
457enum {
458 TB_FLAGS_PAL_MODE = 1,
459 TB_FLAGS_FEN = 2,
460 TB_FLAGS_USER_MODE = 8,
461
462 TB_FLAGS_AMASK_SHIFT = 4,
463 TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
464 TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
465 TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
466 TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
467 TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
468 TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
469};
470
Andreas Färber4d5712f2012-03-14 01:38:21 +0100471static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
Richard Hendersona18ad892011-05-23 12:30:22 -0700472 target_ulong *cs_base, int *pflags)
aliguori6b917542008-11-18 19:46:41 +0000473{
Richard Hendersona18ad892011-05-23 12:30:22 -0700474 int flags = 0;
475
aliguori6b917542008-11-18 19:46:41 +0000476 *pc = env->pc;
477 *cs_base = 0;
Richard Hendersona18ad892011-05-23 12:30:22 -0700478
479 if (env->pal_mode) {
480 flags = TB_FLAGS_PAL_MODE;
481 } else {
482 flags = env->ps & PS_USER_MODE;
483 }
484 if (env->fen) {
485 flags |= TB_FLAGS_FEN;
486 }
487 flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
488
489 *pflags = flags;
aliguori6b917542008-11-18 19:46:41 +0000490}
491
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100492#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +0000493
j_mayer4c9649a2007-04-05 06:58:33 +0000494#endif /* !defined (__CPU_ALPHA_H__) */