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bellard6508fe52005-01-15 12:02:56 +00001/*
2 * QEMU Parallel PORT emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellarde57a8c02005-11-10 23:58:52 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5867c882007-02-17 23:44:43 +00005 * Copyright (c) 2007 Marko Kohtala
ths5fafdf22007-09-16 21:08:06 +00006 *
bellard6508fe52005-01-15 12:02:56 +00007 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020025
Peter Maydellb6a0aa02016-01-26 18:17:03 +000026#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010027#include "qapi/error.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020028#include "qemu/module.h"
Marc-André Lureau7566c6e2017-01-26 17:33:39 +040029#include "chardev/char-parallel.h"
Marc-André Lureau4d43a602017-01-26 18:26:44 +040030#include "chardev/char-fe.h"
Gerd Hoffmanned003c82020-05-15 17:04:12 +020031#include "hw/acpi/aml-build.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020032#include "hw/irq.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010033#include "hw/isa/isa.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020034#include "hw/qdev-properties.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020035#include "migration/vmstate.h"
Philippe Mathieu-Daudébb3d5ea2018-03-08 23:39:22 +010036#include "hw/char/parallel.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020037#include "sysemu/reset.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010038#include "sysemu/sysemu.h"
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -030039#include "trace.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040040#include "qom/object.h"
bellard6508fe52005-01-15 12:02:56 +000041
42//#define DEBUG_PARALLEL
43
ths5867c882007-02-17 23:44:43 +000044#ifdef DEBUG_PARALLEL
Blue Swirl001faf32009-05-13 17:53:17 +000045#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
ths5867c882007-02-17 23:44:43 +000046#else
Blue Swirl001faf32009-05-13 17:53:17 +000047#define pdebug(fmt, ...) ((void)0)
ths5867c882007-02-17 23:44:43 +000048#endif
49
50#define PARA_REG_DATA 0
51#define PARA_REG_STS 1
52#define PARA_REG_CTR 2
53#define PARA_REG_EPP_ADDR 3
54#define PARA_REG_EPP_DATA 4
55
bellard6508fe52005-01-15 12:02:56 +000056/*
57 * These are the definitions for the Printer Status Register
58 */
59#define PARA_STS_BUSY 0x80 /* Busy complement */
60#define PARA_STS_ACK 0x40 /* Acknowledge */
61#define PARA_STS_PAPER 0x20 /* Out of paper */
62#define PARA_STS_ONLINE 0x10 /* Online */
63#define PARA_STS_ERROR 0x08 /* Error complement */
ths5867c882007-02-17 23:44:43 +000064#define PARA_STS_TMOUT 0x01 /* EPP timeout */
bellard6508fe52005-01-15 12:02:56 +000065
66/*
67 * These are the definitions for the Printer Control Register
68 */
ths5867c882007-02-17 23:44:43 +000069#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
bellard6508fe52005-01-15 12:02:56 +000070#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
71#define PARA_CTR_SELECT 0x08 /* Select In complement */
72#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
73#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
74#define PARA_CTR_STROBE 0x01 /* Strobe complement */
75
ths5867c882007-02-17 23:44:43 +000076#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
77
Blue Swirldefdb202011-02-05 14:51:57 +000078typedef struct ParallelState {
Avi Kivity63858cd2011-10-06 16:44:26 +020079 MemoryRegion iomem;
ths5867c882007-02-17 23:44:43 +000080 uint8_t dataw;
81 uint8_t datar;
82 uint8_t status;
bellard6508fe52005-01-15 12:02:56 +000083 uint8_t control;
pbrookd537cf62007-04-07 18:14:41 +000084 qemu_irq irq;
bellard6508fe52005-01-15 12:02:56 +000085 int irq_pending;
Marc-André Lureaubecdfa02016-10-22 12:52:51 +030086 CharBackend chr;
bellarde57a8c02005-11-10 23:58:52 +000087 int hw_driver;
ths5867c882007-02-17 23:44:43 +000088 int epp_timeout;
89 uint32_t last_read_offset; /* For debugging */
thsd60532c2007-06-18 18:55:46 +000090 /* Memory-mapped interface */
thsd60532c2007-06-18 18:55:46 +000091 int it_shift;
Marc-André Lureaue305a162016-07-13 02:11:59 +020092 PortioList portio_list;
Blue Swirldefdb202011-02-05 14:51:57 +000093} ParallelState;
bellard6508fe52005-01-15 12:02:56 +000094
Andreas Färberb0dc5ee2013-04-27 22:18:45 +020095#define TYPE_ISA_PARALLEL "isa-parallel"
Eduardo Habkost80633962020-09-16 14:25:19 -040096OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL)
Andreas Färberb0dc5ee2013-04-27 22:18:45 +020097
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040098struct ISAParallelState {
Andreas Färberb0dc5ee2013-04-27 22:18:45 +020099 ISADevice parent_obj;
100
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200101 uint32_t index;
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200102 uint32_t iobase;
103 uint32_t isairq;
104 ParallelState state;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -0400105};
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200106
bellard6508fe52005-01-15 12:02:56 +0000107static void parallel_update_irq(ParallelState *s)
108{
109 if (s->irq_pending)
pbrookd537cf62007-04-07 18:14:41 +0000110 qemu_irq_raise(s->irq);
bellard6508fe52005-01-15 12:02:56 +0000111 else
pbrookd537cf62007-04-07 18:14:41 +0000112 qemu_irq_lower(s->irq);
bellard6508fe52005-01-15 12:02:56 +0000113}
114
ths5867c882007-02-17 23:44:43 +0000115static void
116parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
bellard6508fe52005-01-15 12:02:56 +0000117{
118 ParallelState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000119
bellard6508fe52005-01-15 12:02:56 +0000120 addr &= 7;
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300121 trace_parallel_ioport_write("SW", addr, val);
bellard6508fe52005-01-15 12:02:56 +0000122 switch(addr) {
ths5867c882007-02-17 23:44:43 +0000123 case PARA_REG_DATA:
ths0fa7f152007-06-07 21:07:11 +0000124 s->dataw = val;
125 parallel_update_irq(s);
bellard6508fe52005-01-15 12:02:56 +0000126 break;
ths5867c882007-02-17 23:44:43 +0000127 case PARA_REG_CTR:
balrog52ccc5e2008-02-10 13:34:48 +0000128 val |= 0xc0;
ths0fa7f152007-06-07 21:07:11 +0000129 if ((val & PARA_CTR_INIT) == 0 ) {
130 s->status = PARA_STS_BUSY;
131 s->status |= PARA_STS_ACK;
132 s->status |= PARA_STS_ONLINE;
133 s->status |= PARA_STS_ERROR;
134 }
135 else if (val & PARA_CTR_SELECT) {
136 if (val & PARA_CTR_STROBE) {
137 s->status &= ~PARA_STS_BUSY;
138 if ((s->control & PARA_CTR_STROBE) == 0)
Daniel P. Berrange6ab3fc32016-09-06 14:56:04 +0100139 /* XXX this blocks entire thread. Rewrite to use
140 * qemu_chr_fe_write and background I/O callbacks */
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300141 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1);
ths0fa7f152007-06-07 21:07:11 +0000142 } else {
143 if (s->control & PARA_CTR_INTEN) {
144 s->irq_pending = 1;
145 }
146 }
147 }
148 parallel_update_irq(s);
149 s->control = val;
bellard6508fe52005-01-15 12:02:56 +0000150 break;
151 }
152}
153
ths5867c882007-02-17 23:44:43 +0000154static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
155{
156 ParallelState *s = opaque;
157 uint8_t parm = val;
aurel32563e3c62008-08-22 08:57:09 +0000158 int dir;
ths5867c882007-02-17 23:44:43 +0000159
160 /* Sometimes programs do several writes for timing purposes on old
161 HW. Take care not to waste time on writes that do nothing. */
162
163 s->last_read_offset = ~0U;
164
165 addr &= 7;
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300166 trace_parallel_ioport_write("HW", addr, val);
ths5867c882007-02-17 23:44:43 +0000167 switch(addr) {
168 case PARA_REG_DATA:
169 if (s->dataw == val)
ths0fa7f152007-06-07 21:07:11 +0000170 return;
171 pdebug("wd%02x\n", val);
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300172 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
ths0fa7f152007-06-07 21:07:11 +0000173 s->dataw = val;
ths5867c882007-02-17 23:44:43 +0000174 break;
175 case PARA_REG_STS:
ths0fa7f152007-06-07 21:07:11 +0000176 pdebug("ws%02x\n", val);
177 if (val & PARA_STS_TMOUT)
178 s->epp_timeout = 0;
179 break;
ths5867c882007-02-17 23:44:43 +0000180 case PARA_REG_CTR:
181 val |= 0xc0;
182 if (s->control == val)
ths0fa7f152007-06-07 21:07:11 +0000183 return;
184 pdebug("wc%02x\n", val);
aurel32563e3c62008-08-22 08:57:09 +0000185
186 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
187 if (val & PARA_CTR_DIR) {
188 dir = 1;
189 } else {
190 dir = 0;
191 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300192 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
aurel32563e3c62008-08-22 08:57:09 +0000193 parm &= ~PARA_CTR_DIR;
194 }
195
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300196 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
ths0fa7f152007-06-07 21:07:11 +0000197 s->control = val;
ths5867c882007-02-17 23:44:43 +0000198 break;
199 case PARA_REG_EPP_ADDR:
ths0fa7f152007-06-07 21:07:11 +0000200 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
201 /* Controls not correct for EPP address cycle, so do nothing */
202 pdebug("wa%02x s\n", val);
203 else {
204 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300205 if (qemu_chr_fe_ioctl(&s->chr,
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300206 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000207 s->epp_timeout = 1;
208 pdebug("wa%02x t\n", val);
209 }
210 else
211 pdebug("wa%02x\n", val);
212 }
213 break;
ths5867c882007-02-17 23:44:43 +0000214 case PARA_REG_EPP_DATA:
ths0fa7f152007-06-07 21:07:11 +0000215 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
216 /* Controls not correct for EPP data cycle, so do nothing */
217 pdebug("we%02x s\n", val);
218 else {
219 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300220 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000221 s->epp_timeout = 1;
222 pdebug("we%02x t\n", val);
223 }
224 else
225 pdebug("we%02x\n", val);
226 }
227 break;
ths5867c882007-02-17 23:44:43 +0000228 }
229}
230
231static void
232parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
233{
234 ParallelState *s = opaque;
235 uint16_t eppdata = cpu_to_le16(val);
236 int err;
237 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000238 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000239 };
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300240
241 trace_parallel_ioport_write("EPP", addr, val);
ths5867c882007-02-17 23:44:43 +0000242 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
ths0fa7f152007-06-07 21:07:11 +0000243 /* Controls not correct for EPP data cycle, so do nothing */
244 pdebug("we%04x s\n", val);
245 return;
ths5867c882007-02-17 23:44:43 +0000246 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300247 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
ths5867c882007-02-17 23:44:43 +0000248 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000249 s->epp_timeout = 1;
250 pdebug("we%04x t\n", val);
ths5867c882007-02-17 23:44:43 +0000251 }
252 else
ths0fa7f152007-06-07 21:07:11 +0000253 pdebug("we%04x\n", val);
ths5867c882007-02-17 23:44:43 +0000254}
255
256static void
257parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
258{
259 ParallelState *s = opaque;
260 uint32_t eppdata = cpu_to_le32(val);
261 int err;
262 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000263 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000264 };
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300265
266 trace_parallel_ioport_write("EPP", addr, val);
ths5867c882007-02-17 23:44:43 +0000267 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
ths0fa7f152007-06-07 21:07:11 +0000268 /* Controls not correct for EPP data cycle, so do nothing */
269 pdebug("we%08x s\n", val);
270 return;
ths5867c882007-02-17 23:44:43 +0000271 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300272 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
ths5867c882007-02-17 23:44:43 +0000273 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000274 s->epp_timeout = 1;
275 pdebug("we%08x t\n", val);
ths5867c882007-02-17 23:44:43 +0000276 }
277 else
ths0fa7f152007-06-07 21:07:11 +0000278 pdebug("we%08x\n", val);
ths5867c882007-02-17 23:44:43 +0000279}
280
281static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
bellard6508fe52005-01-15 12:02:56 +0000282{
283 ParallelState *s = opaque;
284 uint32_t ret = 0xff;
285
286 addr &= 7;
287 switch(addr) {
ths5867c882007-02-17 23:44:43 +0000288 case PARA_REG_DATA:
ths0fa7f152007-06-07 21:07:11 +0000289 if (s->control & PARA_CTR_DIR)
290 ret = s->datar;
291 else
292 ret = s->dataw;
bellard6508fe52005-01-15 12:02:56 +0000293 break;
ths5867c882007-02-17 23:44:43 +0000294 case PARA_REG_STS:
ths0fa7f152007-06-07 21:07:11 +0000295 ret = s->status;
296 s->irq_pending = 0;
297 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
298 /* XXX Fixme: wait 5 microseconds */
299 if (s->status & PARA_STS_ACK)
300 s->status &= ~PARA_STS_ACK;
301 else {
302 /* XXX Fixme: wait 5 microseconds */
303 s->status |= PARA_STS_ACK;
304 s->status |= PARA_STS_BUSY;
305 }
306 }
307 parallel_update_irq(s);
bellard6508fe52005-01-15 12:02:56 +0000308 break;
ths5867c882007-02-17 23:44:43 +0000309 case PARA_REG_CTR:
bellard6508fe52005-01-15 12:02:56 +0000310 ret = s->control;
311 break;
312 }
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300313 trace_parallel_ioport_read("SW", addr, ret);
ths5867c882007-02-17 23:44:43 +0000314 return ret;
315}
316
317static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
318{
319 ParallelState *s = opaque;
320 uint8_t ret = 0xff;
321 addr &= 7;
322 switch(addr) {
323 case PARA_REG_DATA:
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300324 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
ths0fa7f152007-06-07 21:07:11 +0000325 if (s->last_read_offset != addr || s->datar != ret)
326 pdebug("rd%02x\n", ret);
ths5867c882007-02-17 23:44:43 +0000327 s->datar = ret;
328 break;
329 case PARA_REG_STS:
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300330 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ths0fa7f152007-06-07 21:07:11 +0000331 ret &= ~PARA_STS_TMOUT;
332 if (s->epp_timeout)
333 ret |= PARA_STS_TMOUT;
334 if (s->last_read_offset != addr || s->status != ret)
335 pdebug("rs%02x\n", ret);
336 s->status = ret;
ths5867c882007-02-17 23:44:43 +0000337 break;
338 case PARA_REG_CTR:
339 /* s->control has some bits fixed to 1. It is zero only when
ths0fa7f152007-06-07 21:07:11 +0000340 it has not been yet written to. */
341 if (s->control == 0) {
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300342 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
ths0fa7f152007-06-07 21:07:11 +0000343 if (s->last_read_offset != addr)
344 pdebug("rc%02x\n", ret);
345 s->control = ret;
346 }
347 else {
348 ret = s->control;
349 if (s->last_read_offset != addr)
350 pdebug("rc%02x\n", ret);
351 }
ths5867c882007-02-17 23:44:43 +0000352 break;
353 case PARA_REG_EPP_ADDR:
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300354 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
355 (PARA_CTR_DIR | PARA_CTR_INIT))
ths0fa7f152007-06-07 21:07:11 +0000356 /* Controls not correct for EPP addr cycle, so do nothing */
357 pdebug("ra%02x s\n", ret);
358 else {
359 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300360 if (qemu_chr_fe_ioctl(&s->chr,
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300361 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000362 s->epp_timeout = 1;
363 pdebug("ra%02x t\n", ret);
364 }
365 else
366 pdebug("ra%02x\n", ret);
367 }
368 break;
ths5867c882007-02-17 23:44:43 +0000369 case PARA_REG_EPP_DATA:
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300370 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
371 (PARA_CTR_DIR | PARA_CTR_INIT))
ths0fa7f152007-06-07 21:07:11 +0000372 /* Controls not correct for EPP data cycle, so do nothing */
373 pdebug("re%02x s\n", ret);
374 else {
375 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300376 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000377 s->epp_timeout = 1;
378 pdebug("re%02x t\n", ret);
379 }
380 else
381 pdebug("re%02x\n", ret);
382 }
383 break;
ths5867c882007-02-17 23:44:43 +0000384 }
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300385 trace_parallel_ioport_read("HW", addr, ret);
ths5867c882007-02-17 23:44:43 +0000386 s->last_read_offset = addr;
387 return ret;
388}
389
390static uint32_t
391parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
392{
393 ParallelState *s = opaque;
394 uint32_t ret;
395 uint16_t eppdata = ~0;
396 int err;
397 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000398 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000399 };
400 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
ths0fa7f152007-06-07 21:07:11 +0000401 /* Controls not correct for EPP data cycle, so do nothing */
402 pdebug("re%04x s\n", eppdata);
403 return eppdata;
ths5867c882007-02-17 23:44:43 +0000404 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300405 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ths5867c882007-02-17 23:44:43 +0000406 ret = le16_to_cpu(eppdata);
407
408 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000409 s->epp_timeout = 1;
410 pdebug("re%04x t\n", ret);
ths5867c882007-02-17 23:44:43 +0000411 }
412 else
ths0fa7f152007-06-07 21:07:11 +0000413 pdebug("re%04x\n", ret);
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300414 trace_parallel_ioport_read("EPP", addr, ret);
ths5867c882007-02-17 23:44:43 +0000415 return ret;
416}
417
418static uint32_t
419parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
420{
421 ParallelState *s = opaque;
422 uint32_t ret;
423 uint32_t eppdata = ~0U;
424 int err;
425 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000426 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000427 };
428 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
ths0fa7f152007-06-07 21:07:11 +0000429 /* Controls not correct for EPP data cycle, so do nothing */
430 pdebug("re%08x s\n", eppdata);
431 return eppdata;
ths5867c882007-02-17 23:44:43 +0000432 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300433 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ths5867c882007-02-17 23:44:43 +0000434 ret = le32_to_cpu(eppdata);
435
436 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000437 s->epp_timeout = 1;
438 pdebug("re%08x t\n", ret);
ths5867c882007-02-17 23:44:43 +0000439 }
440 else
ths0fa7f152007-06-07 21:07:11 +0000441 pdebug("re%08x\n", ret);
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300442 trace_parallel_ioport_read("EPP", addr, ret);
ths5867c882007-02-17 23:44:43 +0000443 return ret;
444}
445
446static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
447{
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300448 trace_parallel_ioport_write("ECP", addr & 7, val);
Blue Swirl7f5b7d32010-04-25 18:58:25 +0000449 pdebug("wecp%d=%02x\n", addr & 7, val);
ths5867c882007-02-17 23:44:43 +0000450}
451
452static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
453{
454 uint8_t ret = 0xff;
Blue Swirl7f5b7d32010-04-25 18:58:25 +0000455
Philippe Mathieu-Daudécb2d7212018-06-21 14:12:50 -0300456 trace_parallel_ioport_read("ECP", addr & 7, ret);
Blue Swirl7f5b7d32010-04-25 18:58:25 +0000457 pdebug("recp%d:%02x\n", addr & 7, ret);
bellard6508fe52005-01-15 12:02:56 +0000458 return ret;
459}
460
aurel3233093a02008-12-07 23:26:09 +0000461static void parallel_reset(void *opaque)
bellard6508fe52005-01-15 12:02:56 +0000462{
aurel3233093a02008-12-07 23:26:09 +0000463 ParallelState *s = opaque;
464
ths5867c882007-02-17 23:44:43 +0000465 s->datar = ~0;
466 s->dataw = ~0;
bellard6508fe52005-01-15 12:02:56 +0000467 s->status = PARA_STS_BUSY;
468 s->status |= PARA_STS_ACK;
469 s->status |= PARA_STS_ONLINE;
470 s->status |= PARA_STS_ERROR;
balrog52ccc5e2008-02-10 13:34:48 +0000471 s->status |= PARA_STS_TMOUT;
bellard6508fe52005-01-15 12:02:56 +0000472 s->control = PARA_CTR_SELECT;
473 s->control |= PARA_CTR_INIT;
balrog52ccc5e2008-02-10 13:34:48 +0000474 s->control |= 0xc0;
ths5867c882007-02-17 23:44:43 +0000475 s->irq_pending = 0;
ths5867c882007-02-17 23:44:43 +0000476 s->hw_driver = 0;
477 s->epp_timeout = 0;
478 s->last_read_offset = ~0U;
thsd60532c2007-06-18 18:55:46 +0000479}
480
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200481static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
482
Richard Henderson1922abd2011-08-15 15:55:09 -0700483static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
484 { 0, 8, 1,
485 .read = parallel_ioport_read_hw,
486 .write = parallel_ioport_write_hw },
487 { 4, 1, 2,
488 .read = parallel_ioport_eppdata_read_hw2,
489 .write = parallel_ioport_eppdata_write_hw2 },
490 { 4, 1, 4,
491 .read = parallel_ioport_eppdata_read_hw4,
492 .write = parallel_ioport_eppdata_write_hw4 },
493 { 0x400, 8, 1,
494 .read = parallel_ioport_ecp_read,
495 .write = parallel_ioport_ecp_write },
496 PORTIO_END_OF_LIST(),
497};
498
499static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
500 { 0, 8, 1,
501 .read = parallel_ioport_read_sw,
502 .write = parallel_ioport_write_sw },
503 PORTIO_END_OF_LIST(),
504};
505
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400506
507static const VMStateDescription vmstate_parallel_isa = {
508 .name = "parallel_isa",
509 .version_id = 1,
510 .minimum_version_id = 1,
511 .fields = (VMStateField[]) {
512 VMSTATE_UINT8(state.dataw, ISAParallelState),
513 VMSTATE_UINT8(state.datar, ISAParallelState),
514 VMSTATE_UINT8(state.status, ISAParallelState),
515 VMSTATE_UINT8(state.control, ISAParallelState),
516 VMSTATE_INT32(state.irq_pending, ISAParallelState),
517 VMSTATE_INT32(state.epp_timeout, ISAParallelState),
518 VMSTATE_END_OF_LIST()
519 }
520};
521
Peng Hao98fab4c2017-07-12 23:41:59 +0800522static int parallel_can_receive(void *opaque)
523{
524 return 1;
525}
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400526
Andreas Färberdb895a12012-11-25 02:37:14 +0100527static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
thsd60532c2007-06-18 18:55:46 +0000528{
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200529 static int index;
Andreas Färberdb895a12012-11-25 02:37:14 +0100530 ISADevice *isadev = ISA_DEVICE(dev);
Andreas Färberb0dc5ee2013-04-27 22:18:45 +0200531 ISAParallelState *isa = ISA_PARALLEL(dev);
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200532 ParallelState *s = &isa->state;
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200533 int base;
thsd60532c2007-06-18 18:55:46 +0000534 uint8_t dummy;
535
Anton Nefedov30650702017-07-06 15:08:52 +0300536 if (!qemu_chr_fe_backend_connected(&s->chr)) {
Andreas Färberdb895a12012-11-25 02:37:14 +0100537 error_setg(errp, "Can't create parallel device, empty char device");
538 return;
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200539 }
540
Andreas Färberdb895a12012-11-25 02:37:14 +0100541 if (isa->index == -1) {
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200542 isa->index = index;
Andreas Färberdb895a12012-11-25 02:37:14 +0100543 }
544 if (isa->index >= MAX_PARALLEL_PORTS) {
545 error_setg(errp, "Max. supported number of parallel ports is %d.",
546 MAX_PARALLEL_PORTS);
547 return;
548 }
549 if (isa->iobase == -1) {
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200550 isa->iobase = isa_parallel_io[isa->index];
Andreas Färberdb895a12012-11-25 02:37:14 +0100551 }
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200552 index++;
553
554 base = isa->iobase;
Andreas Färberdb895a12012-11-25 02:37:14 +0100555 isa_init_irq(isadev, &s->irq, isa->isairq);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200556 qemu_register_reset(parallel_reset, s);
bellard6508fe52005-01-15 12:02:56 +0000557
Peng Hao98fab4c2017-07-12 23:41:59 +0800558 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL,
559 NULL, NULL, s, NULL, true);
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300560 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
ths5867c882007-02-17 23:44:43 +0000561 s->hw_driver = 1;
ths0fa7f152007-06-07 21:07:11 +0000562 s->status = dummy;
ths5867c882007-02-17 23:44:43 +0000563 }
564
Marc-André Lureaue305a162016-07-13 02:11:59 +0200565 isa_register_portio_list(isadev, &s->portio_list, base,
Richard Henderson1922abd2011-08-15 15:55:09 -0700566 (s->hw_driver
567 ? &isa_parallel_portio_hw_list[0]
568 : &isa_parallel_portio_sw_list[0]),
569 s, "parallel");
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200570}
571
Gerd Hoffmanned003c82020-05-15 17:04:12 +0200572static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope)
573{
574 ISAParallelState *isa = ISA_PARALLEL(isadev);
575 Aml *dev;
576 Aml *crs;
577
578 crs = aml_resource_template();
579 aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08));
580 aml_append(crs, aml_irq_no_flags(isa->isairq));
581
582 dev = aml_device("LPT%d", isa->index + 1);
583 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
584 aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1)));
585 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
586 aml_append(dev, aml_name_decl("_CRS", crs));
587
588 aml_append(scope, dev);
589}
590
thsd60532c2007-06-18 18:55:46 +0000591/* Memory mapped interface */
Peter Maydell05b49402018-06-15 14:57:13 +0100592static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size)
thsd60532c2007-06-18 18:55:46 +0000593{
594 ParallelState *s = opaque;
595
Peter Maydell05b49402018-06-15 14:57:13 +0100596 return parallel_ioport_read_sw(s, addr >> s->it_shift) &
597 MAKE_64BIT_MASK(0, size * 8);
thsd60532c2007-06-18 18:55:46 +0000598}
599
Peter Maydell05b49402018-06-15 14:57:13 +0100600static void parallel_mm_writefn(void *opaque, hwaddr addr,
601 uint64_t value, unsigned size)
thsd60532c2007-06-18 18:55:46 +0000602{
603 ParallelState *s = opaque;
604
Peter Maydell05b49402018-06-15 14:57:13 +0100605 parallel_ioport_write_sw(s, addr >> s->it_shift,
606 value & MAKE_64BIT_MASK(0, size * 8));
thsd60532c2007-06-18 18:55:46 +0000607}
608
Avi Kivity63858cd2011-10-06 16:44:26 +0200609static const MemoryRegionOps parallel_mm_ops = {
Peter Maydell05b49402018-06-15 14:57:13 +0100610 .read = parallel_mm_readfn,
611 .write = parallel_mm_writefn,
612 .valid.min_access_size = 1,
613 .valid.max_access_size = 4,
Avi Kivity63858cd2011-10-06 16:44:26 +0200614 .endianness = DEVICE_NATIVE_ENDIAN,
thsd60532c2007-06-18 18:55:46 +0000615};
616
617/* If fd is zero, it means that the parallel device uses the console */
Avi Kivity63858cd2011-10-06 16:44:26 +0200618bool parallel_mm_init(MemoryRegion *address_space,
Avi Kivitya8170e52012-10-23 12:30:10 +0200619 hwaddr base, int it_shift, qemu_irq irq,
Marc-André Lureau0ec7b3e2016-12-07 16:20:22 +0300620 Chardev *chr)
thsd60532c2007-06-18 18:55:46 +0000621{
622 ParallelState *s;
thsd60532c2007-06-18 18:55:46 +0000623
Anthony Liguori7267c092011-08-20 22:09:37 -0500624 s = g_malloc0(sizeof(ParallelState));
aurel3233093a02008-12-07 23:26:09 +0000625 s->irq = irq;
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300626 qemu_chr_fe_init(&s->chr, chr, &error_abort);
thsd60532c2007-06-18 18:55:46 +0000627 s->it_shift = it_shift;
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200628 qemu_register_reset(parallel_reset, s);
thsd60532c2007-06-18 18:55:46 +0000629
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400630 memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
Avi Kivity63858cd2011-10-06 16:44:26 +0200631 "parallel", 8 << it_shift);
632 memory_region_add_subregion(address_space, base, &s->iomem);
Blue Swirldefdb202011-02-05 14:51:57 +0000633 return true;
thsd60532c2007-06-18 18:55:46 +0000634}
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200635
Anthony Liguori39bffca2011-12-07 21:34:16 -0600636static Property parallel_isa_properties[] = {
637 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
Paolo Bonzinic7bcc852014-02-08 11:01:53 +0100638 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600639 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
640 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
641 DEFINE_PROP_END_OF_LIST(),
642};
643
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600644static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
645{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600646 DeviceClass *dc = DEVICE_CLASS(klass);
Gerd Hoffmanned003c82020-05-15 17:04:12 +0200647 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
Andreas Färberdb895a12012-11-25 02:37:14 +0100648
649 dc->realize = parallel_isa_realizefn;
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400650 dc->vmsd = &vmstate_parallel_isa;
Gerd Hoffmanned003c82020-05-15 17:04:12 +0200651 isa->build_aml = parallel_isa_build_aml;
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400652 device_class_set_props(dc, parallel_isa_properties);
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300653 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600654}
655
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100656static const TypeInfo parallel_isa_info = {
Andreas Färberb0dc5ee2013-04-27 22:18:45 +0200657 .name = TYPE_ISA_PARALLEL,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600658 .parent = TYPE_ISA_DEVICE,
659 .instance_size = sizeof(ISAParallelState),
660 .class_init = parallel_isa_class_initfn,
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200661};
662
Andreas Färber83f7d432012-02-09 15:20:55 +0100663static void parallel_register_types(void)
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200664{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600665 type_register_static(&parallel_isa_info);
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200666}
667
Andreas Färber83f7d432012-02-09 15:20:55 +0100668type_init(parallel_register_types)