bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Parallel PORT emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | e57a8c0 | 2005-11-10 23:58:52 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 5 | * Copyright (c) 2007 Marko Kohtala |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6 | * |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 25 | |
Peter Maydell | b6a0aa0 | 2016-01-26 18:17:03 +0000 | [diff] [blame] | 26 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 27 | #include "qapi/error.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 28 | #include "qemu/module.h" |
Marc-André Lureau | 7566c6e | 2017-01-26 17:33:39 +0400 | [diff] [blame] | 29 | #include "chardev/char-parallel.h" |
Marc-André Lureau | 4d43a60 | 2017-01-26 18:26:44 +0400 | [diff] [blame] | 30 | #include "chardev/char-fe.h" |
Gerd Hoffmann | ed003c8 | 2020-05-15 17:04:12 +0200 | [diff] [blame] | 31 | #include "hw/acpi/aml-build.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 32 | #include "hw/irq.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 33 | #include "hw/isa/isa.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 34 | #include "hw/qdev-properties.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 35 | #include "migration/vmstate.h" |
Philippe Mathieu-Daudé | bb3d5ea | 2018-03-08 23:39:22 +0100 | [diff] [blame] | 36 | #include "hw/char/parallel.h" |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 37 | #include "sysemu/reset.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 38 | #include "sysemu/sysemu.h" |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 39 | #include "trace.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 40 | #include "qom/object.h" |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 41 | |
| 42 | //#define DEBUG_PARALLEL |
| 43 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 44 | #ifdef DEBUG_PARALLEL |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 45 | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 46 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 47 | #define pdebug(fmt, ...) ((void)0) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 48 | #endif |
| 49 | |
| 50 | #define PARA_REG_DATA 0 |
| 51 | #define PARA_REG_STS 1 |
| 52 | #define PARA_REG_CTR 2 |
| 53 | #define PARA_REG_EPP_ADDR 3 |
| 54 | #define PARA_REG_EPP_DATA 4 |
| 55 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 56 | /* |
| 57 | * These are the definitions for the Printer Status Register |
| 58 | */ |
| 59 | #define PARA_STS_BUSY 0x80 /* Busy complement */ |
| 60 | #define PARA_STS_ACK 0x40 /* Acknowledge */ |
| 61 | #define PARA_STS_PAPER 0x20 /* Out of paper */ |
| 62 | #define PARA_STS_ONLINE 0x10 /* Online */ |
| 63 | #define PARA_STS_ERROR 0x08 /* Error complement */ |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 64 | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 65 | |
| 66 | /* |
| 67 | * These are the definitions for the Printer Control Register |
| 68 | */ |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 69 | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 70 | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
| 71 | #define PARA_CTR_SELECT 0x08 /* Select In complement */ |
| 72 | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
| 73 | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
| 74 | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
| 75 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 76 | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) |
| 77 | |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 78 | typedef struct ParallelState { |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 79 | MemoryRegion iomem; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 80 | uint8_t dataw; |
| 81 | uint8_t datar; |
| 82 | uint8_t status; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 83 | uint8_t control; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 84 | qemu_irq irq; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 85 | int irq_pending; |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 86 | CharBackend chr; |
bellard | e57a8c0 | 2005-11-10 23:58:52 +0000 | [diff] [blame] | 87 | int hw_driver; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 88 | int epp_timeout; |
| 89 | uint32_t last_read_offset; /* For debugging */ |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 90 | /* Memory-mapped interface */ |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 91 | int it_shift; |
Marc-André Lureau | e305a16 | 2016-07-13 02:11:59 +0200 | [diff] [blame] | 92 | PortioList portio_list; |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 93 | } ParallelState; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 94 | |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 95 | #define TYPE_ISA_PARALLEL "isa-parallel" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 96 | OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL) |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 97 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 98 | struct ISAParallelState { |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 99 | ISADevice parent_obj; |
| 100 | |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 101 | uint32_t index; |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 102 | uint32_t iobase; |
| 103 | uint32_t isairq; |
| 104 | ParallelState state; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 105 | }; |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 106 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 107 | static void parallel_update_irq(ParallelState *s) |
| 108 | { |
| 109 | if (s->irq_pending) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 110 | qemu_irq_raise(s->irq); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 111 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 112 | qemu_irq_lower(s->irq); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 113 | } |
| 114 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 115 | static void |
| 116 | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 117 | { |
| 118 | ParallelState *s = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 119 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 120 | addr &= 7; |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 121 | trace_parallel_ioport_write("SW", addr, val); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 122 | switch(addr) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 123 | case PARA_REG_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 124 | s->dataw = val; |
| 125 | parallel_update_irq(s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 126 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 127 | case PARA_REG_CTR: |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 128 | val |= 0xc0; |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 129 | if ((val & PARA_CTR_INIT) == 0 ) { |
| 130 | s->status = PARA_STS_BUSY; |
| 131 | s->status |= PARA_STS_ACK; |
| 132 | s->status |= PARA_STS_ONLINE; |
| 133 | s->status |= PARA_STS_ERROR; |
| 134 | } |
| 135 | else if (val & PARA_CTR_SELECT) { |
| 136 | if (val & PARA_CTR_STROBE) { |
| 137 | s->status &= ~PARA_STS_BUSY; |
| 138 | if ((s->control & PARA_CTR_STROBE) == 0) |
Daniel P. Berrange | 6ab3fc3 | 2016-09-06 14:56:04 +0100 | [diff] [blame] | 139 | /* XXX this blocks entire thread. Rewrite to use |
| 140 | * qemu_chr_fe_write and background I/O callbacks */ |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 141 | qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 142 | } else { |
| 143 | if (s->control & PARA_CTR_INTEN) { |
| 144 | s->irq_pending = 1; |
| 145 | } |
| 146 | } |
| 147 | } |
| 148 | parallel_update_irq(s); |
| 149 | s->control = val; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 150 | break; |
| 151 | } |
| 152 | } |
| 153 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 154 | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
| 155 | { |
| 156 | ParallelState *s = opaque; |
| 157 | uint8_t parm = val; |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 158 | int dir; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 159 | |
| 160 | /* Sometimes programs do several writes for timing purposes on old |
| 161 | HW. Take care not to waste time on writes that do nothing. */ |
| 162 | |
| 163 | s->last_read_offset = ~0U; |
| 164 | |
| 165 | addr &= 7; |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 166 | trace_parallel_ioport_write("HW", addr, val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 167 | switch(addr) { |
| 168 | case PARA_REG_DATA: |
| 169 | if (s->dataw == val) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 170 | return; |
| 171 | pdebug("wd%02x\n", val); |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 172 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 173 | s->dataw = val; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 174 | break; |
| 175 | case PARA_REG_STS: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 176 | pdebug("ws%02x\n", val); |
| 177 | if (val & PARA_STS_TMOUT) |
| 178 | s->epp_timeout = 0; |
| 179 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 180 | case PARA_REG_CTR: |
| 181 | val |= 0xc0; |
| 182 | if (s->control == val) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 183 | return; |
| 184 | pdebug("wc%02x\n", val); |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 185 | |
| 186 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { |
| 187 | if (val & PARA_CTR_DIR) { |
| 188 | dir = 1; |
| 189 | } else { |
| 190 | dir = 0; |
| 191 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 192 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 193 | parm &= ~PARA_CTR_DIR; |
| 194 | } |
| 195 | |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 196 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 197 | s->control = val; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 198 | break; |
| 199 | case PARA_REG_EPP_ADDR: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 200 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
| 201 | /* Controls not correct for EPP address cycle, so do nothing */ |
| 202 | pdebug("wa%02x s\n", val); |
| 203 | else { |
| 204 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 205 | if (qemu_chr_fe_ioctl(&s->chr, |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 206 | CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 207 | s->epp_timeout = 1; |
| 208 | pdebug("wa%02x t\n", val); |
| 209 | } |
| 210 | else |
| 211 | pdebug("wa%02x\n", val); |
| 212 | } |
| 213 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 214 | case PARA_REG_EPP_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 215 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
| 216 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 217 | pdebug("we%02x s\n", val); |
| 218 | else { |
| 219 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 220 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 221 | s->epp_timeout = 1; |
| 222 | pdebug("we%02x t\n", val); |
| 223 | } |
| 224 | else |
| 225 | pdebug("we%02x\n", val); |
| 226 | } |
| 227 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 228 | } |
| 229 | } |
| 230 | |
| 231 | static void |
| 232 | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) |
| 233 | { |
| 234 | ParallelState *s = opaque; |
| 235 | uint16_t eppdata = cpu_to_le16(val); |
| 236 | int err; |
| 237 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 238 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 239 | }; |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 240 | |
| 241 | trace_parallel_ioport_write("EPP", addr, val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 242 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 243 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 244 | pdebug("we%04x s\n", val); |
| 245 | return; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 246 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 247 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 248 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 249 | s->epp_timeout = 1; |
| 250 | pdebug("we%04x t\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 251 | } |
| 252 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 253 | pdebug("we%04x\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | static void |
| 257 | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) |
| 258 | { |
| 259 | ParallelState *s = opaque; |
| 260 | uint32_t eppdata = cpu_to_le32(val); |
| 261 | int err; |
| 262 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 263 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 264 | }; |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 265 | |
| 266 | trace_parallel_ioport_write("EPP", addr, val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 267 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 268 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 269 | pdebug("we%08x s\n", val); |
| 270 | return; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 271 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 272 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 273 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 274 | s->epp_timeout = 1; |
| 275 | pdebug("we%08x t\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 276 | } |
| 277 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 278 | pdebug("we%08x\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 282 | { |
| 283 | ParallelState *s = opaque; |
| 284 | uint32_t ret = 0xff; |
| 285 | |
| 286 | addr &= 7; |
| 287 | switch(addr) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 288 | case PARA_REG_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 289 | if (s->control & PARA_CTR_DIR) |
| 290 | ret = s->datar; |
| 291 | else |
| 292 | ret = s->dataw; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 293 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 294 | case PARA_REG_STS: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 295 | ret = s->status; |
| 296 | s->irq_pending = 0; |
| 297 | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
| 298 | /* XXX Fixme: wait 5 microseconds */ |
| 299 | if (s->status & PARA_STS_ACK) |
| 300 | s->status &= ~PARA_STS_ACK; |
| 301 | else { |
| 302 | /* XXX Fixme: wait 5 microseconds */ |
| 303 | s->status |= PARA_STS_ACK; |
| 304 | s->status |= PARA_STS_BUSY; |
| 305 | } |
| 306 | } |
| 307 | parallel_update_irq(s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 308 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 309 | case PARA_REG_CTR: |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 310 | ret = s->control; |
| 311 | break; |
| 312 | } |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 313 | trace_parallel_ioport_read("SW", addr, ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 314 | return ret; |
| 315 | } |
| 316 | |
| 317 | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
| 318 | { |
| 319 | ParallelState *s = opaque; |
| 320 | uint8_t ret = 0xff; |
| 321 | addr &= 7; |
| 322 | switch(addr) { |
| 323 | case PARA_REG_DATA: |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 324 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 325 | if (s->last_read_offset != addr || s->datar != ret) |
| 326 | pdebug("rd%02x\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 327 | s->datar = ret; |
| 328 | break; |
| 329 | case PARA_REG_STS: |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 330 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 331 | ret &= ~PARA_STS_TMOUT; |
| 332 | if (s->epp_timeout) |
| 333 | ret |= PARA_STS_TMOUT; |
| 334 | if (s->last_read_offset != addr || s->status != ret) |
| 335 | pdebug("rs%02x\n", ret); |
| 336 | s->status = ret; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 337 | break; |
| 338 | case PARA_REG_CTR: |
| 339 | /* s->control has some bits fixed to 1. It is zero only when |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 340 | it has not been yet written to. */ |
| 341 | if (s->control == 0) { |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 342 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 343 | if (s->last_read_offset != addr) |
| 344 | pdebug("rc%02x\n", ret); |
| 345 | s->control = ret; |
| 346 | } |
| 347 | else { |
| 348 | ret = s->control; |
| 349 | if (s->last_read_offset != addr) |
| 350 | pdebug("rc%02x\n", ret); |
| 351 | } |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 352 | break; |
| 353 | case PARA_REG_EPP_ADDR: |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 354 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
| 355 | (PARA_CTR_DIR | PARA_CTR_INIT)) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 356 | /* Controls not correct for EPP addr cycle, so do nothing */ |
| 357 | pdebug("ra%02x s\n", ret); |
| 358 | else { |
| 359 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 360 | if (qemu_chr_fe_ioctl(&s->chr, |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 361 | CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 362 | s->epp_timeout = 1; |
| 363 | pdebug("ra%02x t\n", ret); |
| 364 | } |
| 365 | else |
| 366 | pdebug("ra%02x\n", ret); |
| 367 | } |
| 368 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 369 | case PARA_REG_EPP_DATA: |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 370 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
| 371 | (PARA_CTR_DIR | PARA_CTR_INIT)) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 372 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 373 | pdebug("re%02x s\n", ret); |
| 374 | else { |
| 375 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 376 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 377 | s->epp_timeout = 1; |
| 378 | pdebug("re%02x t\n", ret); |
| 379 | } |
| 380 | else |
| 381 | pdebug("re%02x\n", ret); |
| 382 | } |
| 383 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 384 | } |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 385 | trace_parallel_ioport_read("HW", addr, ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 386 | s->last_read_offset = addr; |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | static uint32_t |
| 391 | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) |
| 392 | { |
| 393 | ParallelState *s = opaque; |
| 394 | uint32_t ret; |
| 395 | uint16_t eppdata = ~0; |
| 396 | int err; |
| 397 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 398 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 399 | }; |
| 400 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 401 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 402 | pdebug("re%04x s\n", eppdata); |
| 403 | return eppdata; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 404 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 405 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 406 | ret = le16_to_cpu(eppdata); |
| 407 | |
| 408 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 409 | s->epp_timeout = 1; |
| 410 | pdebug("re%04x t\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 411 | } |
| 412 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 413 | pdebug("re%04x\n", ret); |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 414 | trace_parallel_ioport_read("EPP", addr, ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 415 | return ret; |
| 416 | } |
| 417 | |
| 418 | static uint32_t |
| 419 | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) |
| 420 | { |
| 421 | ParallelState *s = opaque; |
| 422 | uint32_t ret; |
| 423 | uint32_t eppdata = ~0U; |
| 424 | int err; |
| 425 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 426 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 427 | }; |
| 428 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 429 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 430 | pdebug("re%08x s\n", eppdata); |
| 431 | return eppdata; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 432 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 433 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 434 | ret = le32_to_cpu(eppdata); |
| 435 | |
| 436 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 437 | s->epp_timeout = 1; |
| 438 | pdebug("re%08x t\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 439 | } |
| 440 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 441 | pdebug("re%08x\n", ret); |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 442 | trace_parallel_ioport_read("EPP", addr, ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 443 | return ret; |
| 444 | } |
| 445 | |
| 446 | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
| 447 | { |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 448 | trace_parallel_ioport_write("ECP", addr & 7, val); |
Blue Swirl | 7f5b7d3 | 2010-04-25 18:58:25 +0000 | [diff] [blame] | 449 | pdebug("wecp%d=%02x\n", addr & 7, val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
| 453 | { |
| 454 | uint8_t ret = 0xff; |
Blue Swirl | 7f5b7d3 | 2010-04-25 18:58:25 +0000 | [diff] [blame] | 455 | |
Philippe Mathieu-Daudé | cb2d721 | 2018-06-21 14:12:50 -0300 | [diff] [blame] | 456 | trace_parallel_ioport_read("ECP", addr & 7, ret); |
Blue Swirl | 7f5b7d3 | 2010-04-25 18:58:25 +0000 | [diff] [blame] | 457 | pdebug("recp%d:%02x\n", addr & 7, ret); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 458 | return ret; |
| 459 | } |
| 460 | |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 461 | static void parallel_reset(void *opaque) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 462 | { |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 463 | ParallelState *s = opaque; |
| 464 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 465 | s->datar = ~0; |
| 466 | s->dataw = ~0; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 467 | s->status = PARA_STS_BUSY; |
| 468 | s->status |= PARA_STS_ACK; |
| 469 | s->status |= PARA_STS_ONLINE; |
| 470 | s->status |= PARA_STS_ERROR; |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 471 | s->status |= PARA_STS_TMOUT; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 472 | s->control = PARA_CTR_SELECT; |
| 473 | s->control |= PARA_CTR_INIT; |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 474 | s->control |= 0xc0; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 475 | s->irq_pending = 0; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 476 | s->hw_driver = 0; |
| 477 | s->epp_timeout = 0; |
| 478 | s->last_read_offset = ~0U; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 479 | } |
| 480 | |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 481 | static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
| 482 | |
Richard Henderson | 1922abd | 2011-08-15 15:55:09 -0700 | [diff] [blame] | 483 | static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
| 484 | { 0, 8, 1, |
| 485 | .read = parallel_ioport_read_hw, |
| 486 | .write = parallel_ioport_write_hw }, |
| 487 | { 4, 1, 2, |
| 488 | .read = parallel_ioport_eppdata_read_hw2, |
| 489 | .write = parallel_ioport_eppdata_write_hw2 }, |
| 490 | { 4, 1, 4, |
| 491 | .read = parallel_ioport_eppdata_read_hw4, |
| 492 | .write = parallel_ioport_eppdata_write_hw4 }, |
| 493 | { 0x400, 8, 1, |
| 494 | .read = parallel_ioport_ecp_read, |
| 495 | .write = parallel_ioport_ecp_write }, |
| 496 | PORTIO_END_OF_LIST(), |
| 497 | }; |
| 498 | |
| 499 | static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { |
| 500 | { 0, 8, 1, |
| 501 | .read = parallel_ioport_read_sw, |
| 502 | .write = parallel_ioport_write_sw }, |
| 503 | PORTIO_END_OF_LIST(), |
| 504 | }; |
| 505 | |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 506 | |
| 507 | static const VMStateDescription vmstate_parallel_isa = { |
| 508 | .name = "parallel_isa", |
| 509 | .version_id = 1, |
| 510 | .minimum_version_id = 1, |
| 511 | .fields = (VMStateField[]) { |
| 512 | VMSTATE_UINT8(state.dataw, ISAParallelState), |
| 513 | VMSTATE_UINT8(state.datar, ISAParallelState), |
| 514 | VMSTATE_UINT8(state.status, ISAParallelState), |
| 515 | VMSTATE_UINT8(state.control, ISAParallelState), |
| 516 | VMSTATE_INT32(state.irq_pending, ISAParallelState), |
| 517 | VMSTATE_INT32(state.epp_timeout, ISAParallelState), |
| 518 | VMSTATE_END_OF_LIST() |
| 519 | } |
| 520 | }; |
| 521 | |
Peng Hao | 98fab4c | 2017-07-12 23:41:59 +0800 | [diff] [blame] | 522 | static int parallel_can_receive(void *opaque) |
| 523 | { |
| 524 | return 1; |
| 525 | } |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 526 | |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 527 | static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 528 | { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 529 | static int index; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 530 | ISADevice *isadev = ISA_DEVICE(dev); |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 531 | ISAParallelState *isa = ISA_PARALLEL(dev); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 532 | ParallelState *s = &isa->state; |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 533 | int base; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 534 | uint8_t dummy; |
| 535 | |
Anton Nefedov | 3065070 | 2017-07-06 15:08:52 +0300 | [diff] [blame] | 536 | if (!qemu_chr_fe_backend_connected(&s->chr)) { |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 537 | error_setg(errp, "Can't create parallel device, empty char device"); |
| 538 | return; |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 539 | } |
| 540 | |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 541 | if (isa->index == -1) { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 542 | isa->index = index; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 543 | } |
| 544 | if (isa->index >= MAX_PARALLEL_PORTS) { |
| 545 | error_setg(errp, "Max. supported number of parallel ports is %d.", |
| 546 | MAX_PARALLEL_PORTS); |
| 547 | return; |
| 548 | } |
| 549 | if (isa->iobase == -1) { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 550 | isa->iobase = isa_parallel_io[isa->index]; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 551 | } |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 552 | index++; |
| 553 | |
| 554 | base = isa->iobase; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 555 | isa_init_irq(isadev, &s->irq, isa->isairq); |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 556 | qemu_register_reset(parallel_reset, s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 557 | |
Peng Hao | 98fab4c | 2017-07-12 23:41:59 +0800 | [diff] [blame] | 558 | qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, |
| 559 | NULL, NULL, s, NULL, true); |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 560 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 561 | s->hw_driver = 1; |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 562 | s->status = dummy; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 563 | } |
| 564 | |
Marc-André Lureau | e305a16 | 2016-07-13 02:11:59 +0200 | [diff] [blame] | 565 | isa_register_portio_list(isadev, &s->portio_list, base, |
Richard Henderson | 1922abd | 2011-08-15 15:55:09 -0700 | [diff] [blame] | 566 | (s->hw_driver |
| 567 | ? &isa_parallel_portio_hw_list[0] |
| 568 | : &isa_parallel_portio_sw_list[0]), |
| 569 | s, "parallel"); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 570 | } |
| 571 | |
Gerd Hoffmann | ed003c8 | 2020-05-15 17:04:12 +0200 | [diff] [blame] | 572 | static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope) |
| 573 | { |
| 574 | ISAParallelState *isa = ISA_PARALLEL(isadev); |
| 575 | Aml *dev; |
| 576 | Aml *crs; |
| 577 | |
| 578 | crs = aml_resource_template(); |
| 579 | aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08)); |
| 580 | aml_append(crs, aml_irq_no_flags(isa->isairq)); |
| 581 | |
| 582 | dev = aml_device("LPT%d", isa->index + 1); |
| 583 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); |
| 584 | aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1))); |
| 585 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); |
| 586 | aml_append(dev, aml_name_decl("_CRS", crs)); |
| 587 | |
| 588 | aml_append(scope, dev); |
| 589 | } |
| 590 | |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 591 | /* Memory mapped interface */ |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 592 | static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 593 | { |
| 594 | ParallelState *s = opaque; |
| 595 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 596 | return parallel_ioport_read_sw(s, addr >> s->it_shift) & |
| 597 | MAKE_64BIT_MASK(0, size * 8); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 598 | } |
| 599 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 600 | static void parallel_mm_writefn(void *opaque, hwaddr addr, |
| 601 | uint64_t value, unsigned size) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 602 | { |
| 603 | ParallelState *s = opaque; |
| 604 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 605 | parallel_ioport_write_sw(s, addr >> s->it_shift, |
| 606 | value & MAKE_64BIT_MASK(0, size * 8)); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 607 | } |
| 608 | |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 609 | static const MemoryRegionOps parallel_mm_ops = { |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 610 | .read = parallel_mm_readfn, |
| 611 | .write = parallel_mm_writefn, |
| 612 | .valid.min_access_size = 1, |
| 613 | .valid.max_access_size = 4, |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 614 | .endianness = DEVICE_NATIVE_ENDIAN, |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 615 | }; |
| 616 | |
| 617 | /* If fd is zero, it means that the parallel device uses the console */ |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 618 | bool parallel_mm_init(MemoryRegion *address_space, |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 619 | hwaddr base, int it_shift, qemu_irq irq, |
Marc-André Lureau | 0ec7b3e | 2016-12-07 16:20:22 +0300 | [diff] [blame] | 620 | Chardev *chr) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 621 | { |
| 622 | ParallelState *s; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 623 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 624 | s = g_malloc0(sizeof(ParallelState)); |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 625 | s->irq = irq; |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 626 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 627 | s->it_shift = it_shift; |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 628 | qemu_register_reset(parallel_reset, s); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 629 | |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 630 | memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 631 | "parallel", 8 << it_shift); |
| 632 | memory_region_add_subregion(address_space, base, &s->iomem); |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 633 | return true; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 634 | } |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 635 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 636 | static Property parallel_isa_properties[] = { |
| 637 | DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), |
Paolo Bonzini | c7bcc85 | 2014-02-08 11:01:53 +0100 | [diff] [blame] | 638 | DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 639 | DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
| 640 | DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), |
| 641 | DEFINE_PROP_END_OF_LIST(), |
| 642 | }; |
| 643 | |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 644 | static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
| 645 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 646 | DeviceClass *dc = DEVICE_CLASS(klass); |
Gerd Hoffmann | ed003c8 | 2020-05-15 17:04:12 +0200 | [diff] [blame] | 647 | ISADeviceClass *isa = ISA_DEVICE_CLASS(klass); |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 648 | |
| 649 | dc->realize = parallel_isa_realizefn; |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 650 | dc->vmsd = &vmstate_parallel_isa; |
Gerd Hoffmann | ed003c8 | 2020-05-15 17:04:12 +0200 | [diff] [blame] | 651 | isa->build_aml = parallel_isa_build_aml; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 652 | device_class_set_props(dc, parallel_isa_properties); |
Marcel Apfelbaum | 125ee0e | 2013-07-29 17:17:45 +0300 | [diff] [blame] | 653 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 654 | } |
| 655 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 656 | static const TypeInfo parallel_isa_info = { |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 657 | .name = TYPE_ISA_PARALLEL, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 658 | .parent = TYPE_ISA_DEVICE, |
| 659 | .instance_size = sizeof(ISAParallelState), |
| 660 | .class_init = parallel_isa_class_initfn, |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 661 | }; |
| 662 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 663 | static void parallel_register_types(void) |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 664 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 665 | type_register_static(¶llel_isa_info); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 666 | } |
| 667 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 668 | type_init(parallel_register_types) |