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bellard80cabfa2004-03-14 12:20:30 +00001/*
2 * QEMU 8253/8254 interval timer emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard80cabfa2004-03-14 12:20:30 +00004 * Copyright (c) 2003-2004 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard80cabfa2004-03-14 12:20:30 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020024
Peter Maydellb6a0aa02016-01-26 18:17:03 +000025#include "qemu/osdep.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020026#include "hw/irq.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020027#include "qemu/module.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010028#include "qemu/timer.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010029#include "hw/timer/i8254.h"
30#include "hw/timer/i8254_internal.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040031#include "qom/object.h"
bellard80cabfa2004-03-14 12:20:30 +000032
bellardb0a21b52004-03-31 18:58:38 +000033//#define DEBUG_PIT
34
bellardec844b92004-05-03 23:18:25 +000035#define RW_STATE_LSB 1
36#define RW_STATE_MSB 2
37#define RW_STATE_WORD0 3
38#define RW_STATE_WORD1 4
bellard80cabfa2004-03-14 12:20:30 +000039
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040040typedef struct PITClass PITClass;
Eduardo Habkost8110fa12020-08-31 17:07:33 -040041DECLARE_CLASS_CHECKERS(PITClass, PIT,
42 TYPE_I8254)
Andreas Färbera15d0912012-11-25 18:47:58 +010043
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040044struct PITClass {
Andreas Färbera15d0912012-11-25 18:47:58 +010045 PITCommonClass parent_class;
46
47 DeviceRealize parent_realize;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040048};
Andreas Färbera15d0912012-11-25 18:47:58 +010049
bellardb0a21b52004-03-31 18:58:38 +000050static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
51
bellard80cabfa2004-03-14 12:20:30 +000052static int pit_get_count(PITChannelState *s)
53{
54 uint64_t d;
55 int counter;
56
Alex Blighbc72ad62013-08-21 16:03:08 +010057 d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ,
Rutuja Shah73bcb242016-03-21 21:32:30 +053058 NANOSECONDS_PER_SECOND);
bellard80cabfa2004-03-14 12:20:30 +000059 switch(s->mode) {
60 case 0:
61 case 1:
62 case 4:
63 case 5:
64 counter = (s->count - d) & 0xffff;
65 break;
66 case 3:
67 /* XXX: may be incorrect for odd counts */
68 counter = s->count - ((2 * d) % s->count);
69 break;
70 default:
71 counter = s->count - (d % s->count);
72 break;
73 }
74 return counter;
75}
76
bellard80cabfa2004-03-14 12:20:30 +000077/* val must be 0 or 1 */
Jan Kiszkad11e8592012-03-02 20:28:46 +010078static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
79 int val)
bellard80cabfa2004-03-14 12:20:30 +000080{
Jan Kiszkad11e8592012-03-02 20:28:46 +010081 switch (sc->mode) {
bellard80cabfa2004-03-14 12:20:30 +000082 default:
83 case 0:
84 case 4:
85 /* XXX: just disable/enable counting */
86 break;
87 case 1:
88 case 5:
Jan Kiszkad11e8592012-03-02 20:28:46 +010089 if (sc->gate < val) {
bellard80cabfa2004-03-14 12:20:30 +000090 /* restart counting on rising edge */
Alex Blighbc72ad62013-08-21 16:03:08 +010091 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Jan Kiszkad11e8592012-03-02 20:28:46 +010092 pit_irq_timer_update(sc, sc->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +000093 }
94 break;
95 case 2:
96 case 3:
Jan Kiszkad11e8592012-03-02 20:28:46 +010097 if (sc->gate < val) {
bellard80cabfa2004-03-14 12:20:30 +000098 /* restart counting on rising edge */
Alex Blighbc72ad62013-08-21 16:03:08 +010099 sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100100 pit_irq_timer_update(sc, sc->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +0000101 }
102 /* XXX: disable/enable counting */
103 break;
104 }
Jan Kiszkad11e8592012-03-02 20:28:46 +0100105 sc->gate = val;
bellardfd06c372006-04-24 21:58:30 +0000106}
107
bellard80cabfa2004-03-14 12:20:30 +0000108static inline void pit_load_count(PITChannelState *s, int val)
109{
110 if (val == 0)
111 val = 0x10000;
Alex Blighbc72ad62013-08-21 16:03:08 +0100112 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
bellard80cabfa2004-03-14 12:20:30 +0000113 s->count = val;
bellardb0a21b52004-03-31 18:58:38 +0000114 pit_irq_timer_update(s, s->count_load_time);
bellard80cabfa2004-03-14 12:20:30 +0000115}
116
bellardec844b92004-05-03 23:18:25 +0000117/* if already latched, do not latch again */
118static void pit_latch_count(PITChannelState *s)
119{
120 if (!s->count_latched) {
121 s->latched_count = pit_get_count(s);
122 s->count_latched = s->rw_mode;
123 }
124}
125
Alexander Graf0505bcd2012-10-08 13:12:31 +0200126static void pit_ioport_write(void *opaque, hwaddr addr,
127 uint64_t val, unsigned size)
bellard80cabfa2004-03-14 12:20:30 +0000128{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100129 PITCommonState *pit = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000130 int channel, access;
131 PITChannelState *s;
132
133 addr &= 3;
134 if (addr == 3) {
135 channel = val >> 6;
bellardec844b92004-05-03 23:18:25 +0000136 if (channel == 3) {
137 /* read back command */
138 for(channel = 0; channel < 3; channel++) {
139 s = &pit->channels[channel];
140 if (val & (2 << channel)) {
141 if (!(val & 0x20)) {
142 pit_latch_count(s);
143 }
144 if (!(val & 0x10) && !s->status_latched) {
145 /* status latch */
146 /* XXX: add BCD and null count */
Jan Kiszka4aa5d282012-02-01 20:31:43 +0100147 s->status =
148 (pit_get_out(s,
Alex Blighbc72ad62013-08-21 16:03:08 +0100149 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) |
bellardec844b92004-05-03 23:18:25 +0000150 (s->rw_mode << 4) |
151 (s->mode << 1) |
152 s->bcd;
153 s->status_latched = 1;
154 }
155 }
156 }
157 } else {
158 s = &pit->channels[channel];
159 access = (val >> 4) & 3;
160 if (access == 0) {
161 pit_latch_count(s);
162 } else {
163 s->rw_mode = access;
164 s->read_state = access;
165 s->write_state = access;
166
167 s->mode = (val >> 1) & 7;
168 s->bcd = val & 1;
169 /* XXX: update irq timer ? */
170 }
bellard80cabfa2004-03-14 12:20:30 +0000171 }
172 } else {
bellardec844b92004-05-03 23:18:25 +0000173 s = &pit->channels[addr];
174 switch(s->write_state) {
175 default:
bellard80cabfa2004-03-14 12:20:30 +0000176 case RW_STATE_LSB:
177 pit_load_count(s, val);
178 break;
179 case RW_STATE_MSB:
180 pit_load_count(s, val << 8);
181 break;
182 case RW_STATE_WORD0:
bellardec844b92004-05-03 23:18:25 +0000183 s->write_latch = val;
184 s->write_state = RW_STATE_WORD1;
185 break;
bellard80cabfa2004-03-14 12:20:30 +0000186 case RW_STATE_WORD1:
bellardec844b92004-05-03 23:18:25 +0000187 pit_load_count(s, s->write_latch | (val << 8));
188 s->write_state = RW_STATE_WORD0;
bellard80cabfa2004-03-14 12:20:30 +0000189 break;
190 }
191 }
192}
193
Alexander Graf0505bcd2012-10-08 13:12:31 +0200194static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
195 unsigned size)
bellard80cabfa2004-03-14 12:20:30 +0000196{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100197 PITCommonState *pit = opaque;
bellard80cabfa2004-03-14 12:20:30 +0000198 int ret, count;
199 PITChannelState *s;
ths3b46e622007-09-17 08:09:54 +0000200
bellard80cabfa2004-03-14 12:20:30 +0000201 addr &= 3;
Petr Matousekd4862a82015-06-17 12:46:11 +0200202
203 if (addr == 3) {
204 /* Mode/Command register is write only, read is ignored */
205 return 0;
206 }
207
bellardec844b92004-05-03 23:18:25 +0000208 s = &pit->channels[addr];
209 if (s->status_latched) {
210 s->status_latched = 0;
211 ret = s->status;
212 } else if (s->count_latched) {
213 switch(s->count_latched) {
214 default:
215 case RW_STATE_LSB:
bellard80cabfa2004-03-14 12:20:30 +0000216 ret = s->latched_count & 0xff;
bellardec844b92004-05-03 23:18:25 +0000217 s->count_latched = 0;
218 break;
219 case RW_STATE_MSB:
220 ret = s->latched_count >> 8;
221 s->count_latched = 0;
222 break;
223 case RW_STATE_WORD0:
224 ret = s->latched_count & 0xff;
225 s->count_latched = RW_STATE_MSB;
226 break;
227 }
228 } else {
229 switch(s->read_state) {
230 default:
231 case RW_STATE_LSB:
232 count = pit_get_count(s);
233 ret = count & 0xff;
234 break;
235 case RW_STATE_MSB:
236 count = pit_get_count(s);
237 ret = (count >> 8) & 0xff;
238 break;
239 case RW_STATE_WORD0:
240 count = pit_get_count(s);
241 ret = count & 0xff;
242 s->read_state = RW_STATE_WORD1;
243 break;
244 case RW_STATE_WORD1:
245 count = pit_get_count(s);
246 ret = (count >> 8) & 0xff;
247 s->read_state = RW_STATE_WORD0;
248 break;
249 }
bellard80cabfa2004-03-14 12:20:30 +0000250 }
251 return ret;
252}
253
bellardb0a21b52004-03-31 18:58:38 +0000254static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
255{
256 int64_t expire_time;
257 int irq_level;
258
Jan Kiszkace967e22012-02-01 20:31:41 +0100259 if (!s->irq_timer || s->irq_disabled) {
bellardb0a21b52004-03-31 18:58:38 +0000260 return;
Jan Kiszkace967e22012-02-01 20:31:41 +0100261 }
bellardb0a21b52004-03-31 18:58:38 +0000262 expire_time = pit_get_next_transition_time(s, current_time);
Jan Kiszka4aa5d282012-02-01 20:31:43 +0100263 irq_level = pit_get_out(s, current_time);
pbrookd537cf62007-04-07 18:14:41 +0000264 qemu_set_irq(s->irq, irq_level);
bellardb0a21b52004-03-31 18:58:38 +0000265#ifdef DEBUG_PIT
266 printf("irq_level=%d next_delay=%f\n",
ths5fafdf22007-09-16 21:08:06 +0000267 irq_level,
Rutuja Shah73bcb242016-03-21 21:32:30 +0530268 (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND);
bellardb0a21b52004-03-31 18:58:38 +0000269#endif
270 s->next_transition_time = expire_time;
271 if (expire_time != -1)
Alex Blighbc72ad62013-08-21 16:03:08 +0100272 timer_mod(s->irq_timer, expire_time);
bellardb0a21b52004-03-31 18:58:38 +0000273 else
Alex Blighbc72ad62013-08-21 16:03:08 +0100274 timer_del(s->irq_timer);
bellardb0a21b52004-03-31 18:58:38 +0000275}
276
277static void pit_irq_timer(void *opaque)
278{
279 PITChannelState *s = opaque;
280
281 pit_irq_timer_update(s, s->next_transition_time);
282}
283
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000284static void pit_reset(DeviceState *dev)
bellard80cabfa2004-03-14 12:20:30 +0000285{
Andreas Färber3afe7e12012-11-25 18:05:53 +0100286 PITCommonState *pit = PIT_COMMON(dev);
bellard80cabfa2004-03-14 12:20:30 +0000287 PITChannelState *s;
bellard80cabfa2004-03-14 12:20:30 +0000288
Jan Kiszkad11e8592012-03-02 20:28:46 +0100289 pit_reset_common(pit);
290
291 s = &pit->channels[0];
292 if (!s->irq_disabled) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100293 timer_mod(s->irq_timer, s->next_transition_time);
bellard80cabfa2004-03-14 12:20:30 +0000294 }
bellardd7d02e32004-06-20 12:58:36 +0000295}
296
Jan Kiszkace967e22012-02-01 20:31:41 +0100297/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
298 * reenable it when legacy mode is left again. */
299static void pit_irq_control(void *opaque, int n, int enable)
aliguori16b29ae2008-12-17 23:28:44 +0000300{
Jan Kiszkad11e8592012-03-02 20:28:46 +0100301 PITCommonState *pit = opaque;
Jan Kiszkace967e22012-02-01 20:31:41 +0100302 PITChannelState *s = &pit->channels[0];
303
304 if (enable) {
305 s->irq_disabled = 0;
Alex Blighbc72ad62013-08-21 16:03:08 +0100306 pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
Jan Kiszkace967e22012-02-01 20:31:41 +0100307 } else {
308 s->irq_disabled = 1;
Alex Blighbc72ad62013-08-21 16:03:08 +0100309 timer_del(s->irq_timer);
Jan Kiszkace967e22012-02-01 20:31:41 +0100310 }
aliguori16b29ae2008-12-17 23:28:44 +0000311}
312
Richard Henderson60ea6aa2011-08-10 15:28:15 -0700313static const MemoryRegionOps pit_ioport_ops = {
Alexander Graf0505bcd2012-10-08 13:12:31 +0200314 .read = pit_ioport_read,
315 .write = pit_ioport_write,
316 .impl = {
317 .min_access_size = 1,
318 .max_access_size = 1,
319 },
320 .endianness = DEVICE_LITTLE_ENDIAN,
Richard Henderson60ea6aa2011-08-10 15:28:15 -0700321};
322
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100323static void pit_post_load(PITCommonState *s)
324{
325 PITChannelState *sc = &s->channels[0];
326
327 if (sc->next_transition_time != -1) {
Alex Blighbc72ad62013-08-21 16:03:08 +0100328 timer_mod(sc->irq_timer, sc->next_transition_time);
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100329 } else {
Alex Blighbc72ad62013-08-21 16:03:08 +0100330 timer_del(sc->irq_timer);
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100331 }
332}
333
Markus Armbrustera7737e42014-04-25 12:44:21 +0200334static void pit_realizefn(DeviceState *dev, Error **errp)
bellardd7d02e32004-06-20 12:58:36 +0000335{
Andreas Färbera15d0912012-11-25 18:47:58 +0100336 PITCommonState *pit = PIT_COMMON(dev);
337 PITClass *pc = PIT_GET_CLASS(dev);
bellardd7d02e32004-06-20 12:58:36 +0000338 PITChannelState *s;
339
340 s = &pit->channels[0];
341 /* the timer 0 is connected to an IRQ */
Alex Blighbc72ad62013-08-21 16:03:08 +0100342 s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s);
Andreas Färbera15d0912012-11-25 18:47:58 +0100343 qdev_init_gpio_out(dev, &s->irq, 1);
bellard80cabfa2004-03-14 12:20:30 +0000344
Paolo Bonzini853dca12013-06-06 21:25:08 -0400345 memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops,
346 pit, "pit", 4);
bellardd7d02e32004-06-20 12:58:36 +0000347
Andreas Färbera15d0912012-11-25 18:47:58 +0100348 qdev_init_gpio_in(dev, pit_irq_control, 1);
Jan Kiszkaca22a3a2011-03-06 16:09:49 +0100349
Markus Armbrustera7737e42014-04-25 12:44:21 +0200350 pc->parent_realize(dev, errp);
bellard80cabfa2004-03-14 12:20:30 +0000351}
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000352
Anthony Liguori39bffca2011-12-07 21:34:16 -0600353static Property pit_properties[] = {
Paolo Bonzinic7bcc852014-02-08 11:01:53 +0100354 DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600355 DEFINE_PROP_END_OF_LIST(),
356};
357
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600358static void pit_class_initfn(ObjectClass *klass, void *data)
359{
Andreas Färbera15d0912012-11-25 18:47:58 +0100360 PITClass *pc = PIT_CLASS(klass);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100361 PITCommonClass *k = PIT_COMMON_CLASS(klass);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600362 DeviceClass *dc = DEVICE_CLASS(klass);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100363
Philippe Mathieu-Daudébf853882018-01-13 23:04:12 -0300364 device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize);
Jan Kiszkad11e8592012-03-02 20:28:46 +0100365 k->set_channel_gate = pit_set_channel_gate;
366 k->get_channel_info = pit_get_channel_info_common;
Jan Kiszka3fbc1c02012-03-02 20:28:47 +0100367 k->post_load = pit_post_load;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600368 dc->reset = pit_reset;
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400369 device_class_set_props(dc, pit_properties);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600370}
371
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100372static const TypeInfo pit_info = {
Andreas Färber3afe7e12012-11-25 18:05:53 +0100373 .name = TYPE_I8254,
Jan Kiszkad11e8592012-03-02 20:28:46 +0100374 .parent = TYPE_PIT_COMMON,
375 .instance_size = sizeof(PITCommonState),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600376 .class_init = pit_class_initfn,
Andreas Färbera15d0912012-11-25 18:47:58 +0100377 .class_size = sizeof(PITClass),
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000378};
379
Andreas Färber83f7d432012-02-09 15:20:55 +0100380static void pit_register_types(void)
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000381{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600382 type_register_static(&pit_info);
Blue Swirl64d7e9a2011-02-13 19:54:40 +0000383}
Andreas Färber83f7d432012-02-09 15:20:55 +0100384
385type_init(pit_register_types)