bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU 8253/8254 interval timer emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 24 | |
Peter Maydell | b6a0aa0 | 2016-01-26 18:17:03 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 26 | #include "hw/irq.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 27 | #include "qemu/module.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 28 | #include "qemu/timer.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 29 | #include "hw/timer/i8254.h" |
| 30 | #include "hw/timer/i8254_internal.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 31 | #include "qom/object.h" |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 32 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 33 | //#define DEBUG_PIT |
| 34 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 35 | #define RW_STATE_LSB 1 |
| 36 | #define RW_STATE_MSB 2 |
| 37 | #define RW_STATE_WORD0 3 |
| 38 | #define RW_STATE_WORD1 4 |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 39 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 40 | typedef struct PITClass PITClass; |
Eduardo Habkost | 8110fa1 | 2020-08-31 17:07:33 -0400 | [diff] [blame] | 41 | DECLARE_CLASS_CHECKERS(PITClass, PIT, |
| 42 | TYPE_I8254) |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 43 | |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 44 | struct PITClass { |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 45 | PITCommonClass parent_class; |
| 46 | |
| 47 | DeviceRealize parent_realize; |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 48 | }; |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 49 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 50 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
| 51 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 52 | static int pit_get_count(PITChannelState *s) |
| 53 | { |
| 54 | uint64_t d; |
| 55 | int counter; |
| 56 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 57 | d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 58 | NANOSECONDS_PER_SECOND); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 59 | switch(s->mode) { |
| 60 | case 0: |
| 61 | case 1: |
| 62 | case 4: |
| 63 | case 5: |
| 64 | counter = (s->count - d) & 0xffff; |
| 65 | break; |
| 66 | case 3: |
| 67 | /* XXX: may be incorrect for odd counts */ |
| 68 | counter = s->count - ((2 * d) % s->count); |
| 69 | break; |
| 70 | default: |
| 71 | counter = s->count - (d % s->count); |
| 72 | break; |
| 73 | } |
| 74 | return counter; |
| 75 | } |
| 76 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 77 | /* val must be 0 or 1 */ |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 78 | static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc, |
| 79 | int val) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 80 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 81 | switch (sc->mode) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 82 | default: |
| 83 | case 0: |
| 84 | case 4: |
| 85 | /* XXX: just disable/enable counting */ |
| 86 | break; |
| 87 | case 1: |
| 88 | case 5: |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 89 | if (sc->gate < val) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 90 | /* restart counting on rising edge */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 91 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 92 | pit_irq_timer_update(sc, sc->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 93 | } |
| 94 | break; |
| 95 | case 2: |
| 96 | case 3: |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 97 | if (sc->gate < val) { |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 98 | /* restart counting on rising edge */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 99 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 100 | pit_irq_timer_update(sc, sc->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 101 | } |
| 102 | /* XXX: disable/enable counting */ |
| 103 | break; |
| 104 | } |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 105 | sc->gate = val; |
bellard | fd06c37 | 2006-04-24 21:58:30 +0000 | [diff] [blame] | 106 | } |
| 107 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 108 | static inline void pit_load_count(PITChannelState *s, int val) |
| 109 | { |
| 110 | if (val == 0) |
| 111 | val = 0x10000; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 112 | s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 113 | s->count = val; |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 114 | pit_irq_timer_update(s, s->count_load_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 115 | } |
| 116 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 117 | /* if already latched, do not latch again */ |
| 118 | static void pit_latch_count(PITChannelState *s) |
| 119 | { |
| 120 | if (!s->count_latched) { |
| 121 | s->latched_count = pit_get_count(s); |
| 122 | s->count_latched = s->rw_mode; |
| 123 | } |
| 124 | } |
| 125 | |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 126 | static void pit_ioport_write(void *opaque, hwaddr addr, |
| 127 | uint64_t val, unsigned size) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 128 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 129 | PITCommonState *pit = opaque; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 130 | int channel, access; |
| 131 | PITChannelState *s; |
| 132 | |
| 133 | addr &= 3; |
| 134 | if (addr == 3) { |
| 135 | channel = val >> 6; |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 136 | if (channel == 3) { |
| 137 | /* read back command */ |
| 138 | for(channel = 0; channel < 3; channel++) { |
| 139 | s = &pit->channels[channel]; |
| 140 | if (val & (2 << channel)) { |
| 141 | if (!(val & 0x20)) { |
| 142 | pit_latch_count(s); |
| 143 | } |
| 144 | if (!(val & 0x10) && !s->status_latched) { |
| 145 | /* status latch */ |
| 146 | /* XXX: add BCD and null count */ |
Jan Kiszka | 4aa5d28 | 2012-02-01 20:31:43 +0100 | [diff] [blame] | 147 | s->status = |
| 148 | (pit_get_out(s, |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 149 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 150 | (s->rw_mode << 4) | |
| 151 | (s->mode << 1) | |
| 152 | s->bcd; |
| 153 | s->status_latched = 1; |
| 154 | } |
| 155 | } |
| 156 | } |
| 157 | } else { |
| 158 | s = &pit->channels[channel]; |
| 159 | access = (val >> 4) & 3; |
| 160 | if (access == 0) { |
| 161 | pit_latch_count(s); |
| 162 | } else { |
| 163 | s->rw_mode = access; |
| 164 | s->read_state = access; |
| 165 | s->write_state = access; |
| 166 | |
| 167 | s->mode = (val >> 1) & 7; |
| 168 | s->bcd = val & 1; |
| 169 | /* XXX: update irq timer ? */ |
| 170 | } |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 171 | } |
| 172 | } else { |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 173 | s = &pit->channels[addr]; |
| 174 | switch(s->write_state) { |
| 175 | default: |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 176 | case RW_STATE_LSB: |
| 177 | pit_load_count(s, val); |
| 178 | break; |
| 179 | case RW_STATE_MSB: |
| 180 | pit_load_count(s, val << 8); |
| 181 | break; |
| 182 | case RW_STATE_WORD0: |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 183 | s->write_latch = val; |
| 184 | s->write_state = RW_STATE_WORD1; |
| 185 | break; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 186 | case RW_STATE_WORD1: |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 187 | pit_load_count(s, s->write_latch | (val << 8)); |
| 188 | s->write_state = RW_STATE_WORD0; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 189 | break; |
| 190 | } |
| 191 | } |
| 192 | } |
| 193 | |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 194 | static uint64_t pit_ioport_read(void *opaque, hwaddr addr, |
| 195 | unsigned size) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 196 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 197 | PITCommonState *pit = opaque; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 198 | int ret, count; |
| 199 | PITChannelState *s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 200 | |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 201 | addr &= 3; |
Petr Matousek | d4862a8 | 2015-06-17 12:46:11 +0200 | [diff] [blame] | 202 | |
| 203 | if (addr == 3) { |
| 204 | /* Mode/Command register is write only, read is ignored */ |
| 205 | return 0; |
| 206 | } |
| 207 | |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 208 | s = &pit->channels[addr]; |
| 209 | if (s->status_latched) { |
| 210 | s->status_latched = 0; |
| 211 | ret = s->status; |
| 212 | } else if (s->count_latched) { |
| 213 | switch(s->count_latched) { |
| 214 | default: |
| 215 | case RW_STATE_LSB: |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 216 | ret = s->latched_count & 0xff; |
bellard | ec844b9 | 2004-05-03 23:18:25 +0000 | [diff] [blame] | 217 | s->count_latched = 0; |
| 218 | break; |
| 219 | case RW_STATE_MSB: |
| 220 | ret = s->latched_count >> 8; |
| 221 | s->count_latched = 0; |
| 222 | break; |
| 223 | case RW_STATE_WORD0: |
| 224 | ret = s->latched_count & 0xff; |
| 225 | s->count_latched = RW_STATE_MSB; |
| 226 | break; |
| 227 | } |
| 228 | } else { |
| 229 | switch(s->read_state) { |
| 230 | default: |
| 231 | case RW_STATE_LSB: |
| 232 | count = pit_get_count(s); |
| 233 | ret = count & 0xff; |
| 234 | break; |
| 235 | case RW_STATE_MSB: |
| 236 | count = pit_get_count(s); |
| 237 | ret = (count >> 8) & 0xff; |
| 238 | break; |
| 239 | case RW_STATE_WORD0: |
| 240 | count = pit_get_count(s); |
| 241 | ret = count & 0xff; |
| 242 | s->read_state = RW_STATE_WORD1; |
| 243 | break; |
| 244 | case RW_STATE_WORD1: |
| 245 | count = pit_get_count(s); |
| 246 | ret = (count >> 8) & 0xff; |
| 247 | s->read_state = RW_STATE_WORD0; |
| 248 | break; |
| 249 | } |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 250 | } |
| 251 | return ret; |
| 252 | } |
| 253 | |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 254 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
| 255 | { |
| 256 | int64_t expire_time; |
| 257 | int irq_level; |
| 258 | |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 259 | if (!s->irq_timer || s->irq_disabled) { |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 260 | return; |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 261 | } |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 262 | expire_time = pit_get_next_transition_time(s, current_time); |
Jan Kiszka | 4aa5d28 | 2012-02-01 20:31:43 +0100 | [diff] [blame] | 263 | irq_level = pit_get_out(s, current_time); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 264 | qemu_set_irq(s->irq, irq_level); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 265 | #ifdef DEBUG_PIT |
| 266 | printf("irq_level=%d next_delay=%f\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 267 | irq_level, |
Rutuja Shah | 73bcb24 | 2016-03-21 21:32:30 +0530 | [diff] [blame] | 268 | (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 269 | #endif |
| 270 | s->next_transition_time = expire_time; |
| 271 | if (expire_time != -1) |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 272 | timer_mod(s->irq_timer, expire_time); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 273 | else |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 274 | timer_del(s->irq_timer); |
bellard | b0a21b5 | 2004-03-31 18:58:38 +0000 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | static void pit_irq_timer(void *opaque) |
| 278 | { |
| 279 | PITChannelState *s = opaque; |
| 280 | |
| 281 | pit_irq_timer_update(s, s->next_transition_time); |
| 282 | } |
| 283 | |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 284 | static void pit_reset(DeviceState *dev) |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 285 | { |
Andreas Färber | 3afe7e1 | 2012-11-25 18:05:53 +0100 | [diff] [blame] | 286 | PITCommonState *pit = PIT_COMMON(dev); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 287 | PITChannelState *s; |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 288 | |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 289 | pit_reset_common(pit); |
| 290 | |
| 291 | s = &pit->channels[0]; |
| 292 | if (!s->irq_disabled) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 293 | timer_mod(s->irq_timer, s->next_transition_time); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 294 | } |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 295 | } |
| 296 | |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 297 | /* When HPET is operating in legacy mode, suppress the ignored timer IRQ, |
| 298 | * reenable it when legacy mode is left again. */ |
| 299 | static void pit_irq_control(void *opaque, int n, int enable) |
aliguori | 16b29ae | 2008-12-17 23:28:44 +0000 | [diff] [blame] | 300 | { |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 301 | PITCommonState *pit = opaque; |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 302 | PITChannelState *s = &pit->channels[0]; |
| 303 | |
| 304 | if (enable) { |
| 305 | s->irq_disabled = 0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 306 | pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 307 | } else { |
| 308 | s->irq_disabled = 1; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 309 | timer_del(s->irq_timer); |
Jan Kiszka | ce967e2 | 2012-02-01 20:31:41 +0100 | [diff] [blame] | 310 | } |
aliguori | 16b29ae | 2008-12-17 23:28:44 +0000 | [diff] [blame] | 311 | } |
| 312 | |
Richard Henderson | 60ea6aa | 2011-08-10 15:28:15 -0700 | [diff] [blame] | 313 | static const MemoryRegionOps pit_ioport_ops = { |
Alexander Graf | 0505bcd | 2012-10-08 13:12:31 +0200 | [diff] [blame] | 314 | .read = pit_ioport_read, |
| 315 | .write = pit_ioport_write, |
| 316 | .impl = { |
| 317 | .min_access_size = 1, |
| 318 | .max_access_size = 1, |
| 319 | }, |
| 320 | .endianness = DEVICE_LITTLE_ENDIAN, |
Richard Henderson | 60ea6aa | 2011-08-10 15:28:15 -0700 | [diff] [blame] | 321 | }; |
| 322 | |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 323 | static void pit_post_load(PITCommonState *s) |
| 324 | { |
| 325 | PITChannelState *sc = &s->channels[0]; |
| 326 | |
| 327 | if (sc->next_transition_time != -1) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 328 | timer_mod(sc->irq_timer, sc->next_transition_time); |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 329 | } else { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 330 | timer_del(sc->irq_timer); |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 331 | } |
| 332 | } |
| 333 | |
Markus Armbruster | a7737e4 | 2014-04-25 12:44:21 +0200 | [diff] [blame] | 334 | static void pit_realizefn(DeviceState *dev, Error **errp) |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 335 | { |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 336 | PITCommonState *pit = PIT_COMMON(dev); |
| 337 | PITClass *pc = PIT_GET_CLASS(dev); |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 338 | PITChannelState *s; |
| 339 | |
| 340 | s = &pit->channels[0]; |
| 341 | /* the timer 0 is connected to an IRQ */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 342 | s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 343 | qdev_init_gpio_out(dev, &s->irq, 1); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 344 | |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 345 | memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, |
| 346 | pit, "pit", 4); |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 347 | |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 348 | qdev_init_gpio_in(dev, pit_irq_control, 1); |
Jan Kiszka | ca22a3a | 2011-03-06 16:09:49 +0100 | [diff] [blame] | 349 | |
Markus Armbruster | a7737e4 | 2014-04-25 12:44:21 +0200 | [diff] [blame] | 350 | pc->parent_realize(dev, errp); |
bellard | 80cabfa | 2004-03-14 12:20:30 +0000 | [diff] [blame] | 351 | } |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 352 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 353 | static Property pit_properties[] = { |
Paolo Bonzini | c7bcc85 | 2014-02-08 11:01:53 +0100 | [diff] [blame] | 354 | DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 355 | DEFINE_PROP_END_OF_LIST(), |
| 356 | }; |
| 357 | |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 358 | static void pit_class_initfn(ObjectClass *klass, void *data) |
| 359 | { |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 360 | PITClass *pc = PIT_CLASS(klass); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 361 | PITCommonClass *k = PIT_COMMON_CLASS(klass); |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 362 | DeviceClass *dc = DEVICE_CLASS(klass); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 363 | |
Philippe Mathieu-Daudé | bf85388 | 2018-01-13 23:04:12 -0300 | [diff] [blame] | 364 | device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize); |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 365 | k->set_channel_gate = pit_set_channel_gate; |
| 366 | k->get_channel_info = pit_get_channel_info_common; |
Jan Kiszka | 3fbc1c0 | 2012-03-02 20:28:47 +0100 | [diff] [blame] | 367 | k->post_load = pit_post_load; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 368 | dc->reset = pit_reset; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 369 | device_class_set_props(dc, pit_properties); |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 370 | } |
| 371 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 372 | static const TypeInfo pit_info = { |
Andreas Färber | 3afe7e1 | 2012-11-25 18:05:53 +0100 | [diff] [blame] | 373 | .name = TYPE_I8254, |
Jan Kiszka | d11e859 | 2012-03-02 20:28:46 +0100 | [diff] [blame] | 374 | .parent = TYPE_PIT_COMMON, |
| 375 | .instance_size = sizeof(PITCommonState), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 376 | .class_init = pit_class_initfn, |
Andreas Färber | a15d091 | 2012-11-25 18:47:58 +0100 | [diff] [blame] | 377 | .class_size = sizeof(PITClass), |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 378 | }; |
| 379 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 380 | static void pit_register_types(void) |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 381 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 382 | type_register_static(&pit_info); |
Blue Swirl | 64d7e9a | 2011-02-13 19:54:40 +0000 | [diff] [blame] | 383 | } |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 384 | |
| 385 | type_init(pit_register_types) |