bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU PPC PREP hardware System Emulator |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 24 | #include "hw.h" |
| 25 | #include "nvram.h" |
| 26 | #include "pc.h" |
| 27 | #include "fdc.h" |
| 28 | #include "net.h" |
| 29 | #include "sysemu.h" |
| 30 | #include "isa.h" |
| 31 | #include "pci.h" |
Michael S. Tsirkin | 18e08a5 | 2009-11-11 14:59:56 +0200 | [diff] [blame] | 32 | #include "prep_pci.h" |
| 33 | #include "usb-ohci.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 34 | #include "ppc.h" |
| 35 | #include "boards.h" |
blueswir1 | 3b3fb32 | 2008-10-04 07:20:07 +0000 | [diff] [blame] | 36 | #include "qemu-log.h" |
Gerd Hoffmann | ec82026 | 2009-08-20 15:22:19 +0200 | [diff] [blame] | 37 | #include "ide.h" |
Blue Swirl | ca20cf3 | 2009-09-20 14:58:02 +0000 | [diff] [blame] | 38 | #include "loader.h" |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 39 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 40 | //#define HARD_DEBUG_PPC_IO |
| 41 | //#define DEBUG_PPC_IO |
| 42 | |
j_mayer | fe33cc7 | 2007-10-03 01:06:57 +0000 | [diff] [blame] | 43 | /* SMP is not enabled, for now */ |
| 44 | #define MAX_CPUS 1 |
| 45 | |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 46 | #define MAX_IDE_BUS 2 |
| 47 | |
Paul Brook | bba831e | 2009-05-19 14:52:42 +0100 | [diff] [blame] | 48 | #define BIOS_SIZE (1024 * 1024) |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 49 | #define BIOS_FILENAME "ppc_rom.bin" |
| 50 | #define KERNEL_LOAD_ADDR 0x01000000 |
| 51 | #define INITRD_LOAD_ADDR 0x01800000 |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 52 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 53 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
| 54 | #define DEBUG_PPC_IO |
| 55 | #endif |
| 56 | |
| 57 | #if defined (HARD_DEBUG_PPC_IO) |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 58 | #define PPC_IO_DPRINTF(fmt, ...) \ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 59 | do { \ |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 60 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 61 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 62 | } else { \ |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 63 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 64 | } \ |
| 65 | } while (0) |
| 66 | #elif defined (DEBUG_PPC_IO) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 67 | #define PPC_IO_DPRINTF(fmt, ...) \ |
| 68 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 69 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 70 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 71 | #endif |
| 72 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 73 | /* Constants for devices init */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 74 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
| 75 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
| 76 | static const int ide_irq[2] = { 13, 13 }; |
| 77 | |
| 78 | #define NE2000_NB_MAX 6 |
| 79 | |
| 80 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
| 81 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
| 82 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 83 | //static PITState *pit; |
| 84 | |
| 85 | /* ISA IO ports bridge */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 86 | #define PPC_IO_BASE 0x80000000 |
| 87 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 88 | #if 0 |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 89 | /* Speaker port 0x61 */ |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 90 | static int speaker_data_on; |
| 91 | static int dummy_refresh_clock; |
| 92 | #endif |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 93 | |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 94 | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 95 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 96 | #if 0 |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 97 | speaker_data_on = (val >> 1) & 1; |
| 98 | pit_set_gate(pit, 2, val & 1); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 99 | #endif |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 100 | } |
| 101 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 102 | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 103 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 104 | #if 0 |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 105 | int out; |
| 106 | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); |
| 107 | dummy_refresh_clock ^= 1; |
| 108 | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 109 | (dummy_refresh_clock << 4); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 110 | #endif |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 111 | return 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 112 | } |
| 113 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 114 | /* PCI intack register */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 115 | /* Read-only register (?) */ |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 116 | static void _PPC_intack_write (void *opaque, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 117 | target_phys_addr_t addr, uint32_t value) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 118 | { |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 119 | #if 0 |
| 120 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
| 121 | value); |
| 122 | #endif |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 123 | } |
| 124 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 125 | static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 126 | { |
| 127 | uint32_t retval = 0; |
| 128 | |
aurel32 | 4dd8c13 | 2008-12-05 16:05:41 +0000 | [diff] [blame] | 129 | if ((addr & 0xf) == 0) |
bellard | 3de388f | 2005-07-02 18:11:44 +0000 | [diff] [blame] | 130 | retval = pic_intack_read(isa_pic); |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 131 | #if 0 |
| 132 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
| 133 | retval); |
| 134 | #endif |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 135 | |
| 136 | return retval; |
| 137 | } |
| 138 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 139 | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 140 | { |
| 141 | return _PPC_intack_read(addr); |
| 142 | } |
| 143 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 144 | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 145 | { |
| 146 | #ifdef TARGET_WORDS_BIGENDIAN |
| 147 | return bswap16(_PPC_intack_read(addr)); |
| 148 | #else |
| 149 | return _PPC_intack_read(addr); |
| 150 | #endif |
| 151 | } |
| 152 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 153 | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 154 | { |
| 155 | #ifdef TARGET_WORDS_BIGENDIAN |
| 156 | return bswap32(_PPC_intack_read(addr)); |
| 157 | #else |
| 158 | return _PPC_intack_read(addr); |
| 159 | #endif |
| 160 | } |
| 161 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 162 | static CPUWriteMemoryFunc * const PPC_intack_write[] = { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 163 | &_PPC_intack_write, |
| 164 | &_PPC_intack_write, |
| 165 | &_PPC_intack_write, |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 166 | }; |
| 167 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 168 | static CPUReadMemoryFunc * const PPC_intack_read[] = { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 169 | &PPC_intack_readb, |
| 170 | &PPC_intack_readw, |
| 171 | &PPC_intack_readl, |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 172 | }; |
| 173 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 174 | /* PowerPC control and status registers */ |
| 175 | #if 0 // Not used |
| 176 | static struct { |
| 177 | /* IDs */ |
| 178 | uint32_t veni_devi; |
| 179 | uint32_t revi; |
| 180 | /* Control and status */ |
| 181 | uint32_t gcsr; |
| 182 | uint32_t xcfr; |
| 183 | uint32_t ct32; |
| 184 | uint32_t mcsr; |
| 185 | /* General purpose registers */ |
| 186 | uint32_t gprg[6]; |
| 187 | /* Exceptions */ |
| 188 | uint32_t feen; |
| 189 | uint32_t fest; |
| 190 | uint32_t fema; |
| 191 | uint32_t fecl; |
| 192 | uint32_t eeen; |
| 193 | uint32_t eest; |
| 194 | uint32_t eecl; |
| 195 | uint32_t eeint; |
| 196 | uint32_t eemck0; |
| 197 | uint32_t eemck1; |
| 198 | /* Error diagnostic */ |
| 199 | } XCSR; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 200 | |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 201 | static void PPC_XCSR_writeb (void *opaque, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 202 | target_phys_addr_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 203 | { |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 204 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
| 205 | value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 206 | } |
| 207 | |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 208 | static void PPC_XCSR_writew (void *opaque, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 209 | target_phys_addr_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 210 | { |
| 211 | #ifdef TARGET_WORDS_BIGENDIAN |
| 212 | value = bswap16(value); |
| 213 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 214 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
| 215 | value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 216 | } |
| 217 | |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 218 | static void PPC_XCSR_writel (void *opaque, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 219 | target_phys_addr_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 220 | { |
| 221 | #ifdef TARGET_WORDS_BIGENDIAN |
| 222 | value = bswap32(value); |
| 223 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 224 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
| 225 | value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 228 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 229 | { |
| 230 | uint32_t retval = 0; |
| 231 | |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 232 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
| 233 | retval); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 234 | |
| 235 | return retval; |
| 236 | } |
| 237 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 238 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 239 | { |
| 240 | uint32_t retval = 0; |
| 241 | |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 242 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
| 243 | retval); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 244 | #ifdef TARGET_WORDS_BIGENDIAN |
| 245 | retval = bswap16(retval); |
| 246 | #endif |
| 247 | |
| 248 | return retval; |
| 249 | } |
| 250 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 251 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 252 | { |
| 253 | uint32_t retval = 0; |
| 254 | |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 255 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
| 256 | retval); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 257 | #ifdef TARGET_WORDS_BIGENDIAN |
| 258 | retval = bswap32(retval); |
| 259 | #endif |
| 260 | |
| 261 | return retval; |
| 262 | } |
| 263 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 264 | static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 265 | &PPC_XCSR_writeb, |
| 266 | &PPC_XCSR_writew, |
| 267 | &PPC_XCSR_writel, |
| 268 | }; |
| 269 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 270 | static CPUReadMemoryFunc * const PPC_XCSR_read[] = { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 271 | &PPC_XCSR_readb, |
| 272 | &PPC_XCSR_readw, |
| 273 | &PPC_XCSR_readl, |
| 274 | }; |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 275 | #endif |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 276 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 277 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 278 | typedef struct sysctrl_t { |
j_mayer | c4781a5 | 2007-10-29 10:21:12 +0000 | [diff] [blame] | 279 | qemu_irq reset_irq; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 280 | M48t59State *nvram; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 281 | uint8_t state; |
| 282 | uint8_t syscontrol; |
| 283 | uint8_t fake_io[2]; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 284 | int contiguous_map; |
bellard | fb3444b | 2005-07-03 13:57:11 +0000 | [diff] [blame] | 285 | int endian; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 286 | } sysctrl_t; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 287 | |
| 288 | enum { |
| 289 | STATE_HARDFILE = 0x01, |
| 290 | }; |
| 291 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 292 | static sysctrl_t *sysctrl; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 293 | |
| 294 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
| 295 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 296 | sysctrl_t *sysctrl = opaque; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 297 | |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 298 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
| 299 | val); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 300 | sysctrl->fake_io[addr - 0x0398] = val; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
| 304 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 305 | sysctrl_t *sysctrl = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 306 | |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 307 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 308 | sysctrl->fake_io[addr - 0x0398]); |
| 309 | return sysctrl->fake_io[addr - 0x0398]; |
| 310 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 311 | |
| 312 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 313 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 314 | sysctrl_t *sysctrl = opaque; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 315 | |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 316 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
| 317 | addr - PPC_IO_BASE, val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 318 | switch (addr) { |
| 319 | case 0x0092: |
| 320 | /* Special port 92 */ |
| 321 | /* Check soft reset asked */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 322 | if (val & 0x01) { |
j_mayer | c4781a5 | 2007-10-29 10:21:12 +0000 | [diff] [blame] | 323 | qemu_irq_raise(sysctrl->reset_irq); |
| 324 | } else { |
| 325 | qemu_irq_lower(sysctrl->reset_irq); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 326 | } |
| 327 | /* Check LE mode */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 328 | if (val & 0x02) { |
bellard | fb3444b | 2005-07-03 13:57:11 +0000 | [diff] [blame] | 329 | sysctrl->endian = 1; |
| 330 | } else { |
| 331 | sysctrl->endian = 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 332 | } |
| 333 | break; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 334 | case 0x0800: |
| 335 | /* Motorola CPU configuration register : read-only */ |
| 336 | break; |
| 337 | case 0x0802: |
| 338 | /* Motorola base module feature register : read-only */ |
| 339 | break; |
| 340 | case 0x0803: |
| 341 | /* Motorola base module status register : read-only */ |
| 342 | break; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 343 | case 0x0808: |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 344 | /* Hardfile light register */ |
| 345 | if (val & 1) |
| 346 | sysctrl->state |= STATE_HARDFILE; |
| 347 | else |
| 348 | sysctrl->state &= ~STATE_HARDFILE; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 349 | break; |
| 350 | case 0x0810: |
| 351 | /* Password protect 1 register */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 352 | if (sysctrl->nvram != NULL) |
| 353 | m48t59_toggle_lock(sysctrl->nvram, 1); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 354 | break; |
| 355 | case 0x0812: |
| 356 | /* Password protect 2 register */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 357 | if (sysctrl->nvram != NULL) |
| 358 | m48t59_toggle_lock(sysctrl->nvram, 2); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 359 | break; |
| 360 | case 0x0814: |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 361 | /* L2 invalidate register */ |
bellard | c68ea70 | 2005-11-21 23:33:12 +0000 | [diff] [blame] | 362 | // tlb_flush(first_cpu, 1); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 363 | break; |
| 364 | case 0x081C: |
| 365 | /* system control register */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 366 | sysctrl->syscontrol = val & 0x0F; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 367 | break; |
| 368 | case 0x0850: |
| 369 | /* I/O map type register */ |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 370 | sysctrl->contiguous_map = val & 0x01; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 371 | break; |
| 372 | default: |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 373 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
| 374 | " => %02" PRIx32"\n", addr, val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 375 | break; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
| 380 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 381 | sysctrl_t *sysctrl = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 382 | uint32_t retval = 0xFF; |
| 383 | |
| 384 | switch (addr) { |
| 385 | case 0x0092: |
| 386 | /* Special port 92 */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 387 | retval = 0x00; |
| 388 | break; |
| 389 | case 0x0800: |
| 390 | /* Motorola CPU configuration register */ |
| 391 | retval = 0xEF; /* MPC750 */ |
| 392 | break; |
| 393 | case 0x0802: |
| 394 | /* Motorola Base module feature register */ |
| 395 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
| 396 | break; |
| 397 | case 0x0803: |
| 398 | /* Motorola base module status register */ |
| 399 | retval = 0xE0; /* Standard MPC750 */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 400 | break; |
| 401 | case 0x080C: |
| 402 | /* Equipment present register: |
| 403 | * no L2 cache |
| 404 | * no upgrade processor |
| 405 | * no cards in PCI slots |
| 406 | * SCSI fuse is bad |
| 407 | */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 408 | retval = 0x3C; |
| 409 | break; |
| 410 | case 0x0810: |
| 411 | /* Motorola base module extended feature register */ |
| 412 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 413 | break; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 414 | case 0x0814: |
| 415 | /* L2 invalidate: don't care */ |
| 416 | break; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 417 | case 0x0818: |
| 418 | /* Keylock */ |
| 419 | retval = 0x00; |
| 420 | break; |
| 421 | case 0x081C: |
| 422 | /* system control register |
| 423 | * 7 - 6 / 1 - 0: L2 cache enable |
| 424 | */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 425 | retval = sysctrl->syscontrol; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 426 | break; |
| 427 | case 0x0823: |
| 428 | /* */ |
| 429 | retval = 0x03; /* no L2 cache */ |
| 430 | break; |
| 431 | case 0x0850: |
| 432 | /* I/O map type register */ |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 433 | retval = sysctrl->contiguous_map; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 434 | break; |
| 435 | default: |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 436 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 437 | break; |
| 438 | } |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 439 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
| 440 | addr - PPC_IO_BASE, retval); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 441 | |
| 442 | return retval; |
| 443 | } |
| 444 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 445 | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
| 446 | target_phys_addr_t addr) |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 447 | { |
| 448 | if (sysctrl->contiguous_map == 0) { |
| 449 | /* 64 KB contiguous space for IOs */ |
| 450 | addr &= 0xFFFF; |
| 451 | } else { |
| 452 | /* 8 MB non-contiguous space for IOs */ |
| 453 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
| 454 | } |
| 455 | |
| 456 | return addr; |
| 457 | } |
| 458 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 459 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 460 | uint32_t value) |
| 461 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 462 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 463 | |
| 464 | addr = prep_IO_address(sysctrl, addr); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 465 | cpu_outb(addr, value); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 466 | } |
| 467 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 468 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 469 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 470 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 471 | uint32_t ret; |
| 472 | |
| 473 | addr = prep_IO_address(sysctrl, addr); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 474 | ret = cpu_inb(addr); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 475 | |
| 476 | return ret; |
| 477 | } |
| 478 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 479 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 480 | uint32_t value) |
| 481 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 482 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 483 | |
| 484 | addr = prep_IO_address(sysctrl, addr); |
| 485 | #ifdef TARGET_WORDS_BIGENDIAN |
| 486 | value = bswap16(value); |
| 487 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 488 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 489 | cpu_outw(addr, value); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 490 | } |
| 491 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 492 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 493 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 494 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 495 | uint32_t ret; |
| 496 | |
| 497 | addr = prep_IO_address(sysctrl, addr); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 498 | ret = cpu_inw(addr); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 499 | #ifdef TARGET_WORDS_BIGENDIAN |
| 500 | ret = bswap16(ret); |
| 501 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 502 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 503 | |
| 504 | return ret; |
| 505 | } |
| 506 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 507 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 508 | uint32_t value) |
| 509 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 510 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 511 | |
| 512 | addr = prep_IO_address(sysctrl, addr); |
| 513 | #ifdef TARGET_WORDS_BIGENDIAN |
| 514 | value = bswap32(value); |
| 515 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 516 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 517 | cpu_outl(addr, value); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 518 | } |
| 519 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 520 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 521 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 522 | sysctrl_t *sysctrl = opaque; |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 523 | uint32_t ret; |
| 524 | |
| 525 | addr = prep_IO_address(sysctrl, addr); |
Blue Swirl | afcea8c | 2009-09-20 16:05:47 +0000 | [diff] [blame] | 526 | ret = cpu_inl(addr); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 527 | #ifdef TARGET_WORDS_BIGENDIAN |
| 528 | ret = bswap32(ret); |
| 529 | #endif |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 530 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 531 | |
| 532 | return ret; |
| 533 | } |
| 534 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 535 | static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 536 | &PPC_prep_io_writeb, |
| 537 | &PPC_prep_io_writew, |
| 538 | &PPC_prep_io_writel, |
| 539 | }; |
| 540 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 541 | static CPUReadMemoryFunc * const PPC_prep_io_read[] = { |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 542 | &PPC_prep_io_readb, |
| 543 | &PPC_prep_io_readw, |
| 544 | &PPC_prep_io_readl, |
| 545 | }; |
| 546 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 547 | #define NVRAM_SIZE 0x2000 |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 548 | |
bellard | 26aa7d7 | 2004-04-28 22:26:05 +0000 | [diff] [blame] | 549 | /* PowerPC PREP hardware initialisation */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 550 | static void ppc_prep_init (ram_addr_t ram_size, |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 551 | const char *boot_device, |
blueswir1 | b881c2c | 2007-11-18 08:46:58 +0000 | [diff] [blame] | 552 | const char *kernel_filename, |
j_mayer | 94fc95c | 2007-03-05 19:44:02 +0000 | [diff] [blame] | 553 | const char *kernel_cmdline, |
| 554 | const char *initrd_filename, |
| 555 | const char *cpu_model) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 556 | { |
j_mayer | 0d913fd | 2007-11-11 14:44:28 +0000 | [diff] [blame] | 557 | CPUState *env = NULL, *envs[MAX_CPUS]; |
Paul Brook | 5cea859 | 2009-05-30 00:52:44 +0100 | [diff] [blame] | 558 | char *filename; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 559 | nvram_t nvram; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 560 | M48t59State *m48t59; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 561 | int PPC_io_memory; |
bellard | 4157a66 | 2005-07-03 16:00:49 +0000 | [diff] [blame] | 562 | int linux_boot, i, nb_nics1, bios_size; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 563 | ram_addr_t ram_offset, bios_offset; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 564 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
bellard | 46e50e9 | 2004-06-21 19:43:00 +0000 | [diff] [blame] | 565 | PCIBus *pci_bus; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 566 | qemu_irq *i8259; |
j_mayer | 28c5af5 | 2007-11-11 01:50:45 +0000 | [diff] [blame] | 567 | int ppc_boot_device; |
Gerd Hoffmann | f455e98 | 2009-08-28 15:47:03 +0200 | [diff] [blame] | 568 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
Gerd Hoffmann | fd8014e | 2009-09-22 13:53:18 +0200 | [diff] [blame] | 569 | DriveInfo *fd[MAX_FD]; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 570 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 571 | sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 572 | |
| 573 | linux_boot = (kernel_filename != NULL); |
j_mayer | 0a032cb | 2007-04-16 08:56:52 +0000 | [diff] [blame] | 574 | |
bellard | c68ea70 | 2005-11-21 23:33:12 +0000 | [diff] [blame] | 575 | /* init CPUs */ |
j_mayer | 94fc95c | 2007-03-05 19:44:02 +0000 | [diff] [blame] | 576 | if (cpu_model == NULL) |
Gerd Hoffmann | b37fc14 | 2009-09-14 17:49:24 +0200 | [diff] [blame] | 577 | cpu_model = "602"; |
j_mayer | fe33cc7 | 2007-10-03 01:06:57 +0000 | [diff] [blame] | 578 | for (i = 0; i < smp_cpus; i++) { |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 579 | env = cpu_init(cpu_model); |
| 580 | if (!env) { |
| 581 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
| 582 | exit(1); |
| 583 | } |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 584 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
| 585 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ |
| 586 | cpu_ppc_tb_init(env, 7812500UL); |
| 587 | } else { |
| 588 | /* Set time-base frequency to 100 Mhz */ |
| 589 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 590 | } |
Blue Swirl | d84bda4 | 2009-11-07 10:36:04 +0000 | [diff] [blame] | 591 | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
j_mayer | fe33cc7 | 2007-10-03 01:06:57 +0000 | [diff] [blame] | 592 | envs[i] = env; |
| 593 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 594 | |
| 595 | /* allocate RAM */ |
blueswir1 | cf9c147 | 2009-02-11 18:04:12 +0000 | [diff] [blame] | 596 | ram_offset = qemu_ram_alloc(ram_size); |
| 597 | cpu_register_physical_memory(0, ram_size, ram_offset); |
| 598 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 599 | /* allocate and load BIOS */ |
blueswir1 | cf9c147 | 2009-02-11 18:04:12 +0000 | [diff] [blame] | 600 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
j_mayer | 1192dad | 2007-10-05 13:08:35 +0000 | [diff] [blame] | 601 | if (bios_name == NULL) |
| 602 | bios_name = BIOS_FILENAME; |
Paul Brook | 5cea859 | 2009-05-30 00:52:44 +0100 | [diff] [blame] | 603 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 604 | if (filename) { |
| 605 | bios_size = get_image_size(filename); |
| 606 | } else { |
| 607 | bios_size = -1; |
| 608 | } |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 609 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 610 | target_phys_addr_t bios_addr; |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 611 | bios_size = (bios_size + 0xfff) & ~0xfff; |
| 612 | bios_addr = (uint32_t)(-bios_size); |
| 613 | cpu_register_physical_memory(bios_addr, bios_size, |
| 614 | bios_offset | IO_MEM_ROM); |
Paul Brook | 5cea859 | 2009-05-30 00:52:44 +0100 | [diff] [blame] | 615 | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 616 | } |
bellard | 4157a66 | 2005-07-03 16:00:49 +0000 | [diff] [blame] | 617 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
Paul Brook | 5cea859 | 2009-05-30 00:52:44 +0100 | [diff] [blame] | 618 | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); |
| 619 | } |
| 620 | if (filename) { |
| 621 | qemu_free(filename); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 622 | } |
j_mayer | 4c823cf | 2007-10-29 10:19:50 +0000 | [diff] [blame] | 623 | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 624 | hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); |
j_mayer | 4c823cf | 2007-10-29 10:19:50 +0000 | [diff] [blame] | 625 | } |
bellard | 26aa7d7 | 2004-04-28 22:26:05 +0000 | [diff] [blame] | 626 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 627 | if (linux_boot) { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 628 | kernel_base = KERNEL_LOAD_ADDR; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 629 | /* now we can load the kernel */ |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 630 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
| 631 | ram_size - kernel_base); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 632 | if (kernel_size < 0) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 633 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 634 | exit(1); |
| 635 | } |
| 636 | /* load initrd */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 637 | if (initrd_filename) { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 638 | initrd_base = INITRD_LOAD_ADDR; |
pbrook | dcac967 | 2009-04-09 20:05:49 +0000 | [diff] [blame] | 639 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
| 640 | ram_size - initrd_base); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 641 | if (initrd_size < 0) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 642 | hw_error("qemu: could not load initial ram disk '%s'\n", |
j_mayer | 4a05771 | 2007-04-19 08:42:21 +0000 | [diff] [blame] | 643 | initrd_filename); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 644 | } |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 645 | } else { |
| 646 | initrd_base = 0; |
| 647 | initrd_size = 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 648 | } |
balrog | 6ac0e82 | 2007-10-31 01:54:04 +0000 | [diff] [blame] | 649 | ppc_boot_device = 'm'; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 650 | } else { |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 651 | kernel_base = 0; |
| 652 | kernel_size = 0; |
| 653 | initrd_base = 0; |
| 654 | initrd_size = 0; |
j_mayer | 28c5af5 | 2007-11-11 01:50:45 +0000 | [diff] [blame] | 655 | ppc_boot_device = '\0'; |
| 656 | /* For now, OHW cannot boot from the network. */ |
j_mayer | 0d913fd | 2007-11-11 14:44:28 +0000 | [diff] [blame] | 657 | for (i = 0; boot_device[i] != '\0'; i++) { |
| 658 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
| 659 | ppc_boot_device = boot_device[i]; |
j_mayer | 28c5af5 | 2007-11-11 01:50:45 +0000 | [diff] [blame] | 660 | break; |
j_mayer | 0d913fd | 2007-11-11 14:44:28 +0000 | [diff] [blame] | 661 | } |
j_mayer | 28c5af5 | 2007-11-11 01:50:45 +0000 | [diff] [blame] | 662 | } |
| 663 | if (ppc_boot_device == '\0') { |
| 664 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); |
| 665 | exit(1); |
| 666 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 667 | } |
| 668 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 669 | isa_mem_base = 0xc0000000; |
j_mayer | dd37a5e | 2007-04-16 07:41:07 +0000 | [diff] [blame] | 670 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 671 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
j_mayer | dd37a5e | 2007-04-16 07:41:07 +0000 | [diff] [blame] | 672 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 673 | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 674 | pci_bus = pci_prep_init(i8259); |
Gerd Hoffmann | b37fc14 | 2009-09-14 17:49:24 +0200 | [diff] [blame] | 675 | /* Hmm, prep has no pci-isa bridge ??? */ |
| 676 | isa_bus_new(NULL); |
| 677 | isa_bus_irqs(i8259); |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 678 | // pci_bus = i440fx_init(); |
| 679 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 680 | PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
bellard | da9b266 | 2005-04-23 18:18:54 +0000 | [diff] [blame] | 681 | PPC_prep_io_write, sysctrl); |
| 682 | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 683 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 684 | /* init basic PC hardware */ |
Paul Brook | fbe1b59 | 2009-05-13 17:56:25 +0100 | [diff] [blame] | 685 | pci_vga_init(pci_bus, 0, 0); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 686 | // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 687 | // pit = pit_init(0x40, i8259[0]); |
Gerd Hoffmann | 32e0c82 | 2009-09-10 11:43:35 +0200 | [diff] [blame] | 688 | rtc_init(2000); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 689 | |
Gerd Hoffmann | ac0be99 | 2009-09-22 13:53:21 +0200 | [diff] [blame] | 690 | if (serial_hds[0]) |
| 691 | serial_isa_init(0, serial_hds[0]); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 692 | nb_nics1 = nb_nics; |
| 693 | if (nb_nics1 > NE2000_NB_MAX) |
| 694 | nb_nics1 = NE2000_NB_MAX; |
| 695 | for(i = 0; i < nb_nics1; i++) { |
aurel32 | 5652ef7 | 2009-01-09 13:10:41 +0000 | [diff] [blame] | 696 | if (nd_table[i].model == NULL) { |
Mark McLoughlin | 9203f52 | 2009-10-06 12:16:53 +0100 | [diff] [blame] | 697 | nd_table[i].model = qemu_strdup("ne2k_isa"); |
aurel32 | 5652ef7 | 2009-01-09 13:10:41 +0000 | [diff] [blame] | 698 | } |
| 699 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
Gerd Hoffmann | 9453c5b | 2009-09-10 11:43:33 +0200 | [diff] [blame] | 700 | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 701 | } else { |
Markus Armbruster | 07caea3 | 2009-09-25 03:53:51 +0200 | [diff] [blame] | 702 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 703 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 704 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 705 | |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 706 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
| 707 | fprintf(stderr, "qemu: too many IDE bus\n"); |
| 708 | exit(1); |
| 709 | } |
| 710 | |
| 711 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
Gerd Hoffmann | f455e98 | 2009-08-28 15:47:03 +0200 | [diff] [blame] | 712 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 713 | } |
| 714 | |
| 715 | for(i = 0; i < MAX_IDE_BUS; i++) { |
Gerd Hoffmann | dea21e9 | 2009-09-15 20:05:00 +0000 | [diff] [blame] | 716 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 717 | hd[2 * i], |
| 718 | hd[2 * i + 1]); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 719 | } |
Gerd Hoffmann | 11d23c3 | 2009-09-10 11:43:34 +0200 | [diff] [blame] | 720 | isa_create_simple("i8042"); |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 721 | DMA_init(1); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 722 | // SB16_init(); |
| 723 | |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 724 | for(i = 0; i < MAX_FD; i++) { |
Gerd Hoffmann | fd8014e | 2009-09-22 13:53:18 +0200 | [diff] [blame] | 725 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
ths | e4bcb14 | 2007-12-02 04:51:10 +0000 | [diff] [blame] | 726 | } |
Gerd Hoffmann | 86c8615 | 2009-09-10 11:43:26 +0200 | [diff] [blame] | 727 | fdctrl_init_isa(fd); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 728 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 729 | /* Register speaker port */ |
| 730 | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
| 731 | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 732 | /* Register fake IO ports for PREP */ |
j_mayer | c4781a5 | 2007-10-29 10:21:12 +0000 | [diff] [blame] | 733 | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 734 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
| 735 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 736 | /* System control ports */ |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 737 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
| 738 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
| 739 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
| 740 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
| 741 | /* PCI intack location */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 742 | PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 743 | PPC_intack_write, NULL); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 744 | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 745 | /* PowerPC control and status register group */ |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 746 | #if 0 |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 747 | PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 748 | NULL); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 749 | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 750 | #endif |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 751 | |
pbrook | 0d92ed3 | 2006-05-21 16:30:15 +0000 | [diff] [blame] | 752 | if (usb_enabled) { |
Paul Brook | a67ba3b | 2010-04-04 21:18:26 +0100 | [diff] [blame] | 753 | usb_ohci_init_pci(pci_bus, -1); |
pbrook | 0d92ed3 | 2006-05-21 16:30:15 +0000 | [diff] [blame] | 754 | } |
| 755 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 756 | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
| 757 | if (m48t59 == NULL) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 758 | return; |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 759 | sysctrl->nvram = m48t59; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 760 | |
| 761 | /* Initialise NVRAM */ |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 762 | nvram.opaque = m48t59; |
| 763 | nvram.read_fn = &m48t59_read; |
| 764 | nvram.write_fn = &m48t59_write; |
balrog | 6ac0e82 | 2007-10-31 01:54:04 +0000 | [diff] [blame] | 765 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 766 | kernel_base, kernel_size, |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 767 | kernel_cmdline, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 768 | initrd_base, initrd_size, |
| 769 | /* XXX: need an option to load a NVRAM image */ |
bellard | b6b8bd1 | 2004-06-21 16:55:53 +0000 | [diff] [blame] | 770 | 0, |
| 771 | graphic_width, graphic_height, graphic_depth); |
bellard | c0e564d | 2005-06-05 15:17:28 +0000 | [diff] [blame] | 772 | |
| 773 | /* Special port to get debug messages from Open-Firmware */ |
| 774 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 775 | } |
bellard | c0e564d | 2005-06-05 15:17:28 +0000 | [diff] [blame] | 776 | |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 777 | static QEMUMachine prep_machine = { |
aliguori | 4b32e16 | 2008-10-07 20:34:35 +0000 | [diff] [blame] | 778 | .name = "prep", |
| 779 | .desc = "PowerPC PREP platform", |
| 780 | .init = ppc_prep_init, |
balrog | 3d878ca | 2008-10-28 10:59:59 +0000 | [diff] [blame] | 781 | .max_cpus = MAX_CPUS, |
bellard | c0e564d | 2005-06-05 15:17:28 +0000 | [diff] [blame] | 782 | }; |
Anthony Liguori | f80f9ec | 2009-05-20 18:38:09 -0500 | [diff] [blame] | 783 | |
| 784 | static void prep_machine_init(void) |
| 785 | { |
| 786 | qemu_register_machine(&prep_machine); |
| 787 | } |
| 788 | |
| 789 | machine_init(prep_machine_init); |