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bellarda541f292004-04-12 20:39:29 +00001/*
2 * QEMU PPC PREP hardware System Emulator
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer47103572007-03-30 09:38:04 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
ths5fafdf22007-09-16 21:08:06 +00005 *
bellarda541f292004-04-12 20:39:29 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
pbrook87ecb682007-11-17 17:14:51 +000024#include "hw.h"
25#include "nvram.h"
26#include "pc.h"
27#include "fdc.h"
28#include "net.h"
29#include "sysemu.h"
30#include "isa.h"
31#include "pci.h"
Michael S. Tsirkin18e08a52009-11-11 14:59:56 +020032#include "prep_pci.h"
33#include "usb-ohci.h"
pbrook87ecb682007-11-17 17:14:51 +000034#include "ppc.h"
35#include "boards.h"
blueswir13b3fb322008-10-04 07:20:07 +000036#include "qemu-log.h"
Gerd Hoffmannec820262009-08-20 15:22:19 +020037#include "ide.h"
Blue Swirlca20cf32009-09-20 14:58:02 +000038#include "loader.h"
bellard9fddaa02004-05-21 12:59:32 +000039
bellarda541f292004-04-12 20:39:29 +000040//#define HARD_DEBUG_PPC_IO
41//#define DEBUG_PPC_IO
42
j_mayerfe33cc72007-10-03 01:06:57 +000043/* SMP is not enabled, for now */
44#define MAX_CPUS 1
45
thse4bcb142007-12-02 04:51:10 +000046#define MAX_IDE_BUS 2
47
Paul Brookbba831e2009-05-19 14:52:42 +010048#define BIOS_SIZE (1024 * 1024)
bellardb6b8bd12004-06-21 16:55:53 +000049#define BIOS_FILENAME "ppc_rom.bin"
50#define KERNEL_LOAD_ADDR 0x01000000
51#define INITRD_LOAD_ADDR 0x01800000
bellard64201202004-05-26 22:55:16 +000052
bellarda541f292004-04-12 20:39:29 +000053#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
54#define DEBUG_PPC_IO
55#endif
56
57#if defined (HARD_DEBUG_PPC_IO)
Blue Swirl001faf32009-05-13 17:53:17 +000058#define PPC_IO_DPRINTF(fmt, ...) \
bellarda541f292004-04-12 20:39:29 +000059do { \
aliguori8fec2b82009-01-15 22:36:53 +000060 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
Blue Swirl001faf32009-05-13 17:53:17 +000061 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
bellarda541f292004-04-12 20:39:29 +000062 } else { \
Blue Swirl001faf32009-05-13 17:53:17 +000063 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
bellarda541f292004-04-12 20:39:29 +000064 } \
65} while (0)
66#elif defined (DEBUG_PPC_IO)
Blue Swirl0bf9e312009-07-20 17:19:25 +000067#define PPC_IO_DPRINTF(fmt, ...) \
68qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
bellarda541f292004-04-12 20:39:29 +000069#else
Blue Swirl001faf32009-05-13 17:53:17 +000070#define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
bellarda541f292004-04-12 20:39:29 +000071#endif
72
bellard64201202004-05-26 22:55:16 +000073/* Constants for devices init */
bellarda541f292004-04-12 20:39:29 +000074static const int ide_iobase[2] = { 0x1f0, 0x170 };
75static const int ide_iobase2[2] = { 0x3f6, 0x376 };
76static const int ide_irq[2] = { 13, 13 };
77
78#define NE2000_NB_MAX 6
79
80static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
81static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
82
bellard64201202004-05-26 22:55:16 +000083//static PITState *pit;
84
85/* ISA IO ports bridge */
bellarda541f292004-04-12 20:39:29 +000086#define PPC_IO_BASE 0x80000000
87
blueswir1b1d8e522008-10-26 13:43:07 +000088#if 0
bellard64201202004-05-26 22:55:16 +000089/* Speaker port 0x61 */
blueswir1b1d8e522008-10-26 13:43:07 +000090static int speaker_data_on;
91static int dummy_refresh_clock;
92#endif
bellard64201202004-05-26 22:55:16 +000093
j_mayer36081602007-09-17 08:21:54 +000094static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
bellarda541f292004-04-12 20:39:29 +000095{
bellarda541f292004-04-12 20:39:29 +000096#if 0
bellard64201202004-05-26 22:55:16 +000097 speaker_data_on = (val >> 1) & 1;
98 pit_set_gate(pit, 2, val & 1);
bellarda541f292004-04-12 20:39:29 +000099#endif
bellarda541f292004-04-12 20:39:29 +0000100}
101
j_mayer47103572007-03-30 09:38:04 +0000102static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
bellarda541f292004-04-12 20:39:29 +0000103{
bellarda541f292004-04-12 20:39:29 +0000104#if 0
bellard64201202004-05-26 22:55:16 +0000105 int out;
106 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
107 dummy_refresh_clock ^= 1;
108 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
j_mayer47103572007-03-30 09:38:04 +0000109 (dummy_refresh_clock << 4);
bellarda541f292004-04-12 20:39:29 +0000110#endif
bellard64201202004-05-26 22:55:16 +0000111 return 0;
bellarda541f292004-04-12 20:39:29 +0000112}
113
bellard64201202004-05-26 22:55:16 +0000114/* PCI intack register */
bellarda541f292004-04-12 20:39:29 +0000115/* Read-only register (?) */
j_mayer47103572007-03-30 09:38:04 +0000116static void _PPC_intack_write (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500117 target_phys_addr_t addr, uint32_t value)
bellarda541f292004-04-12 20:39:29 +0000118{
Blue Swirl90e189e2009-08-16 11:13:18 +0000119#if 0
120 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
121 value);
122#endif
bellarda541f292004-04-12 20:39:29 +0000123}
124
Anthony Liguoric227f092009-10-01 16:12:16 -0500125static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
bellarda541f292004-04-12 20:39:29 +0000126{
127 uint32_t retval = 0;
128
aurel324dd8c132008-12-05 16:05:41 +0000129 if ((addr & 0xf) == 0)
bellard3de388f2005-07-02 18:11:44 +0000130 retval = pic_intack_read(isa_pic);
Blue Swirl90e189e2009-08-16 11:13:18 +0000131#if 0
132 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
133 retval);
134#endif
bellarda541f292004-04-12 20:39:29 +0000135
136 return retval;
137}
138
Anthony Liguoric227f092009-10-01 16:12:16 -0500139static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000140{
141 return _PPC_intack_read(addr);
142}
143
Anthony Liguoric227f092009-10-01 16:12:16 -0500144static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000145{
146#ifdef TARGET_WORDS_BIGENDIAN
147 return bswap16(_PPC_intack_read(addr));
148#else
149 return _PPC_intack_read(addr);
150#endif
151}
152
Anthony Liguoric227f092009-10-01 16:12:16 -0500153static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000154{
155#ifdef TARGET_WORDS_BIGENDIAN
156 return bswap32(_PPC_intack_read(addr));
157#else
158 return _PPC_intack_read(addr);
159#endif
160}
161
Blue Swirld60efc62009-08-25 18:29:31 +0000162static CPUWriteMemoryFunc * const PPC_intack_write[] = {
bellard64201202004-05-26 22:55:16 +0000163 &_PPC_intack_write,
164 &_PPC_intack_write,
165 &_PPC_intack_write,
bellarda541f292004-04-12 20:39:29 +0000166};
167
Blue Swirld60efc62009-08-25 18:29:31 +0000168static CPUReadMemoryFunc * const PPC_intack_read[] = {
bellard64201202004-05-26 22:55:16 +0000169 &PPC_intack_readb,
170 &PPC_intack_readw,
171 &PPC_intack_readl,
bellarda541f292004-04-12 20:39:29 +0000172};
173
bellard64201202004-05-26 22:55:16 +0000174/* PowerPC control and status registers */
175#if 0 // Not used
176static struct {
177 /* IDs */
178 uint32_t veni_devi;
179 uint32_t revi;
180 /* Control and status */
181 uint32_t gcsr;
182 uint32_t xcfr;
183 uint32_t ct32;
184 uint32_t mcsr;
185 /* General purpose registers */
186 uint32_t gprg[6];
187 /* Exceptions */
188 uint32_t feen;
189 uint32_t fest;
190 uint32_t fema;
191 uint32_t fecl;
192 uint32_t eeen;
193 uint32_t eest;
194 uint32_t eecl;
195 uint32_t eeint;
196 uint32_t eemck0;
197 uint32_t eemck1;
198 /* Error diagnostic */
199} XCSR;
bellarda541f292004-04-12 20:39:29 +0000200
j_mayer36081602007-09-17 08:21:54 +0000201static void PPC_XCSR_writeb (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500202 target_phys_addr_t addr, uint32_t value)
bellard64201202004-05-26 22:55:16 +0000203{
Blue Swirl90e189e2009-08-16 11:13:18 +0000204 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
205 value);
bellard64201202004-05-26 22:55:16 +0000206}
207
j_mayer36081602007-09-17 08:21:54 +0000208static void PPC_XCSR_writew (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500209 target_phys_addr_t addr, uint32_t value)
bellard64201202004-05-26 22:55:16 +0000210{
211#ifdef TARGET_WORDS_BIGENDIAN
212 value = bswap16(value);
213#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000214 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
215 value);
bellard64201202004-05-26 22:55:16 +0000216}
217
j_mayer36081602007-09-17 08:21:54 +0000218static void PPC_XCSR_writel (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500219 target_phys_addr_t addr, uint32_t value)
bellard64201202004-05-26 22:55:16 +0000220{
221#ifdef TARGET_WORDS_BIGENDIAN
222 value = bswap32(value);
223#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000224 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
225 value);
bellard64201202004-05-26 22:55:16 +0000226}
227
Anthony Liguoric227f092009-10-01 16:12:16 -0500228static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000229{
230 uint32_t retval = 0;
231
Blue Swirl90e189e2009-08-16 11:13:18 +0000232 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
233 retval);
bellard64201202004-05-26 22:55:16 +0000234
235 return retval;
236}
237
Anthony Liguoric227f092009-10-01 16:12:16 -0500238static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000239{
240 uint32_t retval = 0;
241
Blue Swirl90e189e2009-08-16 11:13:18 +0000242 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
243 retval);
bellard64201202004-05-26 22:55:16 +0000244#ifdef TARGET_WORDS_BIGENDIAN
245 retval = bswap16(retval);
246#endif
247
248 return retval;
249}
250
Anthony Liguoric227f092009-10-01 16:12:16 -0500251static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
bellard64201202004-05-26 22:55:16 +0000252{
253 uint32_t retval = 0;
254
Blue Swirl90e189e2009-08-16 11:13:18 +0000255 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
256 retval);
bellard64201202004-05-26 22:55:16 +0000257#ifdef TARGET_WORDS_BIGENDIAN
258 retval = bswap32(retval);
259#endif
260
261 return retval;
262}
263
Blue Swirld60efc62009-08-25 18:29:31 +0000264static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
bellard64201202004-05-26 22:55:16 +0000265 &PPC_XCSR_writeb,
266 &PPC_XCSR_writew,
267 &PPC_XCSR_writel,
268};
269
Blue Swirld60efc62009-08-25 18:29:31 +0000270static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
bellard64201202004-05-26 22:55:16 +0000271 &PPC_XCSR_readb,
272 &PPC_XCSR_readw,
273 &PPC_XCSR_readl,
274};
bellardb6b8bd12004-06-21 16:55:53 +0000275#endif
bellard64201202004-05-26 22:55:16 +0000276
bellarda541f292004-04-12 20:39:29 +0000277/* Fake super-io ports for PREP platform (Intel 82378ZB) */
Anthony Liguoric227f092009-10-01 16:12:16 -0500278typedef struct sysctrl_t {
j_mayerc4781a52007-10-29 10:21:12 +0000279 qemu_irq reset_irq;
Blue Swirl43a34702010-02-07 08:05:03 +0000280 M48t59State *nvram;
bellard64201202004-05-26 22:55:16 +0000281 uint8_t state;
282 uint8_t syscontrol;
283 uint8_t fake_io[2];
bellardda9b2662005-04-23 18:18:54 +0000284 int contiguous_map;
bellardfb3444b2005-07-03 13:57:11 +0000285 int endian;
Anthony Liguoric227f092009-10-01 16:12:16 -0500286} sysctrl_t;
bellard64201202004-05-26 22:55:16 +0000287
288enum {
289 STATE_HARDFILE = 0x01,
290};
291
Anthony Liguoric227f092009-10-01 16:12:16 -0500292static sysctrl_t *sysctrl;
bellarda541f292004-04-12 20:39:29 +0000293
294static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
295{
Anthony Liguoric227f092009-10-01 16:12:16 -0500296 sysctrl_t *sysctrl = opaque;
bellard64201202004-05-26 22:55:16 +0000297
j_mayeraae93662007-11-24 02:56:36 +0000298 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
299 val);
bellard64201202004-05-26 22:55:16 +0000300 sysctrl->fake_io[addr - 0x0398] = val;
bellarda541f292004-04-12 20:39:29 +0000301}
302
303static uint32_t PREP_io_read (void *opaque, uint32_t addr)
304{
Anthony Liguoric227f092009-10-01 16:12:16 -0500305 sysctrl_t *sysctrl = opaque;
bellarda541f292004-04-12 20:39:29 +0000306
j_mayeraae93662007-11-24 02:56:36 +0000307 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
bellard64201202004-05-26 22:55:16 +0000308 sysctrl->fake_io[addr - 0x0398]);
309 return sysctrl->fake_io[addr - 0x0398];
310}
bellarda541f292004-04-12 20:39:29 +0000311
312static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
313{
Anthony Liguoric227f092009-10-01 16:12:16 -0500314 sysctrl_t *sysctrl = opaque;
bellard64201202004-05-26 22:55:16 +0000315
j_mayeraae93662007-11-24 02:56:36 +0000316 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
317 addr - PPC_IO_BASE, val);
bellarda541f292004-04-12 20:39:29 +0000318 switch (addr) {
319 case 0x0092:
320 /* Special port 92 */
321 /* Check soft reset asked */
bellard64201202004-05-26 22:55:16 +0000322 if (val & 0x01) {
j_mayerc4781a52007-10-29 10:21:12 +0000323 qemu_irq_raise(sysctrl->reset_irq);
324 } else {
325 qemu_irq_lower(sysctrl->reset_irq);
bellarda541f292004-04-12 20:39:29 +0000326 }
327 /* Check LE mode */
bellard64201202004-05-26 22:55:16 +0000328 if (val & 0x02) {
bellardfb3444b2005-07-03 13:57:11 +0000329 sysctrl->endian = 1;
330 } else {
331 sysctrl->endian = 0;
bellarda541f292004-04-12 20:39:29 +0000332 }
333 break;
bellard64201202004-05-26 22:55:16 +0000334 case 0x0800:
335 /* Motorola CPU configuration register : read-only */
336 break;
337 case 0x0802:
338 /* Motorola base module feature register : read-only */
339 break;
340 case 0x0803:
341 /* Motorola base module status register : read-only */
342 break;
bellarda541f292004-04-12 20:39:29 +0000343 case 0x0808:
bellard64201202004-05-26 22:55:16 +0000344 /* Hardfile light register */
345 if (val & 1)
346 sysctrl->state |= STATE_HARDFILE;
347 else
348 sysctrl->state &= ~STATE_HARDFILE;
bellarda541f292004-04-12 20:39:29 +0000349 break;
350 case 0x0810:
351 /* Password protect 1 register */
bellard64201202004-05-26 22:55:16 +0000352 if (sysctrl->nvram != NULL)
353 m48t59_toggle_lock(sysctrl->nvram, 1);
bellarda541f292004-04-12 20:39:29 +0000354 break;
355 case 0x0812:
356 /* Password protect 2 register */
bellard64201202004-05-26 22:55:16 +0000357 if (sysctrl->nvram != NULL)
358 m48t59_toggle_lock(sysctrl->nvram, 2);
bellarda541f292004-04-12 20:39:29 +0000359 break;
360 case 0x0814:
bellard64201202004-05-26 22:55:16 +0000361 /* L2 invalidate register */
bellardc68ea702005-11-21 23:33:12 +0000362 // tlb_flush(first_cpu, 1);
bellarda541f292004-04-12 20:39:29 +0000363 break;
364 case 0x081C:
365 /* system control register */
bellard64201202004-05-26 22:55:16 +0000366 sysctrl->syscontrol = val & 0x0F;
bellarda541f292004-04-12 20:39:29 +0000367 break;
368 case 0x0850:
369 /* I/O map type register */
bellardda9b2662005-04-23 18:18:54 +0000370 sysctrl->contiguous_map = val & 0x01;
bellarda541f292004-04-12 20:39:29 +0000371 break;
372 default:
j_mayeraae93662007-11-24 02:56:36 +0000373 printf("ERROR: unaffected IO port write: %04" PRIx32
374 " => %02" PRIx32"\n", addr, val);
bellarda541f292004-04-12 20:39:29 +0000375 break;
376 }
377}
378
379static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
380{
Anthony Liguoric227f092009-10-01 16:12:16 -0500381 sysctrl_t *sysctrl = opaque;
bellarda541f292004-04-12 20:39:29 +0000382 uint32_t retval = 0xFF;
383
384 switch (addr) {
385 case 0x0092:
386 /* Special port 92 */
bellard64201202004-05-26 22:55:16 +0000387 retval = 0x00;
388 break;
389 case 0x0800:
390 /* Motorola CPU configuration register */
391 retval = 0xEF; /* MPC750 */
392 break;
393 case 0x0802:
394 /* Motorola Base module feature register */
395 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
396 break;
397 case 0x0803:
398 /* Motorola base module status register */
399 retval = 0xE0; /* Standard MPC750 */
bellarda541f292004-04-12 20:39:29 +0000400 break;
401 case 0x080C:
402 /* Equipment present register:
403 * no L2 cache
404 * no upgrade processor
405 * no cards in PCI slots
406 * SCSI fuse is bad
407 */
bellard64201202004-05-26 22:55:16 +0000408 retval = 0x3C;
409 break;
410 case 0x0810:
411 /* Motorola base module extended feature register */
412 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
bellarda541f292004-04-12 20:39:29 +0000413 break;
bellardda9b2662005-04-23 18:18:54 +0000414 case 0x0814:
415 /* L2 invalidate: don't care */
416 break;
bellarda541f292004-04-12 20:39:29 +0000417 case 0x0818:
418 /* Keylock */
419 retval = 0x00;
420 break;
421 case 0x081C:
422 /* system control register
423 * 7 - 6 / 1 - 0: L2 cache enable
424 */
bellard64201202004-05-26 22:55:16 +0000425 retval = sysctrl->syscontrol;
bellarda541f292004-04-12 20:39:29 +0000426 break;
427 case 0x0823:
428 /* */
429 retval = 0x03; /* no L2 cache */
430 break;
431 case 0x0850:
432 /* I/O map type register */
bellardda9b2662005-04-23 18:18:54 +0000433 retval = sysctrl->contiguous_map;
bellarda541f292004-04-12 20:39:29 +0000434 break;
435 default:
j_mayeraae93662007-11-24 02:56:36 +0000436 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
bellarda541f292004-04-12 20:39:29 +0000437 break;
438 }
j_mayeraae93662007-11-24 02:56:36 +0000439 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
440 addr - PPC_IO_BASE, retval);
bellarda541f292004-04-12 20:39:29 +0000441
442 return retval;
443}
444
Anthony Liguoric227f092009-10-01 16:12:16 -0500445static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
446 target_phys_addr_t addr)
bellardda9b2662005-04-23 18:18:54 +0000447{
448 if (sysctrl->contiguous_map == 0) {
449 /* 64 KB contiguous space for IOs */
450 addr &= 0xFFFF;
451 } else {
452 /* 8 MB non-contiguous space for IOs */
453 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
454 }
455
456 return addr;
457}
458
Anthony Liguoric227f092009-10-01 16:12:16 -0500459static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
bellardda9b2662005-04-23 18:18:54 +0000460 uint32_t value)
461{
Anthony Liguoric227f092009-10-01 16:12:16 -0500462 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000463
464 addr = prep_IO_address(sysctrl, addr);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000465 cpu_outb(addr, value);
bellardda9b2662005-04-23 18:18:54 +0000466}
467
Anthony Liguoric227f092009-10-01 16:12:16 -0500468static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
bellardda9b2662005-04-23 18:18:54 +0000469{
Anthony Liguoric227f092009-10-01 16:12:16 -0500470 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000471 uint32_t ret;
472
473 addr = prep_IO_address(sysctrl, addr);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000474 ret = cpu_inb(addr);
bellardda9b2662005-04-23 18:18:54 +0000475
476 return ret;
477}
478
Anthony Liguoric227f092009-10-01 16:12:16 -0500479static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
bellardda9b2662005-04-23 18:18:54 +0000480 uint32_t value)
481{
Anthony Liguoric227f092009-10-01 16:12:16 -0500482 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000483
484 addr = prep_IO_address(sysctrl, addr);
485#ifdef TARGET_WORDS_BIGENDIAN
486 value = bswap16(value);
487#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000488 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000489 cpu_outw(addr, value);
bellardda9b2662005-04-23 18:18:54 +0000490}
491
Anthony Liguoric227f092009-10-01 16:12:16 -0500492static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
bellardda9b2662005-04-23 18:18:54 +0000493{
Anthony Liguoric227f092009-10-01 16:12:16 -0500494 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000495 uint32_t ret;
496
497 addr = prep_IO_address(sysctrl, addr);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000498 ret = cpu_inw(addr);
bellardda9b2662005-04-23 18:18:54 +0000499#ifdef TARGET_WORDS_BIGENDIAN
500 ret = bswap16(ret);
501#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000502 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
bellardda9b2662005-04-23 18:18:54 +0000503
504 return ret;
505}
506
Anthony Liguoric227f092009-10-01 16:12:16 -0500507static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
bellardda9b2662005-04-23 18:18:54 +0000508 uint32_t value)
509{
Anthony Liguoric227f092009-10-01 16:12:16 -0500510 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000511
512 addr = prep_IO_address(sysctrl, addr);
513#ifdef TARGET_WORDS_BIGENDIAN
514 value = bswap32(value);
515#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000516 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000517 cpu_outl(addr, value);
bellardda9b2662005-04-23 18:18:54 +0000518}
519
Anthony Liguoric227f092009-10-01 16:12:16 -0500520static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
bellardda9b2662005-04-23 18:18:54 +0000521{
Anthony Liguoric227f092009-10-01 16:12:16 -0500522 sysctrl_t *sysctrl = opaque;
bellardda9b2662005-04-23 18:18:54 +0000523 uint32_t ret;
524
525 addr = prep_IO_address(sysctrl, addr);
Blue Swirlafcea8c2009-09-20 16:05:47 +0000526 ret = cpu_inl(addr);
bellardda9b2662005-04-23 18:18:54 +0000527#ifdef TARGET_WORDS_BIGENDIAN
528 ret = bswap32(ret);
529#endif
Blue Swirl90e189e2009-08-16 11:13:18 +0000530 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
bellardda9b2662005-04-23 18:18:54 +0000531
532 return ret;
533}
534
Blue Swirld60efc62009-08-25 18:29:31 +0000535static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
bellardda9b2662005-04-23 18:18:54 +0000536 &PPC_prep_io_writeb,
537 &PPC_prep_io_writew,
538 &PPC_prep_io_writel,
539};
540
Blue Swirld60efc62009-08-25 18:29:31 +0000541static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
bellardda9b2662005-04-23 18:18:54 +0000542 &PPC_prep_io_readb,
543 &PPC_prep_io_readw,
544 &PPC_prep_io_readl,
545};
546
bellard64201202004-05-26 22:55:16 +0000547#define NVRAM_SIZE 0x2000
bellarda541f292004-04-12 20:39:29 +0000548
bellard26aa7d72004-04-28 22:26:05 +0000549/* PowerPC PREP hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -0500550static void ppc_prep_init (ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000551 const char *boot_device,
blueswir1b881c2c2007-11-18 08:46:58 +0000552 const char *kernel_filename,
j_mayer94fc95c2007-03-05 19:44:02 +0000553 const char *kernel_cmdline,
554 const char *initrd_filename,
555 const char *cpu_model)
bellarda541f292004-04-12 20:39:29 +0000556{
j_mayer0d913fd2007-11-11 14:44:28 +0000557 CPUState *env = NULL, *envs[MAX_CPUS];
Paul Brook5cea8592009-05-30 00:52:44 +0100558 char *filename;
Anthony Liguoric227f092009-10-01 16:12:16 -0500559 nvram_t nvram;
Blue Swirl43a34702010-02-07 08:05:03 +0000560 M48t59State *m48t59;
bellarda541f292004-04-12 20:39:29 +0000561 int PPC_io_memory;
bellard4157a662005-07-03 16:00:49 +0000562 int linux_boot, i, nb_nics1, bios_size;
Anthony Liguoric227f092009-10-01 16:12:16 -0500563 ram_addr_t ram_offset, bios_offset;
bellard64201202004-05-26 22:55:16 +0000564 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
bellard46e50e92004-06-21 19:43:00 +0000565 PCIBus *pci_bus;
pbrookd537cf62007-04-07 18:14:41 +0000566 qemu_irq *i8259;
j_mayer28c5af52007-11-11 01:50:45 +0000567 int ppc_boot_device;
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200568 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200569 DriveInfo *fd[MAX_FD];
bellard64201202004-05-26 22:55:16 +0000570
Anthony Liguoric227f092009-10-01 16:12:16 -0500571 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
bellarda541f292004-04-12 20:39:29 +0000572
573 linux_boot = (kernel_filename != NULL);
j_mayer0a032cb2007-04-16 08:56:52 +0000574
bellardc68ea702005-11-21 23:33:12 +0000575 /* init CPUs */
j_mayer94fc95c2007-03-05 19:44:02 +0000576 if (cpu_model == NULL)
Gerd Hoffmannb37fc142009-09-14 17:49:24 +0200577 cpu_model = "602";
j_mayerfe33cc72007-10-03 01:06:57 +0000578 for (i = 0; i < smp_cpus; i++) {
bellardaaed9092007-11-10 15:15:54 +0000579 env = cpu_init(cpu_model);
580 if (!env) {
581 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
582 exit(1);
583 }
j_mayer4018bae2007-11-19 01:48:12 +0000584 if (env->flags & POWERPC_FLAG_RTC_CLK) {
585 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
586 cpu_ppc_tb_init(env, 7812500UL);
587 } else {
588 /* Set time-base frequency to 100 Mhz */
589 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
590 }
Blue Swirld84bda42009-11-07 10:36:04 +0000591 qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
j_mayerfe33cc72007-10-03 01:06:57 +0000592 envs[i] = env;
593 }
bellarda541f292004-04-12 20:39:29 +0000594
595 /* allocate RAM */
blueswir1cf9c1472009-02-11 18:04:12 +0000596 ram_offset = qemu_ram_alloc(ram_size);
597 cpu_register_physical_memory(0, ram_size, ram_offset);
598
bellard64201202004-05-26 22:55:16 +0000599 /* allocate and load BIOS */
blueswir1cf9c1472009-02-11 18:04:12 +0000600 bios_offset = qemu_ram_alloc(BIOS_SIZE);
j_mayer1192dad2007-10-05 13:08:35 +0000601 if (bios_name == NULL)
602 bios_name = BIOS_FILENAME;
Paul Brook5cea8592009-05-30 00:52:44 +0100603 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
604 if (filename) {
605 bios_size = get_image_size(filename);
606 } else {
607 bios_size = -1;
608 }
pbrookdcac9672009-04-09 20:05:49 +0000609 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
Anthony Liguoric227f092009-10-01 16:12:16 -0500610 target_phys_addr_t bios_addr;
pbrookdcac9672009-04-09 20:05:49 +0000611 bios_size = (bios_size + 0xfff) & ~0xfff;
612 bios_addr = (uint32_t)(-bios_size);
613 cpu_register_physical_memory(bios_addr, bios_size,
614 bios_offset | IO_MEM_ROM);
Paul Brook5cea8592009-05-30 00:52:44 +0100615 bios_size = load_image_targphys(filename, bios_addr, bios_size);
pbrookdcac9672009-04-09 20:05:49 +0000616 }
bellard4157a662005-07-03 16:00:49 +0000617 if (bios_size < 0 || bios_size > BIOS_SIZE) {
Paul Brook5cea8592009-05-30 00:52:44 +0100618 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
619 }
620 if (filename) {
621 qemu_free(filename);
bellard64201202004-05-26 22:55:16 +0000622 }
j_mayer4c823cf2007-10-29 10:19:50 +0000623 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
Paul Brook2ac71172009-05-08 02:35:15 +0100624 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
j_mayer4c823cf2007-10-29 10:19:50 +0000625 }
bellard26aa7d72004-04-28 22:26:05 +0000626
bellarda541f292004-04-12 20:39:29 +0000627 if (linux_boot) {
bellard64201202004-05-26 22:55:16 +0000628 kernel_base = KERNEL_LOAD_ADDR;
bellarda541f292004-04-12 20:39:29 +0000629 /* now we can load the kernel */
pbrookdcac9672009-04-09 20:05:49 +0000630 kernel_size = load_image_targphys(kernel_filename, kernel_base,
631 ram_size - kernel_base);
bellard64201202004-05-26 22:55:16 +0000632 if (kernel_size < 0) {
Paul Brook2ac71172009-05-08 02:35:15 +0100633 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
bellarda541f292004-04-12 20:39:29 +0000634 exit(1);
635 }
636 /* load initrd */
bellarda541f292004-04-12 20:39:29 +0000637 if (initrd_filename) {
bellard64201202004-05-26 22:55:16 +0000638 initrd_base = INITRD_LOAD_ADDR;
pbrookdcac9672009-04-09 20:05:49 +0000639 initrd_size = load_image_targphys(initrd_filename, initrd_base,
640 ram_size - initrd_base);
bellarda541f292004-04-12 20:39:29 +0000641 if (initrd_size < 0) {
Paul Brook2ac71172009-05-08 02:35:15 +0100642 hw_error("qemu: could not load initial ram disk '%s'\n",
j_mayer4a057712007-04-19 08:42:21 +0000643 initrd_filename);
bellarda541f292004-04-12 20:39:29 +0000644 }
bellard64201202004-05-26 22:55:16 +0000645 } else {
646 initrd_base = 0;
647 initrd_size = 0;
bellarda541f292004-04-12 20:39:29 +0000648 }
balrog6ac0e822007-10-31 01:54:04 +0000649 ppc_boot_device = 'm';
bellarda541f292004-04-12 20:39:29 +0000650 } else {
bellard64201202004-05-26 22:55:16 +0000651 kernel_base = 0;
652 kernel_size = 0;
653 initrd_base = 0;
654 initrd_size = 0;
j_mayer28c5af52007-11-11 01:50:45 +0000655 ppc_boot_device = '\0';
656 /* For now, OHW cannot boot from the network. */
j_mayer0d913fd2007-11-11 14:44:28 +0000657 for (i = 0; boot_device[i] != '\0'; i++) {
658 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
659 ppc_boot_device = boot_device[i];
j_mayer28c5af52007-11-11 01:50:45 +0000660 break;
j_mayer0d913fd2007-11-11 14:44:28 +0000661 }
j_mayer28c5af52007-11-11 01:50:45 +0000662 }
663 if (ppc_boot_device == '\0') {
664 fprintf(stderr, "No valid boot device for Mac99 machine\n");
665 exit(1);
666 }
bellarda541f292004-04-12 20:39:29 +0000667 }
668
bellard64201202004-05-26 22:55:16 +0000669 isa_mem_base = 0xc0000000;
j_mayerdd37a5e2007-04-16 07:41:07 +0000670 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
Paul Brook2ac71172009-05-08 02:35:15 +0100671 hw_error("Only 6xx bus is supported on PREP machine\n");
j_mayerdd37a5e2007-04-16 07:41:07 +0000672 }
j_mayer24be5ae2007-04-12 21:24:29 +0000673 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pbrookd537cf62007-04-07 18:14:41 +0000674 pci_bus = pci_prep_init(i8259);
Gerd Hoffmannb37fc142009-09-14 17:49:24 +0200675 /* Hmm, prep has no pci-isa bridge ??? */
676 isa_bus_new(NULL);
677 isa_bus_irqs(i8259);
bellardda9b2662005-04-23 18:18:54 +0000678 // pci_bus = i440fx_init();
679 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
Avi Kivity1eed09c2009-06-14 11:38:51 +0300680 PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
bellardda9b2662005-04-23 18:18:54 +0000681 PPC_prep_io_write, sysctrl);
682 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
bellard64201202004-05-26 22:55:16 +0000683
bellarda541f292004-04-12 20:39:29 +0000684 /* init basic PC hardware */
Paul Brookfbe1b592009-05-13 17:56:25 +0100685 pci_vga_init(pci_bus, 0, 0);
bellard64201202004-05-26 22:55:16 +0000686 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
pbrookd537cf62007-04-07 18:14:41 +0000687 // pit = pit_init(0x40, i8259[0]);
Gerd Hoffmann32e0c822009-09-10 11:43:35 +0200688 rtc_init(2000);
bellarda541f292004-04-12 20:39:29 +0000689
Gerd Hoffmannac0be992009-09-22 13:53:21 +0200690 if (serial_hds[0])
691 serial_isa_init(0, serial_hds[0]);
bellarda541f292004-04-12 20:39:29 +0000692 nb_nics1 = nb_nics;
693 if (nb_nics1 > NE2000_NB_MAX)
694 nb_nics1 = NE2000_NB_MAX;
695 for(i = 0; i < nb_nics1; i++) {
aurel325652ef72009-01-09 13:10:41 +0000696 if (nd_table[i].model == NULL) {
Mark McLoughlin9203f522009-10-06 12:16:53 +0100697 nd_table[i].model = qemu_strdup("ne2k_isa");
aurel325652ef72009-01-09 13:10:41 +0000698 }
699 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
Gerd Hoffmann9453c5b2009-09-10 11:43:33 +0200700 isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
pbrooka41b2ff2006-02-05 04:14:41 +0000701 } else {
Markus Armbruster07caea32009-09-25 03:53:51 +0200702 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
pbrooka41b2ff2006-02-05 04:14:41 +0000703 }
bellarda541f292004-04-12 20:39:29 +0000704 }
bellarda541f292004-04-12 20:39:29 +0000705
thse4bcb142007-12-02 04:51:10 +0000706 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
707 fprintf(stderr, "qemu: too many IDE bus\n");
708 exit(1);
709 }
710
711 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
Gerd Hoffmannf455e982009-08-28 15:47:03 +0200712 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
thse4bcb142007-12-02 04:51:10 +0000713 }
714
715 for(i = 0; i < MAX_IDE_BUS; i++) {
Gerd Hoffmanndea21e92009-09-15 20:05:00 +0000716 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
thse4bcb142007-12-02 04:51:10 +0000717 hd[2 * i],
718 hd[2 * i + 1]);
bellarda541f292004-04-12 20:39:29 +0000719 }
Gerd Hoffmann11d23c32009-09-10 11:43:34 +0200720 isa_create_simple("i8042");
bellardb6b8bd12004-06-21 16:55:53 +0000721 DMA_init(1);
bellarda541f292004-04-12 20:39:29 +0000722 // SB16_init();
723
thse4bcb142007-12-02 04:51:10 +0000724 for(i = 0; i < MAX_FD; i++) {
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200725 fd[i] = drive_get(IF_FLOPPY, 0, i);
thse4bcb142007-12-02 04:51:10 +0000726 }
Gerd Hoffmann86c86152009-09-10 11:43:26 +0200727 fdctrl_init_isa(fd);
bellarda541f292004-04-12 20:39:29 +0000728
bellard64201202004-05-26 22:55:16 +0000729 /* Register speaker port */
730 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
731 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
bellarda541f292004-04-12 20:39:29 +0000732 /* Register fake IO ports for PREP */
j_mayerc4781a52007-10-29 10:21:12 +0000733 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
bellard64201202004-05-26 22:55:16 +0000734 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
735 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
bellarda541f292004-04-12 20:39:29 +0000736 /* System control ports */
bellard64201202004-05-26 22:55:16 +0000737 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
738 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
739 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
740 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
741 /* PCI intack location */
Avi Kivity1eed09c2009-06-14 11:38:51 +0300742 PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
bellarda4193c82004-06-03 14:01:43 +0000743 PPC_intack_write, NULL);
bellarda541f292004-04-12 20:39:29 +0000744 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
bellard64201202004-05-26 22:55:16 +0000745 /* PowerPC control and status register group */
bellardb6b8bd12004-06-21 16:55:53 +0000746#if 0
Avi Kivity1eed09c2009-06-14 11:38:51 +0300747 PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
j_mayer36081602007-09-17 08:21:54 +0000748 NULL);
bellard64201202004-05-26 22:55:16 +0000749 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
bellardb6b8bd12004-06-21 16:55:53 +0000750#endif
bellarda541f292004-04-12 20:39:29 +0000751
pbrook0d92ed32006-05-21 16:30:15 +0000752 if (usb_enabled) {
Paul Brooka67ba3b2010-04-04 21:18:26 +0100753 usb_ohci_init_pci(pci_bus, -1);
pbrook0d92ed32006-05-21 16:30:15 +0000754 }
755
j_mayer3cbee152007-10-28 23:42:18 +0000756 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
757 if (m48t59 == NULL)
bellard64201202004-05-26 22:55:16 +0000758 return;
j_mayer3cbee152007-10-28 23:42:18 +0000759 sysctrl->nvram = m48t59;
bellard64201202004-05-26 22:55:16 +0000760
761 /* Initialise NVRAM */
j_mayer3cbee152007-10-28 23:42:18 +0000762 nvram.opaque = m48t59;
763 nvram.read_fn = &m48t59_read;
764 nvram.write_fn = &m48t59_write;
balrog6ac0e822007-10-31 01:54:04 +0000765 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
bellard64201202004-05-26 22:55:16 +0000766 kernel_base, kernel_size,
bellardb6b8bd12004-06-21 16:55:53 +0000767 kernel_cmdline,
bellard64201202004-05-26 22:55:16 +0000768 initrd_base, initrd_size,
769 /* XXX: need an option to load a NVRAM image */
bellardb6b8bd12004-06-21 16:55:53 +0000770 0,
771 graphic_width, graphic_height, graphic_depth);
bellardc0e564d2005-06-05 15:17:28 +0000772
773 /* Special port to get debug messages from Open-Firmware */
774 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
bellarda541f292004-04-12 20:39:29 +0000775}
bellardc0e564d2005-06-05 15:17:28 +0000776
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500777static QEMUMachine prep_machine = {
aliguori4b32e162008-10-07 20:34:35 +0000778 .name = "prep",
779 .desc = "PowerPC PREP platform",
780 .init = ppc_prep_init,
balrog3d878ca2008-10-28 10:59:59 +0000781 .max_cpus = MAX_CPUS,
bellardc0e564d2005-06-05 15:17:28 +0000782};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500783
784static void prep_machine_init(void)
785{
786 qemu_register_machine(&prep_machine);
787}
788
789machine_init(prep_machine_init);