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j_mayer1a6c0882007-04-24 07:40:49 +00001/*
2 * QEMU PowerPC 405 evaluation boards emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer1a6c0882007-04-24 07:40:49 +00004 * Copyright (c) 2007 Jocelyn Mayer
ths5fafdf22007-09-16 21:08:06 +00005 *
j_mayer1a6c0882007-04-24 07:40:49 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
pbrook87ecb682007-11-17 17:14:51 +000024#include "hw.h"
25#include "ppc.h"
j_mayer1a6c0882007-04-24 07:40:49 +000026#include "ppc405.h"
pbrook87ecb682007-11-17 17:14:51 +000027#include "nvram.h"
28#include "flash.h"
29#include "sysemu.h"
30#include "block.h"
31#include "boards.h"
blueswir13b3fb322008-10-04 07:20:07 +000032#include "qemu-log.h"
Blue Swirlca20cf32009-09-20 14:58:02 +000033#include "loader.h"
j_mayer1a6c0882007-04-24 07:40:49 +000034
35#define BIOS_FILENAME "ppc405_rom.bin"
j_mayer1a6c0882007-04-24 07:40:49 +000036#define BIOS_SIZE (2048 * 1024)
37
38#define KERNEL_LOAD_ADDR 0x00000000
39#define INITRD_LOAD_ADDR 0x01800000
40
41#define USE_FLASH_BIOS
42
43#define DEBUG_BOARD_INIT
44
45/*****************************************************************************/
46/* PPC405EP reference board (IBM) */
47/* Standalone board with:
48 * - PowerPC 405EP CPU
49 * - SDRAM (0x00000000)
50 * - Flash (0xFFF80000)
51 * - SRAM (0xFFF00000)
52 * - NVRAM (0xF0000000)
53 * - FPGA (0xF0300000)
54 */
Anthony Liguoric227f092009-10-01 16:12:16 -050055typedef struct ref405ep_fpga_t ref405ep_fpga_t;
56struct ref405ep_fpga_t {
j_mayer1a6c0882007-04-24 07:40:49 +000057 uint8_t reg0;
58 uint8_t reg1;
59};
60
Anthony Liguoric227f092009-10-01 16:12:16 -050061static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +000062{
Anthony Liguoric227f092009-10-01 16:12:16 -050063 ref405ep_fpga_t *fpga;
j_mayer1a6c0882007-04-24 07:40:49 +000064 uint32_t ret;
65
66 fpga = opaque;
j_mayer1a6c0882007-04-24 07:40:49 +000067 switch (addr) {
68 case 0x0:
69 ret = fpga->reg0;
70 break;
71 case 0x1:
72 ret = fpga->reg1;
73 break;
74 default:
75 ret = 0;
76 break;
77 }
78
79 return ret;
80}
81
82static void ref405ep_fpga_writeb (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -050083 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +000084{
Anthony Liguoric227f092009-10-01 16:12:16 -050085 ref405ep_fpga_t *fpga;
j_mayer1a6c0882007-04-24 07:40:49 +000086
87 fpga = opaque;
j_mayer1a6c0882007-04-24 07:40:49 +000088 switch (addr) {
89 case 0x0:
90 /* Read only */
91 break;
92 case 0x1:
93 fpga->reg1 = value;
94 break;
95 default:
96 break;
97 }
98}
99
Anthony Liguoric227f092009-10-01 16:12:16 -0500100static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +0000101{
102 uint32_t ret;
103
104 ret = ref405ep_fpga_readb(opaque, addr) << 8;
105 ret |= ref405ep_fpga_readb(opaque, addr + 1);
106
107 return ret;
108}
109
110static void ref405ep_fpga_writew (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500111 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +0000112{
113 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
114 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
115}
116
Anthony Liguoric227f092009-10-01 16:12:16 -0500117static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +0000118{
119 uint32_t ret;
120
121 ret = ref405ep_fpga_readb(opaque, addr) << 24;
122 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
123 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
124 ret |= ref405ep_fpga_readb(opaque, addr + 3);
125
126 return ret;
127}
128
129static void ref405ep_fpga_writel (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500130 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +0000131{
aurel328de24102008-12-11 22:43:07 +0000132 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
133 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
134 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
j_mayer1a6c0882007-04-24 07:40:49 +0000135 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
136}
137
Blue Swirld60efc62009-08-25 18:29:31 +0000138static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
j_mayer1a6c0882007-04-24 07:40:49 +0000139 &ref405ep_fpga_readb,
140 &ref405ep_fpga_readw,
141 &ref405ep_fpga_readl,
142};
143
Blue Swirld60efc62009-08-25 18:29:31 +0000144static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
j_mayer1a6c0882007-04-24 07:40:49 +0000145 &ref405ep_fpga_writeb,
146 &ref405ep_fpga_writew,
147 &ref405ep_fpga_writel,
148};
149
150static void ref405ep_fpga_reset (void *opaque)
151{
Anthony Liguoric227f092009-10-01 16:12:16 -0500152 ref405ep_fpga_t *fpga;
j_mayer1a6c0882007-04-24 07:40:49 +0000153
154 fpga = opaque;
155 fpga->reg0 = 0x00;
156 fpga->reg1 = 0x0F;
157}
158
159static void ref405ep_fpga_init (uint32_t base)
160{
Anthony Liguoric227f092009-10-01 16:12:16 -0500161 ref405ep_fpga_t *fpga;
j_mayer1a6c0882007-04-24 07:40:49 +0000162 int fpga_memory;
163
Anthony Liguoric227f092009-10-01 16:12:16 -0500164 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
Avi Kivity1eed09c2009-06-14 11:38:51 +0300165 fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
aliguori487414f2009-02-05 22:06:05 +0000166 ref405ep_fpga_write, fpga);
167 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200168 qemu_register_reset(&ref405ep_fpga_reset, fpga);
j_mayer1a6c0882007-04-24 07:40:49 +0000169}
170
Anthony Liguoric227f092009-10-01 16:12:16 -0500171static void ref405ep_init (ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000172 const char *boot_device,
ths5fafdf22007-09-16 21:08:06 +0000173 const char *kernel_filename,
j_mayer1a6c0882007-04-24 07:40:49 +0000174 const char *kernel_cmdline,
175 const char *initrd_filename,
176 const char *cpu_model)
177{
Paul Brook5cea8592009-05-30 00:52:44 +0100178 char *filename;
Anthony Liguoric227f092009-10-01 16:12:16 -0500179 ppc4xx_bd_info_t bd;
j_mayer1a6c0882007-04-24 07:40:49 +0000180 CPUPPCState *env;
181 qemu_irq *pic;
Anthony Liguoric227f092009-10-01 16:12:16 -0500182 ram_addr_t sram_offset, bios_offset, bdloc;
183 target_phys_addr_t ram_bases[2], ram_sizes[2];
j_mayer1a6c0882007-04-24 07:40:49 +0000184 target_ulong sram_size, bios_size;
185 //int phy_addr = 0;
186 //static int phy_addr = 1;
187 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
188 int linux_boot;
189 int fl_idx, fl_sectors, len;
balrog6ac0e822007-10-31 01:54:04 +0000190 int ppc_boot_device = boot_device[0];
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200191 DriveInfo *dinfo;
j_mayer1a6c0882007-04-24 07:40:49 +0000192
193 /* XXX: fix this */
pbrook5c130f62009-04-10 14:29:45 +0000194 ram_bases[0] = qemu_ram_alloc(0x08000000);
j_mayer1a6c0882007-04-24 07:40:49 +0000195 ram_sizes[0] = 0x08000000;
196 ram_bases[1] = 0x00000000;
197 ram_sizes[1] = 0x00000000;
198 ram_size = 128 * 1024 * 1024;
199#ifdef DEBUG_BOARD_INIT
200 printf("%s: register cpu\n", __func__);
201#endif
pbrook5c130f62009-04-10 14:29:45 +0000202 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
j_mayer1a6c0882007-04-24 07:40:49 +0000203 kernel_filename == NULL ? 0 : 1);
204 /* allocate SRAM */
pbrook5c130f62009-04-10 14:29:45 +0000205 sram_size = 512 * 1024;
206 sram_offset = qemu_ram_alloc(sram_size);
j_mayer1a6c0882007-04-24 07:40:49 +0000207#ifdef DEBUG_BOARD_INIT
208 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
209#endif
j_mayer1a6c0882007-04-24 07:40:49 +0000210 cpu_register_physical_memory(0xFFF00000, sram_size,
211 sram_offset | IO_MEM_RAM);
212 /* allocate and load BIOS */
213#ifdef DEBUG_BOARD_INIT
214 printf("%s: register BIOS\n", __func__);
215#endif
j_mayer1a6c0882007-04-24 07:40:49 +0000216 fl_idx = 0;
217#ifdef USE_FLASH_BIOS
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200218 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
219 if (dinfo) {
220 bios_size = bdrv_getlength(dinfo->bdrv);
pbrook5c130f62009-04-10 14:29:45 +0000221 bios_offset = qemu_ram_alloc(bios_size);
j_mayer1a6c0882007-04-24 07:40:49 +0000222 fl_sectors = (bios_size + 65535) >> 16;
223#ifdef DEBUG_BOARD_INIT
Blue Swirl90e189e2009-08-16 11:13:18 +0000224 printf("Register parallel flash %d size " TARGET_FMT_lx
225 " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000226 fl_idx, bios_size, bios_offset, -bios_size,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200227 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
j_mayer1a6c0882007-04-24 07:40:49 +0000228#endif
balrog88eeee02007-12-10 00:28:27 +0000229 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200230 dinfo->bdrv, 65536, fl_sectors, 1,
Blue Swirl5f9fc5a2010-03-29 19:23:55 +0000231 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
232 1);
j_mayer1a6c0882007-04-24 07:40:49 +0000233 fl_idx++;
234 } else
235#endif
236 {
237#ifdef DEBUG_BOARD_INIT
238 printf("Load BIOS from file\n");
239#endif
Paul Brook5cea8592009-05-30 00:52:44 +0100240 bios_offset = qemu_ram_alloc(BIOS_SIZE);
j_mayer1192dad2007-10-05 13:08:35 +0000241 if (bios_name == NULL)
242 bios_name = BIOS_FILENAME;
Paul Brook5cea8592009-05-30 00:52:44 +0100243 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
244 if (filename) {
245 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
246 qemu_free(filename);
247 } else {
248 bios_size = -1;
249 }
j_mayer1a6c0882007-04-24 07:40:49 +0000250 if (bios_size < 0 || bios_size > BIOS_SIZE) {
Paul Brook5cea8592009-05-30 00:52:44 +0100251 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
252 bios_name);
j_mayer1a6c0882007-04-24 07:40:49 +0000253 exit(1);
254 }
255 bios_size = (bios_size + 0xfff) & ~0xfff;
ths5fafdf22007-09-16 21:08:06 +0000256 cpu_register_physical_memory((uint32_t)(-bios_size),
j_mayer1a6c0882007-04-24 07:40:49 +0000257 bios_size, bios_offset | IO_MEM_ROM);
258 }
j_mayer1a6c0882007-04-24 07:40:49 +0000259 /* Register FPGA */
260#ifdef DEBUG_BOARD_INIT
261 printf("%s: register FPGA\n", __func__);
262#endif
263 ref405ep_fpga_init(0xF0300000);
264 /* Register NVRAM */
265#ifdef DEBUG_BOARD_INIT
266 printf("%s: register NVRAM\n", __func__);
267#endif
268 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
269 /* Load kernel */
270 linux_boot = (kernel_filename != NULL);
271 if (linux_boot) {
272#ifdef DEBUG_BOARD_INIT
273 printf("%s: load kernel\n", __func__);
274#endif
275 memset(&bd, 0, sizeof(bd));
276 bd.bi_memstart = 0x00000000;
277 bd.bi_memsize = ram_size;
j_mayer217fae22007-10-03 01:04:20 +0000278 bd.bi_flashstart = -bios_size;
j_mayer1a6c0882007-04-24 07:40:49 +0000279 bd.bi_flashsize = -bios_size;
280 bd.bi_flashoffset = 0;
281 bd.bi_sramstart = 0xFFF00000;
282 bd.bi_sramsize = sram_size;
283 bd.bi_bootflags = 0;
284 bd.bi_intfreq = 133333333;
285 bd.bi_busfreq = 33333333;
286 bd.bi_baudrate = 115200;
287 bd.bi_s_version[0] = 'Q';
288 bd.bi_s_version[1] = 'M';
289 bd.bi_s_version[2] = 'U';
290 bd.bi_s_version[3] = '\0';
291 bd.bi_r_version[0] = 'Q';
292 bd.bi_r_version[1] = 'E';
293 bd.bi_r_version[2] = 'M';
294 bd.bi_r_version[3] = 'U';
295 bd.bi_r_version[4] = '\0';
296 bd.bi_procfreq = 133333333;
297 bd.bi_plb_busfreq = 33333333;
298 bd.bi_pci_busfreq = 33333333;
299 bd.bi_opbfreq = 33333333;
j_mayerb8d3f5d2007-09-26 23:55:31 +0000300 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
j_mayer1a6c0882007-04-24 07:40:49 +0000301 env->gpr[3] = bdloc;
302 kernel_base = KERNEL_LOAD_ADDR;
303 /* now we can load the kernel */
pbrook5c130f62009-04-10 14:29:45 +0000304 kernel_size = load_image_targphys(kernel_filename, kernel_base,
305 ram_size - kernel_base);
j_mayer1a6c0882007-04-24 07:40:49 +0000306 if (kernel_size < 0) {
ths5fafdf22007-09-16 21:08:06 +0000307 fprintf(stderr, "qemu: could not load kernel '%s'\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000308 kernel_filename);
309 exit(1);
310 }
pbrook5c130f62009-04-10 14:29:45 +0000311 printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
312 kernel_size, kernel_base);
j_mayer1a6c0882007-04-24 07:40:49 +0000313 /* load initrd */
314 if (initrd_filename) {
315 initrd_base = INITRD_LOAD_ADDR;
pbrook5c130f62009-04-10 14:29:45 +0000316 initrd_size = load_image_targphys(initrd_filename, initrd_base,
317 ram_size - initrd_base);
j_mayer1a6c0882007-04-24 07:40:49 +0000318 if (initrd_size < 0) {
ths5fafdf22007-09-16 21:08:06 +0000319 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000320 initrd_filename);
321 exit(1);
322 }
323 } else {
324 initrd_base = 0;
325 initrd_size = 0;
326 }
327 env->gpr[4] = initrd_base;
328 env->gpr[5] = initrd_size;
balrog6ac0e822007-10-31 01:54:04 +0000329 ppc_boot_device = 'm';
j_mayer1a6c0882007-04-24 07:40:49 +0000330 if (kernel_cmdline != NULL) {
331 len = strlen(kernel_cmdline);
332 bdloc -= ((len + 255) & ~255);
pbrook5c130f62009-04-10 14:29:45 +0000333 cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
j_mayer1a6c0882007-04-24 07:40:49 +0000334 env->gpr[6] = bdloc;
335 env->gpr[7] = bdloc + len;
336 } else {
337 env->gpr[6] = 0;
338 env->gpr[7] = 0;
339 }
340 env->nip = KERNEL_LOAD_ADDR;
341 } else {
342 kernel_base = 0;
343 kernel_size = 0;
344 initrd_base = 0;
345 initrd_size = 0;
346 bdloc = 0;
347 }
348#ifdef DEBUG_BOARD_INIT
349 printf("%s: Done\n", __func__);
350#endif
pbrook5c130f62009-04-10 14:29:45 +0000351 printf("bdloc %016lx\n", (unsigned long)bdloc);
j_mayer1a6c0882007-04-24 07:40:49 +0000352}
353
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500354static QEMUMachine ref405ep_machine = {
aliguori4b32e162008-10-07 20:34:35 +0000355 .name = "ref405ep",
356 .desc = "ref405ep",
357 .init = ref405ep_init,
j_mayer1a6c0882007-04-24 07:40:49 +0000358};
359
360/*****************************************************************************/
361/* AMCC Taihu evaluation board */
362/* - PowerPC 405EP processor
363 * - SDRAM 128 MB at 0x00000000
364 * - Boot flash 2 MB at 0xFFE00000
365 * - Application flash 32 MB at 0xFC000000
366 * - 2 serial ports
367 * - 2 ethernet PHY
368 * - 1 USB 1.1 device 0x50000000
369 * - 1 LCD display 0x50100000
370 * - 1 CPLD 0x50100000
371 * - 1 I2C EEPROM
372 * - 1 I2C thermal sensor
373 * - a set of LEDs
374 * - bit-bang SPI port using GPIOs
375 * - 1 EBC interface connector 0 0x50200000
376 * - 1 cardbus controller + expansion slot.
377 * - 1 PCI expansion slot.
378 */
379typedef struct taihu_cpld_t taihu_cpld_t;
380struct taihu_cpld_t {
j_mayer1a6c0882007-04-24 07:40:49 +0000381 uint8_t reg0;
382 uint8_t reg1;
383};
384
Anthony Liguoric227f092009-10-01 16:12:16 -0500385static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +0000386{
387 taihu_cpld_t *cpld;
388 uint32_t ret;
389
390 cpld = opaque;
j_mayer1a6c0882007-04-24 07:40:49 +0000391 switch (addr) {
392 case 0x0:
393 ret = cpld->reg0;
394 break;
395 case 0x1:
396 ret = cpld->reg1;
397 break;
398 default:
399 ret = 0;
400 break;
401 }
402
403 return ret;
404}
405
406static void taihu_cpld_writeb (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500407 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +0000408{
409 taihu_cpld_t *cpld;
410
411 cpld = opaque;
j_mayer1a6c0882007-04-24 07:40:49 +0000412 switch (addr) {
413 case 0x0:
414 /* Read only */
415 break;
416 case 0x1:
417 cpld->reg1 = value;
418 break;
419 default:
420 break;
421 }
422}
423
Anthony Liguoric227f092009-10-01 16:12:16 -0500424static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +0000425{
426 uint32_t ret;
427
428 ret = taihu_cpld_readb(opaque, addr) << 8;
429 ret |= taihu_cpld_readb(opaque, addr + 1);
430
431 return ret;
432}
433
434static void taihu_cpld_writew (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500435 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +0000436{
437 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
438 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
439}
440
Anthony Liguoric227f092009-10-01 16:12:16 -0500441static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
j_mayer1a6c0882007-04-24 07:40:49 +0000442{
443 uint32_t ret;
444
445 ret = taihu_cpld_readb(opaque, addr) << 24;
446 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
447 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
448 ret |= taihu_cpld_readb(opaque, addr + 3);
449
450 return ret;
451}
452
453static void taihu_cpld_writel (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500454 target_phys_addr_t addr, uint32_t value)
j_mayer1a6c0882007-04-24 07:40:49 +0000455{
456 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
457 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
458 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
459 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
460}
461
Blue Swirld60efc62009-08-25 18:29:31 +0000462static CPUReadMemoryFunc * const taihu_cpld_read[] = {
j_mayer1a6c0882007-04-24 07:40:49 +0000463 &taihu_cpld_readb,
464 &taihu_cpld_readw,
465 &taihu_cpld_readl,
466};
467
Blue Swirld60efc62009-08-25 18:29:31 +0000468static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
j_mayer1a6c0882007-04-24 07:40:49 +0000469 &taihu_cpld_writeb,
470 &taihu_cpld_writew,
471 &taihu_cpld_writel,
472};
473
474static void taihu_cpld_reset (void *opaque)
475{
476 taihu_cpld_t *cpld;
477
478 cpld = opaque;
479 cpld->reg0 = 0x01;
480 cpld->reg1 = 0x80;
481}
482
483static void taihu_cpld_init (uint32_t base)
484{
485 taihu_cpld_t *cpld;
486 int cpld_memory;
487
488 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
Avi Kivity1eed09c2009-06-14 11:38:51 +0300489 cpld_memory = cpu_register_io_memory(taihu_cpld_read,
aliguori487414f2009-02-05 22:06:05 +0000490 taihu_cpld_write, cpld);
491 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200492 qemu_register_reset(&taihu_cpld_reset, cpld);
j_mayer1a6c0882007-04-24 07:40:49 +0000493}
494
Anthony Liguoric227f092009-10-01 16:12:16 -0500495static void taihu_405ep_init(ram_addr_t ram_size,
aliguori3023f332009-01-16 19:04:14 +0000496 const char *boot_device,
ths5fafdf22007-09-16 21:08:06 +0000497 const char *kernel_filename,
j_mayer1a6c0882007-04-24 07:40:49 +0000498 const char *kernel_cmdline,
499 const char *initrd_filename,
500 const char *cpu_model)
501{
Paul Brook5cea8592009-05-30 00:52:44 +0100502 char *filename;
j_mayer1a6c0882007-04-24 07:40:49 +0000503 CPUPPCState *env;
504 qemu_irq *pic;
Anthony Liguoric227f092009-10-01 16:12:16 -0500505 ram_addr_t bios_offset;
506 target_phys_addr_t ram_bases[2], ram_sizes[2];
j_mayer1a6c0882007-04-24 07:40:49 +0000507 target_ulong bios_size;
508 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
509 int linux_boot;
510 int fl_idx, fl_sectors;
balrog6ac0e822007-10-31 01:54:04 +0000511 int ppc_boot_device = boot_device[0];
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200512 DriveInfo *dinfo;
ths3b46e622007-09-17 08:09:54 +0000513
j_mayer1a6c0882007-04-24 07:40:49 +0000514 /* RAM is soldered to the board so the size cannot be changed */
pbrook5c130f62009-04-10 14:29:45 +0000515 ram_bases[0] = qemu_ram_alloc(0x04000000);
j_mayer1a6c0882007-04-24 07:40:49 +0000516 ram_sizes[0] = 0x04000000;
pbrook5c130f62009-04-10 14:29:45 +0000517 ram_bases[1] = qemu_ram_alloc(0x04000000);
j_mayer1a6c0882007-04-24 07:40:49 +0000518 ram_sizes[1] = 0x04000000;
pbrooka0b753d2009-04-11 17:24:39 +0000519 ram_size = 0x08000000;
j_mayer1a6c0882007-04-24 07:40:49 +0000520#ifdef DEBUG_BOARD_INIT
521 printf("%s: register cpu\n", __func__);
522#endif
pbrook5c130f62009-04-10 14:29:45 +0000523 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
j_mayer1a6c0882007-04-24 07:40:49 +0000524 kernel_filename == NULL ? 0 : 1);
525 /* allocate and load BIOS */
526#ifdef DEBUG_BOARD_INIT
527 printf("%s: register BIOS\n", __func__);
528#endif
529 fl_idx = 0;
530#if defined(USE_FLASH_BIOS)
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200531 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
532 if (dinfo) {
533 bios_size = bdrv_getlength(dinfo->bdrv);
j_mayer1a6c0882007-04-24 07:40:49 +0000534 /* XXX: should check that size is 2MB */
535 // bios_size = 2 * 1024 * 1024;
536 fl_sectors = (bios_size + 65535) >> 16;
pbrook5c130f62009-04-10 14:29:45 +0000537 bios_offset = qemu_ram_alloc(bios_size);
j_mayer1a6c0882007-04-24 07:40:49 +0000538#ifdef DEBUG_BOARD_INIT
Blue Swirl90e189e2009-08-16 11:13:18 +0000539 printf("Register parallel flash %d size " TARGET_FMT_lx
540 " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000541 fl_idx, bios_size, bios_offset, -bios_size,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200542 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
j_mayer1a6c0882007-04-24 07:40:49 +0000543#endif
balrog88eeee02007-12-10 00:28:27 +0000544 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200545 dinfo->bdrv, 65536, fl_sectors, 1,
Blue Swirl5f9fc5a2010-03-29 19:23:55 +0000546 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
547 1);
j_mayer1a6c0882007-04-24 07:40:49 +0000548 fl_idx++;
549 } else
550#endif
551 {
552#ifdef DEBUG_BOARD_INIT
553 printf("Load BIOS from file\n");
554#endif
j_mayer1192dad2007-10-05 13:08:35 +0000555 if (bios_name == NULL)
556 bios_name = BIOS_FILENAME;
pbrook5c130f62009-04-10 14:29:45 +0000557 bios_offset = qemu_ram_alloc(BIOS_SIZE);
Paul Brook5cea8592009-05-30 00:52:44 +0100558 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
559 if (filename) {
560 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
561 } else {
562 bios_size = -1;
563 }
j_mayer1a6c0882007-04-24 07:40:49 +0000564 if (bios_size < 0 || bios_size > BIOS_SIZE) {
Paul Brook5cea8592009-05-30 00:52:44 +0100565 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
566 bios_name);
j_mayer1a6c0882007-04-24 07:40:49 +0000567 exit(1);
568 }
569 bios_size = (bios_size + 0xfff) & ~0xfff;
ths5fafdf22007-09-16 21:08:06 +0000570 cpu_register_physical_memory((uint32_t)(-bios_size),
j_mayer1a6c0882007-04-24 07:40:49 +0000571 bios_size, bios_offset | IO_MEM_ROM);
572 }
j_mayer1a6c0882007-04-24 07:40:49 +0000573 /* Register Linux flash */
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200574 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
575 if (dinfo) {
576 bios_size = bdrv_getlength(dinfo->bdrv);
j_mayer1a6c0882007-04-24 07:40:49 +0000577 /* XXX: should check that size is 32MB */
578 bios_size = 32 * 1024 * 1024;
579 fl_sectors = (bios_size + 65535) >> 16;
580#ifdef DEBUG_BOARD_INIT
Blue Swirl90e189e2009-08-16 11:13:18 +0000581 printf("Register parallel flash %d size " TARGET_FMT_lx
582 " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000583 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200584 bdrv_get_device_name(dinfo->bdrv));
j_mayer1a6c0882007-04-24 07:40:49 +0000585#endif
pbrook5c130f62009-04-10 14:29:45 +0000586 bios_offset = qemu_ram_alloc(bios_size);
balrog88eeee02007-12-10 00:28:27 +0000587 pflash_cfi02_register(0xfc000000, bios_offset,
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200588 dinfo->bdrv, 65536, fl_sectors, 1,
Blue Swirl5f9fc5a2010-03-29 19:23:55 +0000589 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
590 1);
j_mayer1a6c0882007-04-24 07:40:49 +0000591 fl_idx++;
592 }
593 /* Register CLPD & LCD display */
594#ifdef DEBUG_BOARD_INIT
595 printf("%s: register CPLD\n", __func__);
596#endif
597 taihu_cpld_init(0x50100000);
598 /* Load kernel */
599 linux_boot = (kernel_filename != NULL);
600 if (linux_boot) {
601#ifdef DEBUG_BOARD_INIT
602 printf("%s: load kernel\n", __func__);
603#endif
604 kernel_base = KERNEL_LOAD_ADDR;
605 /* now we can load the kernel */
pbrook5c130f62009-04-10 14:29:45 +0000606 kernel_size = load_image_targphys(kernel_filename, kernel_base,
607 ram_size - kernel_base);
j_mayer1a6c0882007-04-24 07:40:49 +0000608 if (kernel_size < 0) {
ths5fafdf22007-09-16 21:08:06 +0000609 fprintf(stderr, "qemu: could not load kernel '%s'\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000610 kernel_filename);
611 exit(1);
612 }
613 /* load initrd */
614 if (initrd_filename) {
615 initrd_base = INITRD_LOAD_ADDR;
pbrook5c130f62009-04-10 14:29:45 +0000616 initrd_size = load_image_targphys(initrd_filename, initrd_base,
617 ram_size - initrd_base);
j_mayer1a6c0882007-04-24 07:40:49 +0000618 if (initrd_size < 0) {
619 fprintf(stderr,
ths5fafdf22007-09-16 21:08:06 +0000620 "qemu: could not load initial ram disk '%s'\n",
j_mayer1a6c0882007-04-24 07:40:49 +0000621 initrd_filename);
622 exit(1);
623 }
624 } else {
625 initrd_base = 0;
626 initrd_size = 0;
627 }
balrog6ac0e822007-10-31 01:54:04 +0000628 ppc_boot_device = 'm';
j_mayer1a6c0882007-04-24 07:40:49 +0000629 } else {
630 kernel_base = 0;
631 kernel_size = 0;
632 initrd_base = 0;
633 initrd_size = 0;
634 }
635#ifdef DEBUG_BOARD_INIT
636 printf("%s: Done\n", __func__);
637#endif
638}
639
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500640static QEMUMachine taihu_machine = {
pbrookb2ee0ce2009-04-11 17:41:32 +0000641 .name = "taihu",
642 .desc = "taihu",
643 .init = taihu_405ep_init,
j_mayer1a6c0882007-04-24 07:40:49 +0000644};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500645
646static void ppc405_machine_init(void)
647{
648 qemu_register_machine(&ref405ep_machine);
649 qemu_register_machine(&taihu_machine);
650}
651
652machine_init(ppc405_machine_init);