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balrog7e7c5e42008-04-14 21:57:44 +00001/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
aurel32fad6cb12009-01-04 22:05:52 +000017 * You should have received a copy of the GNU General Public License along
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * with this program; if not, see <http://www.gnu.org/licenses/>.
balrog7e7c5e42008-04-14 21:57:44 +000019 */
20
Peter Maydell12b16722015-12-07 16:23:45 +000021#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010022#include "qapi/error.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010023#include "cpu.h"
Thomas Huth6da68df2019-11-20 10:10:11 +010024#include "chardev/char.h"
Veronia Bahaaf348b6d2016-03-20 19:16:19 +020025#include "qemu/cutils.h"
Paolo Bonzini58369e22016-03-15 17:22:36 +010026#include "qemu/bswap.h"
Peter Maydell15e09912022-02-08 20:08:56 +000027#include "qemu/hw-version.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020028#include "sysemu/reset.h"
Markus Armbruster54d31232019-08-12 07:23:59 +020029#include "sysemu/runstate.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010030#include "sysemu/sysemu.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010031#include "hw/arm/omap.h"
Peter Maydell12ec8bd2019-05-23 14:47:43 +010032#include "hw/arm/boot.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/irq.h"
Paolo Bonzini28ecbae2012-11-28 12:06:30 +010034#include "ui/console.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010035#include "hw/boards.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010036#include "hw/i2c/i2c.h"
Philippe Mathieu-Daudé8a08cc72019-04-12 18:54:09 +020037#include "hw/display/blizzard.h"
Philippe Mathieu-Daudé410bbee2021-06-17 13:53:20 +020038#include "hw/input/lm832x.h"
Philippe Mathieu-Daudéa331dd02019-04-12 18:54:12 +020039#include "hw/input/tsc2xxx.h"
Philippe Mathieu-Daudée8fa3952019-04-12 18:54:10 +020040#include "hw/misc/cbus.h"
Corey Minyard5e9ae4b2021-05-18 16:08:03 -050041#include "hw/sensor/tmp105.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020042#include "hw/qdev-properties.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010043#include "hw/block/flash.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010044#include "hw/hw.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010045#include "hw/loader.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010046#include "hw/sysbus.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010047#include "qemu/log.h"
Richard Hendersoncc37d982023-03-15 17:43:13 +000048#include "qemu/error-report.h"
49
balrog7e7c5e42008-04-14 21:57:44 +000050
51/* Nokia N8x0 support */
52struct n800_s {
Andreas Färber518ec132012-05-13 22:13:15 +020053 struct omap_mpu_state_s *mpu;
balrog7e7c5e42008-04-14 21:57:44 +000054
55 struct rfbi_chip_s blizzard;
balroge927bb02008-05-07 14:30:38 +000056 struct {
57 void *opaque;
58 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
Paul Brookbc24a222009-05-10 01:44:56 +010059 uWireSlave *chip;
balroge927bb02008-05-07 14:30:38 +000060 } ts;
balrog7e7c5e42008-04-14 21:57:44 +000061
62 int keymap[0x80];
Peter Maydellc4f05c82011-07-29 16:35:18 +010063 DeviceState *kbd;
balrog7e7c5e42008-04-14 21:57:44 +000064
Peter Maydellbdc76462011-08-30 18:36:56 +010065 DeviceState *usb;
balrog7e7c5e42008-04-14 21:57:44 +000066 void *retu;
67 void *tahvo;
Juha Riihimäki500954e2011-08-28 16:22:17 +000068 DeviceState *nand;
balrog7e7c5e42008-04-14 21:57:44 +000069};
70
71/* GPIO pins */
balroge927bb02008-05-07 14:30:38 +000072#define N8X0_TUSB_ENABLE_GPIO 0
balrog7e7c5e42008-04-14 21:57:44 +000073#define N800_MMC2_WP_GPIO 8
74#define N800_UNKNOWN_GPIO0 9 /* out */
balrog09410412008-05-18 13:14:29 +000075#define N810_MMC2_VIOSD_GPIO 9
balrog99570a42008-07-18 07:50:20 +000076#define N810_HEADSET_AMP_GPIO 10
balrog7e7c5e42008-04-14 21:57:44 +000077#define N800_CAM_TURN_GPIO 12
balroge927bb02008-05-07 14:30:38 +000078#define N810_GPS_RESET_GPIO 12
balrog7e7c5e42008-04-14 21:57:44 +000079#define N800_BLIZZARD_POWERDOWN_GPIO 15
80#define N800_MMC1_WP_GPIO 23
balrog09410412008-05-18 13:14:29 +000081#define N810_MMC2_VSD_GPIO 23
balrog7e7c5e42008-04-14 21:57:44 +000082#define N8X0_ONENAND_GPIO 26
balroge927bb02008-05-07 14:30:38 +000083#define N810_BLIZZARD_RESET_GPIO 30
balrog7e7c5e42008-04-14 21:57:44 +000084#define N800_UNKNOWN_GPIO2 53 /* out */
85#define N8X0_TUSB_INT_GPIO 58
balroge927bb02008-05-07 14:30:38 +000086#define N8X0_BT_WKUP_GPIO 61
87#define N8X0_STI_GPIO 62
balrog7e7c5e42008-04-14 21:57:44 +000088#define N8X0_CBUS_SEL_GPIO 64
balroge927bb02008-05-07 14:30:38 +000089#define N8X0_CBUS_DAT_GPIO 65
90#define N8X0_CBUS_CLK_GPIO 66
91#define N8X0_WLAN_IRQ_GPIO 87
92#define N8X0_BT_RESET_GPIO 92
93#define N8X0_TEA5761_CS_GPIO 93
balrog7e7c5e42008-04-14 21:57:44 +000094#define N800_UNKNOWN_GPIO 94
balroge927bb02008-05-07 14:30:38 +000095#define N810_TSC_RESET_GPIO 94
balrog7e7c5e42008-04-14 21:57:44 +000096#define N800_CAM_ACT_GPIO 95
balroge927bb02008-05-07 14:30:38 +000097#define N810_GPS_WAKEUP_GPIO 95
98#define N8X0_MMC_CS_GPIO 96
99#define N8X0_WLAN_PWR_GPIO 97
balrog7e7c5e42008-04-14 21:57:44 +0000100#define N8X0_BT_HOST_WKUP_GPIO 98
balrog99570a42008-07-18 07:50:20 +0000101#define N810_SPEAKER_AMP_GPIO 101
balrog7e7c5e42008-04-14 21:57:44 +0000102#define N810_KB_LOCK_GPIO 102
103#define N800_TSC_TS_GPIO 103
balroge927bb02008-05-07 14:30:38 +0000104#define N810_TSC_TS_GPIO 106
105#define N8X0_HEADPHONE_GPIO 107
balrog7e7c5e42008-04-14 21:57:44 +0000106#define N8X0_RETU_GPIO 108
107#define N800_TSC_KP_IRQ_GPIO 109
108#define N810_KEYBOARD_GPIO 109
109#define N800_BAT_COVER_GPIO 110
110#define N810_SLIDE_GPIO 110
111#define N8X0_TAHVO_GPIO 111
112#define N800_UNKNOWN_GPIO4 112 /* out */
balroge927bb02008-05-07 14:30:38 +0000113#define N810_SLEEPX_LED_GPIO 112
balrog1d4e5472008-05-09 22:16:11 +0000114#define N800_TSC_RESET_GPIO 118 /* ? */
balrog99570a42008-07-18 07:50:20 +0000115#define N810_AIC33_RESET_GPIO 118
balrog1d4e5472008-05-09 22:16:11 +0000116#define N800_TSC_UNKNOWN_GPIO 119 /* out */
balrog7e7c5e42008-04-14 21:57:44 +0000117#define N8X0_TMP105_GPIO 125
118
119/* Config */
balrogc580d922008-07-29 14:19:16 +0000120#define BT_UART 0
balrog7e7c5e42008-04-14 21:57:44 +0000121#define XLDR_LL_UART 1
122
balrog1d4e5472008-05-09 22:16:11 +0000123/* Addresses on the I2C bus 0 */
124#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
125#define N8X0_TCM825x_ADDR 0x29 /* Camera */
126#define N810_LP5521_ADDR 0x32 /* LEDs */
127#define N810_TSL2563_ADDR 0x3d /* Light sensor */
128#define N810_LM8323_ADDR 0x45 /* Keyboard */
129/* Addresses on the I2C bus 1 */
130#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
131#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
balrog7e7c5e42008-04-14 21:57:44 +0000132
133/* Chipselects on GPMC NOR interface */
134#define N8X0_ONENAND_CS 0
135#define N8X0_USB_ASYNC_CS 1
136#define N8X0_USB_SYNC_CS 4
137
balrogc580d922008-07-29 14:19:16 +0000138#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
139
balrog7e7c5e42008-04-14 21:57:44 +0000140static void n800_mmc_cs_cb(void *opaque, int line, int level)
141{
142 /* TODO: this seems to actually be connected to the menelaus, to
143 * which also both MMC slots connect. */
144 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
balrog7e7c5e42008-04-14 21:57:44 +0000145}
146
balroge927bb02008-05-07 14:30:38 +0000147static void n8x0_gpio_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000148{
Shannon Zhao294972c2015-05-29 13:27:10 +0800149 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
150 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
Andreas Färber518ec132012-05-13 22:13:15 +0200151 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
balrog7e7c5e42008-04-14 21:57:44 +0000152}
153
balrogc580d922008-07-29 14:19:16 +0000154#define MAEMO_CAL_HEADER(...) \
155 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
156 __VA_ARGS__, \
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
158
159static const uint8_t n8x0_cal_wlan_mac[] = {
160 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
161 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
162 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
163 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
164 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
165 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
166};
167
168static const uint8_t n8x0_cal_bt_id[] = {
169 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
170 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
171 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
172 N8X0_BD_ADDR,
173};
174
balrog7e7c5e42008-04-14 21:57:44 +0000175static void n8x0_nand_setup(struct n800_s *s)
176{
balrogc580d922008-07-29 14:19:16 +0000177 char *otp_region;
Peter Maydellaf5a75f2011-07-29 16:35:25 +0100178 DriveInfo *dinfo;
balrogc580d922008-07-29 14:19:16 +0000179
Markus Armbruster3e80f692020-06-10 07:31:58 +0200180 s->nand = qdev_new("onenand");
Juha Riihimäki500954e2011-08-28 16:22:17 +0000181 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
Juha Riihimäki5923ba42011-07-29 16:35:26 +0100182 /* Either 0x40 or 0x48 are OK for the device ID */
Juha Riihimäki500954e2011-08-28 16:22:17 +0000183 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
184 qdev_prop_set_uint16(s->nand, "version_id", 0);
185 qdev_prop_set_int32(s->nand, "shift", 1);
186 dinfo = drive_get(IF_MTD, 0, 0);
Markus Armbrusterfa1d36d2014-10-07 13:59:13 +0200187 if (dinfo) {
Markus Armbruster934df912020-06-22 11:42:24 +0200188 qdev_prop_set_drive_err(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
189 &error_fatal);
Juha Riihimäki500954e2011-08-28 16:22:17 +0000190 }
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200191 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->nand), &error_fatal);
Andreas Färber1356b982013-01-20 02:47:33 +0100192 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
Andreas Färber518ec132012-05-13 22:13:15 +0200193 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
194 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
Andreas Färber1356b982013-01-20 02:47:33 +0100195 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
balrogc580d922008-07-29 14:19:16 +0000196 otp_region = onenand_raw_otp(s->nand);
197
198 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
199 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
200 /* XXX: in theory should also update the OOB for both pages */
balrog7e7c5e42008-04-14 21:57:44 +0000201}
202
Igor Mammedovc72ddb12012-09-05 23:06:23 +0200203static qemu_irq n8x0_system_powerdown;
204
205static void n8x0_powerdown_req(Notifier *n, void *opaque)
206{
207 qemu_irq_raise(n8x0_system_powerdown);
208}
209
210static Notifier n8x0_system_powerdown_notifier = {
211 .notify = n8x0_powerdown_req
212};
213
balroge927bb02008-05-07 14:30:38 +0000214static void n8x0_i2c_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000215{
Paul Brook697454e2009-05-14 22:35:08 +0100216 DeviceState *dev;
Andreas Färber518ec132012-05-13 22:13:15 +0200217 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
Andreas Färbera5c82852013-08-03 00:18:51 +0200218 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
balrog7e7c5e42008-04-14 21:57:44 +0000219
220 /* Attach a menelaus PM chip */
Philippe Mathieu-Daudé1373b152020-07-06 00:41:53 +0200221 dev = DEVICE(i2c_slave_create_simple(i2c, "twl92230", N8X0_MENELAUS_ADDR));
Peter Maydell0919ac72011-09-23 09:44:38 +0000222 qdev_connect_gpio_out(dev, 3,
Andreas Färber518ec132012-05-13 22:13:15 +0200223 qdev_get_gpio_in(s->mpu->ih[0],
Peter Maydell0919ac72011-09-23 09:44:38 +0000224 OMAP_INT_24XX_SYS_NIRQ));
balrog7e7c5e42008-04-14 21:57:44 +0000225
Igor Mammedovc72ddb12012-09-05 23:06:23 +0200226 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
227 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
Paolo Bonzinidd4427a2012-01-20 12:10:34 +0100228
balrog7e7c5e42008-04-14 21:57:44 +0000229 /* Attach a TMP105 PM chip (A0 wired to ground) */
Philippe Mathieu-Daudé1373b152020-07-06 00:41:53 +0200230 dev = DEVICE(i2c_slave_create_simple(i2c, TYPE_TMP105, N8X0_TMP105_ADDR));
Paul Brook697454e2009-05-14 22:35:08 +0100231 qdev_connect_gpio_out(dev, 0, tmp_irq);
balrog7e7c5e42008-04-14 21:57:44 +0000232}
233
234/* Touchscreen and keypad controller */
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +0100235static const MouseTransformInfo n800_pointercal = {
balroge927bb02008-05-07 14:30:38 +0000236 .x = 800,
237 .y = 480,
238 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
239};
240
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +0100241static const MouseTransformInfo n810_pointercal = {
balroge927bb02008-05-07 14:30:38 +0000242 .x = 800,
243 .y = 480,
244 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
245};
246
balrog7e7c5e42008-04-14 21:57:44 +0000247#define RETU_KEYCODE 61 /* F3 */
248
249static void n800_key_event(void *opaque, int keycode)
250{
251 struct n800_s *s = (struct n800_s *) opaque;
252 int code = s->keymap[keycode & 0x7f];
253
254 if (code == -1) {
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200255 if ((keycode & 0x7f) == RETU_KEYCODE) {
balrog7e7c5e42008-04-14 21:57:44 +0000256 retu_key_event(s->retu, !(keycode & 0x80));
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200257 }
balrog7e7c5e42008-04-14 21:57:44 +0000258 return;
259 }
260
balroge927bb02008-05-07 14:30:38 +0000261 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
balrog7e7c5e42008-04-14 21:57:44 +0000262}
263
264static const int n800_keys[16] = {
265 -1,
266 72, /* Up */
267 63, /* Home (F5) */
268 -1,
269 75, /* Left */
270 28, /* Enter */
271 77, /* Right */
272 -1,
balrog1d4e5472008-05-09 22:16:11 +0000273 1, /* Cycle (ESC) */
balrog7e7c5e42008-04-14 21:57:44 +0000274 80, /* Down */
275 62, /* Menu (F4) */
276 -1,
277 66, /* Zoom- (F8) */
balrog1d4e5472008-05-09 22:16:11 +0000278 64, /* FullScreen (F6) */
balrog7e7c5e42008-04-14 21:57:44 +0000279 65, /* Zoom+ (F7) */
280 -1,
281};
282
balroge927bb02008-05-07 14:30:38 +0000283static void n800_tsc_kbd_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000284{
285 int i;
286
287 /* XXX: are the three pins inverted inside the chip between the
288 * tsc and the cpu (N4111)? */
Blue Swirlb9d38e92009-09-21 18:11:34 +0000289 qemu_irq penirq = NULL; /* NC */
Andreas Färber518ec132012-05-13 22:13:15 +0200290 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
291 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
balrog7e7c5e42008-04-14 21:57:44 +0000292
Paul Brook22d83b12009-05-12 12:33:04 +0100293 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
balroge927bb02008-05-07 14:30:38 +0000294 s->ts.opaque = s->ts.chip->opaque;
295 s->ts.txrx = tsc210x_txrx;
balrog7e7c5e42008-04-14 21:57:44 +0000296
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200297 for (i = 0; i < 0x80; i++) {
balrog7e7c5e42008-04-14 21:57:44 +0000298 s->keymap[i] = -1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200299 }
300 for (i = 0; i < 0x10; i++) {
301 if (n800_keys[i] >= 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000302 s->keymap[n800_keys[i]] = i;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200303 }
304 }
balrog7e7c5e42008-04-14 21:57:44 +0000305
306 qemu_add_kbd_event_handler(n800_key_event, s);
307
balroge927bb02008-05-07 14:30:38 +0000308 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
309}
310
311static void n810_tsc_setup(struct n800_s *s)
312{
Andreas Färber518ec132012-05-13 22:13:15 +0200313 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
balroge927bb02008-05-07 14:30:38 +0000314
315 s->ts.opaque = tsc2005_init(pintdav);
316 s->ts.txrx = tsc2005_txrx;
317
318 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
balrog7e7c5e42008-04-14 21:57:44 +0000319}
320
balrog1d4e5472008-05-09 22:16:11 +0000321/* N810 Keyboard controller */
322static void n810_key_event(void *opaque, int keycode)
323{
324 struct n800_s *s = (struct n800_s *) opaque;
325 int code = s->keymap[keycode & 0x7f];
326
327 if (code == -1) {
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200328 if ((keycode & 0x7f) == RETU_KEYCODE) {
balrog1d4e5472008-05-09 22:16:11 +0000329 retu_key_event(s->retu, !(keycode & 0x80));
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200330 }
balrog1d4e5472008-05-09 22:16:11 +0000331 return;
332 }
333
334 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
335}
336
337#define M 0
338
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +0100339static const int n810_keys[0x80] = {
balrog1d4e5472008-05-09 22:16:11 +0000340 [0x01] = 16, /* Q */
341 [0x02] = 37, /* K */
342 [0x03] = 24, /* O */
343 [0x04] = 25, /* P */
344 [0x05] = 14, /* Backspace */
345 [0x06] = 30, /* A */
346 [0x07] = 31, /* S */
347 [0x08] = 32, /* D */
348 [0x09] = 33, /* F */
349 [0x0a] = 34, /* G */
350 [0x0b] = 35, /* H */
351 [0x0c] = 36, /* J */
352
353 [0x11] = 17, /* W */
354 [0x12] = 62, /* Menu (F4) */
355 [0x13] = 38, /* L */
356 [0x14] = 40, /* ' (Apostrophe) */
357 [0x16] = 44, /* Z */
358 [0x17] = 45, /* X */
359 [0x18] = 46, /* C */
360 [0x19] = 47, /* V */
361 [0x1a] = 48, /* B */
362 [0x1b] = 49, /* N */
363 [0x1c] = 42, /* Shift (Left shift) */
364 [0x1f] = 65, /* Zoom+ (F7) */
365
366 [0x21] = 18, /* E */
367 [0x22] = 39, /* ; (Semicolon) */
368 [0x23] = 12, /* - (Minus) */
369 [0x24] = 13, /* = (Equal) */
370 [0x2b] = 56, /* Fn (Left Alt) */
371 [0x2c] = 50, /* M */
372 [0x2f] = 66, /* Zoom- (F8) */
373
374 [0x31] = 19, /* R */
375 [0x32] = 29 | M, /* Right Ctrl */
376 [0x34] = 57, /* Space */
377 [0x35] = 51, /* , (Comma) */
378 [0x37] = 72 | M, /* Up */
379 [0x3c] = 82 | M, /* Compose (Insert) */
380 [0x3f] = 64, /* FullScreen (F6) */
381
382 [0x41] = 20, /* T */
383 [0x44] = 52, /* . (Dot) */
384 [0x46] = 77 | M, /* Right */
385 [0x4f] = 63, /* Home (F5) */
386 [0x51] = 21, /* Y */
387 [0x53] = 80 | M, /* Down */
388 [0x55] = 28, /* Enter */
389 [0x5f] = 1, /* Cycle (ESC) */
390
391 [0x61] = 22, /* U */
392 [0x64] = 75 | M, /* Left */
393
394 [0x71] = 23, /* I */
395#if 0
396 [0x75] = 28 | M, /* KP Enter (KP Enter) */
397#else
398 [0x75] = 15, /* KP Enter (Tab) */
399#endif
400};
401
402#undef M
403
404static void n810_kbd_setup(struct n800_s *s)
405{
Andreas Färber518ec132012-05-13 22:13:15 +0200406 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
balrog1d4e5472008-05-09 22:16:11 +0000407 int i;
408
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200409 for (i = 0; i < 0x80; i++) {
balrog1d4e5472008-05-09 22:16:11 +0000410 s->keymap[i] = -1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200411 }
412 for (i = 0; i < 0x80; i++) {
413 if (n810_keys[i] > 0) {
balrog1d4e5472008-05-09 22:16:11 +0000414 s->keymap[n810_keys[i]] = i;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200415 }
416 }
balrog1d4e5472008-05-09 22:16:11 +0000417
418 qemu_add_kbd_event_handler(n810_key_event, s);
419
420 /* Attach the LM8322 keyboard to the I2C bus,
421 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
Philippe Mathieu-Daudé1373b152020-07-06 00:41:53 +0200422 s->kbd = DEVICE(i2c_slave_create_simple(omap_i2c_bus(s->mpu->i2c[0]),
Philippe Mathieu-Daudé426f53d2021-06-17 13:53:21 +0200423 TYPE_LM8323, N810_LM8323_ADDR));
Peter Maydellc4f05c82011-07-29 16:35:18 +0100424 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
balrog1d4e5472008-05-09 22:16:11 +0000425}
426
balrog7e7c5e42008-04-14 21:57:44 +0000427/* LCD MIPI DBI-C controller (URAL) */
428struct mipid_s {
429 int resp[4];
430 int param[4];
431 int p;
432 int pm;
433 int cmd;
434
435 int sleep;
436 int booster;
437 int te;
438 int selfcheck;
439 int partial;
440 int normal;
441 int vscr;
442 int invert;
443 int onoff;
444 int gamma;
445 uint32_t id;
446};
447
448static void mipid_reset(struct mipid_s *s)
449{
balrog7e7c5e42008-04-14 21:57:44 +0000450 s->pm = 0;
451 s->cmd = 0;
452
453 s->sleep = 1;
454 s->booster = 0;
455 s->selfcheck =
456 (1 << 7) | /* Register loading OK. */
457 (1 << 5) | /* The chip is attached. */
458 (1 << 4); /* Display glass still in one piece. */
459 s->te = 0;
460 s->partial = 0;
461 s->normal = 1;
462 s->vscr = 0;
463 s->invert = 0;
464 s->onoff = 1;
465 s->gamma = 0;
466}
467
balroge927bb02008-05-07 14:30:38 +0000468static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
balrog7e7c5e42008-04-14 21:57:44 +0000469{
470 struct mipid_s *s = (struct mipid_s *) opaque;
471 uint8_t ret;
472
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200473 if (len > 9) {
Alistair Francisa89f3642017-11-08 14:56:31 -0800474 hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200475 }
balroge927bb02008-05-07 14:30:38 +0000476
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200477 if (s->p >= ARRAY_SIZE(s->resp)) {
balrog7e7c5e42008-04-14 21:57:44 +0000478 ret = 0;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200479 } else {
480 ret = s->resp[s->p++];
481 }
482 if (s->pm-- > 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000483 s->param[s->pm] = cmd;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200484 } else {
balrog7e7c5e42008-04-14 21:57:44 +0000485 s->cmd = cmd;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200486 }
balrog7e7c5e42008-04-14 21:57:44 +0000487
488 switch (s->cmd) {
489 case 0x00: /* NOP */
490 break;
491
492 case 0x01: /* SWRESET */
493 mipid_reset(s);
494 break;
495
496 case 0x02: /* BSTROFF */
497 s->booster = 0;
498 break;
499 case 0x03: /* BSTRON */
500 s->booster = 1;
501 break;
502
503 case 0x04: /* RDDID */
504 s->p = 0;
505 s->resp[0] = (s->id >> 16) & 0xff;
506 s->resp[1] = (s->id >> 8) & 0xff;
507 s->resp[2] = (s->id >> 0) & 0xff;
508 break;
509
510 case 0x06: /* RD_RED */
511 case 0x07: /* RD_GREEN */
512 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
513 * for the bootloader one needs to change this. */
514 case 0x08: /* RD_BLUE */
515 s->p = 0;
516 /* TODO: return first pixel components */
517 s->resp[0] = 0x01;
518 break;
519
520 case 0x09: /* RDDST */
521 s->p = 0;
522 s->resp[0] = s->booster << 7;
523 s->resp[1] = (5 << 4) | (s->partial << 2) |
524 (s->sleep << 1) | s->normal;
525 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
526 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
527 s->resp[3] = s->gamma << 6;
528 break;
529
530 case 0x0a: /* RDDPM */
531 s->p = 0;
532 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
533 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
534 break;
535 case 0x0b: /* RDDMADCTR */
536 s->p = 0;
537 s->resp[0] = 0;
538 break;
539 case 0x0c: /* RDDCOLMOD */
540 s->p = 0;
541 s->resp[0] = 5; /* 65K colours */
542 break;
543 case 0x0d: /* RDDIM */
544 s->p = 0;
545 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
546 break;
547 case 0x0e: /* RDDSM */
548 s->p = 0;
549 s->resp[0] = s->te << 7;
550 break;
551 case 0x0f: /* RDDSDR */
552 s->p = 0;
553 s->resp[0] = s->selfcheck;
554 break;
555
556 case 0x10: /* SLPIN */
557 s->sleep = 1;
558 break;
559 case 0x11: /* SLPOUT */
560 s->sleep = 0;
561 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
562 break;
563
564 case 0x12: /* PTLON */
565 s->partial = 1;
566 s->normal = 0;
567 s->vscr = 0;
568 break;
569 case 0x13: /* NORON */
570 s->partial = 0;
571 s->normal = 1;
572 s->vscr = 0;
573 break;
574
575 case 0x20: /* INVOFF */
576 s->invert = 0;
577 break;
578 case 0x21: /* INVON */
579 s->invert = 1;
580 break;
581
582 case 0x22: /* APOFF */
583 case 0x23: /* APON */
584 goto bad_cmd;
585
586 case 0x25: /* WRCNTR */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200587 if (s->pm < 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000588 s->pm = 1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200589 }
balrog7e7c5e42008-04-14 21:57:44 +0000590 goto bad_cmd;
591
592 case 0x26: /* GAMSET */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200593 if (!s->pm) {
Stefan Hajnocziad5f5fd2015-03-23 15:29:24 +0000594 s->gamma = ctz32(s->param[0] & 0xf);
595 if (s->gamma == 32) {
596 s->gamma = -1; /* XXX: should this be 0? */
597 }
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200598 } else if (s->pm < 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000599 s->pm = 1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200600 }
balrog7e7c5e42008-04-14 21:57:44 +0000601 break;
602
603 case 0x28: /* DISPOFF */
604 s->onoff = 0;
balrog7e7c5e42008-04-14 21:57:44 +0000605 break;
606 case 0x29: /* DISPON */
607 s->onoff = 1;
balrog7e7c5e42008-04-14 21:57:44 +0000608 break;
609
610 case 0x2a: /* CASET */
611 case 0x2b: /* RASET */
612 case 0x2c: /* RAMWR */
613 case 0x2d: /* RGBSET */
614 case 0x2e: /* RAMRD */
615 case 0x30: /* PTLAR */
616 case 0x33: /* SCRLAR */
617 goto bad_cmd;
618
619 case 0x34: /* TEOFF */
620 s->te = 0;
621 break;
622 case 0x35: /* TEON */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200623 if (!s->pm) {
balrog7e7c5e42008-04-14 21:57:44 +0000624 s->te = 1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200625 } else if (s->pm < 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000626 s->pm = 1;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200627 }
balrog7e7c5e42008-04-14 21:57:44 +0000628 break;
629
630 case 0x36: /* MADCTR */
631 goto bad_cmd;
632
633 case 0x37: /* VSCSAD */
634 s->partial = 0;
635 s->normal = 0;
636 s->vscr = 1;
637 break;
638
639 case 0x38: /* IDMOFF */
640 case 0x39: /* IDMON */
641 case 0x3a: /* COLMOD */
642 goto bad_cmd;
643
644 case 0xb0: /* CLKINT / DISCTL */
645 case 0xb1: /* CLKEXT */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200646 if (s->pm < 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000647 s->pm = 2;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200648 }
balrog7e7c5e42008-04-14 21:57:44 +0000649 break;
650
651 case 0xb4: /* FRMSEL */
652 break;
653
654 case 0xb5: /* FRM8SEL */
655 case 0xb6: /* TMPRNG / INIESC */
656 case 0xb7: /* TMPHIS / NOP2 */
657 case 0xb8: /* TMPREAD / MADCTL */
658 case 0xba: /* DISTCTR */
659 case 0xbb: /* EPVOL */
660 goto bad_cmd;
661
662 case 0xbd: /* Unknown */
663 s->p = 0;
664 s->resp[0] = 0;
665 s->resp[1] = 1;
666 break;
667
668 case 0xc2: /* IFMOD */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200669 if (s->pm < 0) {
balrog7e7c5e42008-04-14 21:57:44 +0000670 s->pm = 2;
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200671 }
balrog7e7c5e42008-04-14 21:57:44 +0000672 break;
673
674 case 0xc6: /* PWRCTL */
675 case 0xc7: /* PPWRCTL */
676 case 0xd0: /* EPWROUT */
677 case 0xd1: /* EPWRIN */
678 case 0xd4: /* RDEV */
679 case 0xd5: /* RDRR */
680 goto bad_cmd;
681
682 case 0xda: /* RDID1 */
683 s->p = 0;
684 s->resp[0] = (s->id >> 16) & 0xff;
685 break;
686 case 0xdb: /* RDID2 */
687 s->p = 0;
688 s->resp[0] = (s->id >> 8) & 0xff;
689 break;
690 case 0xdc: /* RDID3 */
691 s->p = 0;
692 s->resp[0] = (s->id >> 0) & 0xff;
693 break;
694
695 default:
696 bad_cmd:
Peter Maydell591f73f2013-04-05 16:17:58 +0100697 qemu_log_mask(LOG_GUEST_ERROR,
Philippe Mathieu-Daudéb1c2a6b2021-07-26 17:09:53 +0200698 "%s: unknown command 0x%02x\n", __func__, s->cmd);
balrog7e7c5e42008-04-14 21:57:44 +0000699 break;
700 }
701
702 return ret;
703}
704
705static void *mipid_init(void)
706{
Markus Armbruster0a553c12022-09-23 14:00:24 +0200707 struct mipid_s *s = g_malloc0(sizeof(*s));
balrog7e7c5e42008-04-14 21:57:44 +0000708
709 s->id = 0x838f03;
710 mipid_reset(s);
711
712 return s;
713}
714
balroge927bb02008-05-07 14:30:38 +0000715static void n8x0_spi_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000716{
balroge927bb02008-05-07 14:30:38 +0000717 void *tsc = s->ts.opaque;
balrog7e7c5e42008-04-14 21:57:44 +0000718 void *mipid = mipid_init();
719
Andreas Färber518ec132012-05-13 22:13:15 +0200720 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
721 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
balrog7e7c5e42008-04-14 21:57:44 +0000722}
723
724/* This task is normally performed by the bootloader. If we're loading
725 * a kernel directly, we need to enable the Blizzard ourselves. */
726static void n800_dss_init(struct rfbi_chip_s *chip)
727{
728 uint8_t *fb_blank;
729
730 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
731 chip->write(chip->opaque, 1, 0x64);
732 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
733 chip->write(chip->opaque, 1, 0x1e);
734 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
735 chip->write(chip->opaque, 1, 0xe0);
736 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
737 chip->write(chip->opaque, 1, 0x01);
738 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
739 chip->write(chip->opaque, 1, 0x06);
740 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
741 chip->write(chip->opaque, 1, 1); /* Enable bit */
742
743 chip->write(chip->opaque, 0, 0x6c);
744 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
745 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
746 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
747 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
748 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
749 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
750 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
751 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
752 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
753 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
754 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
755 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
756 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
757 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
758 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
759 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
760 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
761 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
762
Anthony Liguori7267c092011-08-20 22:09:37 -0500763 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
balrog7e7c5e42008-04-14 21:57:44 +0000764 /* Display Memory Data Port */
765 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
Anthony Liguori7267c092011-08-20 22:09:37 -0500766 g_free(fb_blank);
balrog7e7c5e42008-04-14 21:57:44 +0000767}
768
aliguori3023f332009-01-16 19:04:14 +0000769static void n8x0_dss_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000770{
Blue Swirlb9d38e92009-09-21 18:11:34 +0000771 s->blizzard.opaque = s1d13745_init(NULL);
balrog7e7c5e42008-04-14 21:57:44 +0000772 s->blizzard.block = s1d13745_write_block;
773 s->blizzard.write = s1d13745_write;
774 s->blizzard.read = s1d13745_read;
775
Andreas Färber518ec132012-05-13 22:13:15 +0200776 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
balrog7e7c5e42008-04-14 21:57:44 +0000777}
778
balroge927bb02008-05-07 14:30:38 +0000779static void n8x0_cbus_setup(struct n800_s *s)
balrog7e7c5e42008-04-14 21:57:44 +0000780{
Andreas Färber518ec132012-05-13 22:13:15 +0200781 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
782 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
783 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
balrog7e7c5e42008-04-14 21:57:44 +0000784
Paul Brookbc24a222009-05-10 01:44:56 +0100785 CBus *cbus = cbus_init(dat_out);
balrog7e7c5e42008-04-14 21:57:44 +0000786
Andreas Färber518ec132012-05-13 22:13:15 +0200787 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
788 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
789 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
balrog7e7c5e42008-04-14 21:57:44 +0000790
791 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
792 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
793}
794
balroge927bb02008-05-07 14:30:38 +0000795static void n8x0_usb_setup(struct n800_s *s)
balrog942ac052008-04-22 03:15:10 +0000796{
Peter Maydellbdc76462011-08-30 18:36:56 +0100797 SysBusDevice *dev;
Markus Armbruster3e80f692020-06-10 07:31:58 +0200798 s->usb = qdev_new("tusb6010");
Andreas Färber1356b982013-01-20 02:47:33 +0100799 dev = SYS_BUS_DEVICE(s->usb);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200800 sysbus_realize_and_unref(dev, &error_fatal);
Peter Maydellbdc76462011-08-30 18:36:56 +0100801 sysbus_connect_irq(dev, 0,
Andreas Färber518ec132012-05-13 22:13:15 +0200802 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
balrog942ac052008-04-22 03:15:10 +0000803 /* Using the NOR interface */
Andreas Färber518ec132012-05-13 22:13:15 +0200804 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
Peter Maydellbdc76462011-08-30 18:36:56 +0100805 sysbus_mmio_get_region(dev, 0));
Andreas Färber518ec132012-05-13 22:13:15 +0200806 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
Peter Maydellbdc76462011-08-30 18:36:56 +0100807 sysbus_mmio_get_region(dev, 1));
Andreas Färber518ec132012-05-13 22:13:15 +0200808 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
Peter Maydellbdc76462011-08-30 18:36:56 +0100809 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
balrog942ac052008-04-22 03:15:10 +0000810}
811
balrogd238db72008-05-18 13:58:19 +0000812/* Setup done before the main bootloader starts by some early setup code
813 * - used when we want to run the main bootloader in emulation. This
814 * isn't documented. */
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +0100815static const uint32_t n800_pinout[104] = {
balrogd238db72008-05-18 13:58:19 +0000816 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
817 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
818 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
819 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
820 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
821 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
822 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
823 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
824 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
825 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
826 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
827 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
828 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
829 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
830 0x00000000, 0x00000038, 0x00340000, 0x00000000,
831 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
832 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
833 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
834 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
835 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
836 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
837 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
838 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
839 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
840 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
841 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
842};
843
844static void n800_setup_nolo_tags(void *sram_base)
845{
846 int i;
847 uint32_t *p = sram_base + 0x8000;
848 uint32_t *v = sram_base + 0xa000;
849
850 memset(p, 0, 0x3000);
851
852 strcpy((void *) (p + 0), "QEMU N800");
853
854 strcpy((void *) (p + 8), "F5");
855
Paolo Bonzini09839792014-03-28 18:43:14 +0100856 stl_p(p + 10, 0x04f70000);
balrogd238db72008-05-18 13:58:19 +0000857 strcpy((void *) (p + 9), "RX-34");
858
859 /* RAM size in MB? */
Paolo Bonzini09839792014-03-28 18:43:14 +0100860 stl_p(p + 12, 0x80);
balrogd238db72008-05-18 13:58:19 +0000861
862 /* Pointer to the list of tags */
Paolo Bonzini09839792014-03-28 18:43:14 +0100863 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
balrogd238db72008-05-18 13:58:19 +0000864
865 /* The NOLO tags start here */
866 p = sram_base + 0x9000;
867#define ADD_TAG(tag, len) \
Paolo Bonzini09839792014-03-28 18:43:14 +0100868 stw_p((uint16_t *) p + 0, tag); \
869 stw_p((uint16_t *) p + 1, len); p++; \
870 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
balrogd238db72008-05-18 13:58:19 +0000871
872 /* OMAP STI console? Pin out settings? */
873 ADD_TAG(0x6e01, 414);
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200874 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
Paolo Bonzini09839792014-03-28 18:43:14 +0100875 stl_p(v++, n800_pinout[i]);
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200876 }
balrogd238db72008-05-18 13:58:19 +0000877
878 /* Kernel memsize? */
879 ADD_TAG(0x6e05, 1);
Paolo Bonzini09839792014-03-28 18:43:14 +0100880 stl_p(v++, 2);
balrogd238db72008-05-18 13:58:19 +0000881
882 /* NOLO serial console */
883 ADD_TAG(0x6e02, 4);
Paolo Bonzini09839792014-03-28 18:43:14 +0100884 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */
balrogd238db72008-05-18 13:58:19 +0000885
886#if 0
887 /* CBUS settings (Retu/AVilma) */
888 ADD_TAG(0x6e03, 6);
Paolo Bonzini09839792014-03-28 18:43:14 +0100889 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
890 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
891 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
balrogd238db72008-05-18 13:58:19 +0000892 v += 2;
893#endif
894
895 /* Nokia ASIC BB5 (Retu/Tahvo) */
896 ADD_TAG(0x6e0a, 4);
Paolo Bonzini09839792014-03-28 18:43:14 +0100897 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
898 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200899 v++;
balrogd238db72008-05-18 13:58:19 +0000900
901 /* LCD console? */
902 ADD_TAG(0x6e04, 4);
Paolo Bonzini09839792014-03-28 18:43:14 +0100903 stw_p((uint16_t *) v + 0, 30); /* ??? */
904 stw_p((uint16_t *) v + 1, 24); /* ??? */
Paolo Bonzinifddbd802014-05-12 10:03:05 +0200905 v++;
balrogd238db72008-05-18 13:58:19 +0000906
907#if 0
908 /* LCD settings */
909 ADD_TAG(0x6e06, 2);
Paolo Bonzini09839792014-03-28 18:43:14 +0100910 stw_p((uint16_t *) (v++), 15); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000911#endif
912
913 /* I^2C (Menelaus) */
914 ADD_TAG(0x6e07, 4);
Paolo Bonzini09839792014-03-28 18:43:14 +0100915 stl_p(v++, 0x00720000); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000916
917 /* Unknown */
918 ADD_TAG(0x6e0b, 6);
Paolo Bonzini09839792014-03-28 18:43:14 +0100919 stw_p((uint16_t *) v + 0, 94); /* ??? */
920 stw_p((uint16_t *) v + 1, 23); /* ??? */
921 stw_p((uint16_t *) v + 2, 0); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000922 v += 2;
923
924 /* OMAP gpio switch info */
925 ADD_TAG(0x6e0c, 80);
926 strcpy((void *) v, "bat_cover"); v += 3;
Paolo Bonzini09839792014-03-28 18:43:14 +0100927 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */
928 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */
balrogd238db72008-05-18 13:58:19 +0000929 v += 2;
930 strcpy((void *) v, "cam_act"); v += 3;
Paolo Bonzini09839792014-03-28 18:43:14 +0100931 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */
932 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */
balrogd238db72008-05-18 13:58:19 +0000933 v += 2;
934 strcpy((void *) v, "cam_turn"); v += 3;
Paolo Bonzini09839792014-03-28 18:43:14 +0100935 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */
936 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */
balrogd238db72008-05-18 13:58:19 +0000937 v += 2;
938 strcpy((void *) v, "headphone"); v += 3;
Paolo Bonzini09839792014-03-28 18:43:14 +0100939 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */
940 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */
balrogd238db72008-05-18 13:58:19 +0000941 v += 2;
942
943 /* Bluetooth */
944 ADD_TAG(0x6e0e, 12);
Paolo Bonzini09839792014-03-28 18:43:14 +0100945 stl_p(v++, 0x5c623d01); /* ??? */
946 stl_p(v++, 0x00000201); /* ??? */
947 stl_p(v++, 0x00000000); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000948
949 /* CX3110x WLAN settings */
950 ADD_TAG(0x6e0f, 8);
Paolo Bonzini09839792014-03-28 18:43:14 +0100951 stl_p(v++, 0x00610025); /* ??? */
952 stl_p(v++, 0xffff0057); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000953
954 /* MMC host settings */
955 ADD_TAG(0x6e10, 12);
Paolo Bonzini09839792014-03-28 18:43:14 +0100956 stl_p(v++, 0xffff000f); /* ??? */
957 stl_p(v++, 0xffffffff); /* ??? */
958 stl_p(v++, 0x00000060); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000959
960 /* OneNAND chip select */
961 ADD_TAG(0x6e11, 10);
Paolo Bonzini09839792014-03-28 18:43:14 +0100962 stl_p(v++, 0x00000401); /* ??? */
963 stl_p(v++, 0x0002003a); /* ??? */
964 stl_p(v++, 0x00000002); /* ??? */
balrogd238db72008-05-18 13:58:19 +0000965
966 /* TEA5761 sensor settings */
967 ADD_TAG(0x6e12, 2);
Paolo Bonzini09839792014-03-28 18:43:14 +0100968 stl_p(v++, 93); /* GPIO num ??? */
balrogd238db72008-05-18 13:58:19 +0000969
970#if 0
971 /* Unknown tag */
972 ADD_TAG(6e09, 0);
973
974 /* Kernel UART / console */
975 ADD_TAG(6e12, 0);
976#endif
977
978 /* End of the list */
Paolo Bonzini09839792014-03-28 18:43:14 +0100979 stl_p(p++, 0x00000000);
980 stl_p(p++, 0x00000000);
balrogd238db72008-05-18 13:58:19 +0000981}
982
balrog7e7c5e42008-04-14 21:57:44 +0000983/* This task is normally performed by the bootloader. If we're loading
984 * a kernel directly, we need to set up GPMC mappings ourselves. */
985static void n800_gpmc_init(struct n800_s *s)
986{
987 uint32_t config7 =
988 (0xf << 8) | /* MASKADDRESS */
989 (1 << 6) | /* CSVALID */
990 (4 << 0); /* BASEADDRESS */
991
992 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
Stefan Weile1fe50d2013-04-12 20:53:58 +0200993 &config7, sizeof(config7));
balrog7e7c5e42008-04-14 21:57:44 +0000994}
995
996/* Setup sequence done by the bootloader */
balroge927bb02008-05-07 14:30:38 +0000997static void n8x0_boot_init(void *opaque)
balrog7e7c5e42008-04-14 21:57:44 +0000998{
999 struct n800_s *s = (struct n800_s *) opaque;
1000 uint32_t buf;
1001
1002 /* PRCM setup */
1003#define omap_writel(addr, val) \
1004 buf = (val); \
Stefan Weile1fe50d2013-04-12 20:53:58 +02001005 cpu_physical_memory_write(addr, &buf, sizeof(buf))
balrog7e7c5e42008-04-14 21:57:44 +00001006
1007 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1008 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1009 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1010 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1011 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1012 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1013 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1014 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1015 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1016 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1017 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1018 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1019 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1020 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1021 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1022 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1023 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1024 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1025 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1026 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1027 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1028 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1029 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1030 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1031 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1032 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1033 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1034 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1035 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1036 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1037 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1038 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1039 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1040 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1041 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1042 (0x78 << 12) | (6 << 8));
1043 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1044
1045 /* GPMC setup */
1046 n800_gpmc_init(s);
1047
1048 /* Video setup */
1049 n800_dss_init(&s->blizzard);
1050
1051 /* CPU setup */
Andreas Färber518ec132012-05-13 22:13:15 +02001052 s->mpu->cpu->env.GE = 0x5;
balrog09410412008-05-18 13:14:29 +00001053
1054 /* If the machine has a slided keyboard, open it */
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001055 if (s->kbd) {
Andreas Färber518ec132012-05-13 22:13:15 +02001056 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001057 }
balrog7e7c5e42008-04-14 21:57:44 +00001058}
1059
1060#define OMAP_TAG_NOKIA_BT 0x4e01
1061#define OMAP_TAG_WLAN_CX3110X 0x4e02
1062#define OMAP_TAG_CBUS 0x4e03
1063#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1064
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +01001065static const struct omap_gpiosw_info_s {
balroge927bb02008-05-07 14:30:38 +00001066 const char *name;
1067 int line;
1068 int type;
1069} n800_gpiosw_info[] = {
1070 {
1071 "bat_cover", N800_BAT_COVER_GPIO,
1072 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1073 }, {
1074 "cam_act", N800_CAM_ACT_GPIO,
1075 OMAP_GPIOSW_TYPE_ACTIVITY,
1076 }, {
1077 "cam_turn", N800_CAM_TURN_GPIO,
1078 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1079 }, {
1080 "headphone", N8X0_HEADPHONE_GPIO,
1081 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1082 },
Philippe Mathieu-Daudé6aee3402022-12-20 15:25:20 +01001083 { /* end of list */ }
balroge927bb02008-05-07 14:30:38 +00001084}, n810_gpiosw_info[] = {
1085 {
1086 "gps_reset", N810_GPS_RESET_GPIO,
1087 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1088 }, {
1089 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1090 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1091 }, {
1092 "headphone", N8X0_HEADPHONE_GPIO,
1093 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1094 }, {
1095 "kb_lock", N810_KB_LOCK_GPIO,
1096 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1097 }, {
1098 "sleepx_led", N810_SLEEPX_LED_GPIO,
1099 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1100 }, {
1101 "slide", N810_SLIDE_GPIO,
1102 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1103 },
Philippe Mathieu-Daudé6aee3402022-12-20 15:25:20 +01001104 { /* end of list */ }
balroge927bb02008-05-07 14:30:38 +00001105};
1106
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +01001107static const struct omap_partition_info_s {
balroge927bb02008-05-07 14:30:38 +00001108 uint32_t offset;
1109 uint32_t size;
1110 int mask;
1111 const char *name;
1112} n800_part_info[] = {
1113 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1114 { 0x00020000, 0x00060000, 0x0, "config" },
1115 { 0x00080000, 0x00200000, 0x0, "kernel" },
1116 { 0x00280000, 0x00200000, 0x3, "initfs" },
1117 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
Philippe Mathieu-Daudé6aee3402022-12-20 15:25:20 +01001118 { /* end of list */ }
balroge927bb02008-05-07 14:30:38 +00001119}, n810_part_info[] = {
1120 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1121 { 0x00020000, 0x00060000, 0x0, "config" },
1122 { 0x00080000, 0x00220000, 0x0, "kernel" },
1123 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1124 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
Philippe Mathieu-Daudé6aee3402022-12-20 15:25:20 +01001125 { /* end of list */ }
balroge927bb02008-05-07 14:30:38 +00001126};
1127
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +01001128static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
balrogc580d922008-07-29 14:19:16 +00001129
balroge927bb02008-05-07 14:30:38 +00001130static int n8x0_atag_setup(void *p, int model)
balrog7e7c5e42008-04-14 21:57:44 +00001131{
1132 uint8_t *b;
1133 uint16_t *w;
1134 uint32_t *l;
Philippe Mathieu-Daudébd8d01b2022-12-20 15:25:19 +01001135 const struct omap_gpiosw_info_s *gpiosw;
1136 const struct omap_partition_info_s *partition;
balroge927bb02008-05-07 14:30:38 +00001137 const char *tag;
balrog7e7c5e42008-04-14 21:57:44 +00001138
1139 w = p;
1140
Paolo Bonzini09839792014-03-28 18:43:14 +01001141 stw_p(w++, OMAP_TAG_UART); /* u16 tag */
1142 stw_p(w++, 4); /* u16 len */
1143 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001144 w++;
balrog7e7c5e42008-04-14 21:57:44 +00001145
balroge927bb02008-05-07 14:30:38 +00001146#if 0
Paolo Bonzini09839792014-03-28 18:43:14 +01001147 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1148 stw_p(w++, 4); /* u16 len */
1149 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */
1150 stw_p(w++, 115200); /* u32 console_speed */
balroge927bb02008-05-07 14:30:38 +00001151#endif
1152
Paolo Bonzini09839792014-03-28 18:43:14 +01001153 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */
1154 stw_p(w++, 36); /* u16 len */
balroge927bb02008-05-07 14:30:38 +00001155 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1156 w += 8;
1157 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1158 w += 8;
Paolo Bonzini09839792014-03-28 18:43:14 +01001159 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1160 stw_p(w++, 24); /* u8 data_lines */
balrog7e7c5e42008-04-14 21:57:44 +00001161
Paolo Bonzini09839792014-03-28 18:43:14 +01001162 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */
1163 stw_p(w++, 8); /* u16 len */
1164 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1165 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1166 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001167 w++;
balrog7e7c5e42008-04-14 21:57:44 +00001168
Paolo Bonzini09839792014-03-28 18:43:14 +01001169 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1170 stw_p(w++, 4); /* u16 len */
1171 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1172 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
balrog7e7c5e42008-04-14 21:57:44 +00001173
balroge927bb02008-05-07 14:30:38 +00001174 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001175 for (; gpiosw->name; gpiosw++) {
Paolo Bonzini09839792014-03-28 18:43:14 +01001176 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1177 stw_p(w++, 20); /* u16 len */
balroge927bb02008-05-07 14:30:38 +00001178 strcpy((void *) w, gpiosw->name); /* char name[12] */
1179 w += 6;
Paolo Bonzini09839792014-03-28 18:43:14 +01001180 stw_p(w++, gpiosw->line); /* u16 gpio */
1181 stw_p(w++, gpiosw->type);
1182 stw_p(w++, 0);
1183 stw_p(w++, 0);
balroge927bb02008-05-07 14:30:38 +00001184 }
balrog7e7c5e42008-04-14 21:57:44 +00001185
Paolo Bonzini09839792014-03-28 18:43:14 +01001186 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1187 stw_p(w++, 12); /* u16 len */
balrog7e7c5e42008-04-14 21:57:44 +00001188 b = (void *) w;
Paolo Bonzini09839792014-03-28 18:43:14 +01001189 stb_p(b++, 0x01); /* u8 chip_type (CSR) */
1190 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1191 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1192 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1193 stb_p(b++, BT_UART + 1); /* u8 bt_uart */
balrogc580d922008-07-29 14:19:16 +00001194 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
balrog7e7c5e42008-04-14 21:57:44 +00001195 b += 6;
Paolo Bonzini09839792014-03-28 18:43:14 +01001196 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */
balrog7e7c5e42008-04-14 21:57:44 +00001197 w = (void *) b;
1198
Paolo Bonzini09839792014-03-28 18:43:14 +01001199 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1200 stw_p(w++, 8); /* u16 len */
1201 stw_p(w++, 0x25); /* u8 chip_type */
1202 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1203 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1204 stw_p(w++, -1); /* s16 spi_cs_gpio */
balrog7e7c5e42008-04-14 21:57:44 +00001205
Paolo Bonzini09839792014-03-28 18:43:14 +01001206 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */
1207 stw_p(w++, 16); /* u16 len */
balroge927bb02008-05-07 14:30:38 +00001208 if (model == 810) {
Paolo Bonzini09839792014-03-28 18:43:14 +01001209 stw_p(w++, 0x23f); /* unsigned flags */
1210 stw_p(w++, -1); /* s16 power_pin */
1211 stw_p(w++, -1); /* s16 switch_pin */
1212 stw_p(w++, -1); /* s16 wp_pin */
1213 stw_p(w++, 0x240); /* unsigned flags */
1214 stw_p(w++, 0xc000); /* s16 power_pin */
1215 stw_p(w++, 0x0248); /* s16 switch_pin */
1216 stw_p(w++, 0xc000); /* s16 wp_pin */
balroge927bb02008-05-07 14:30:38 +00001217 } else {
Paolo Bonzini09839792014-03-28 18:43:14 +01001218 stw_p(w++, 0xf); /* unsigned flags */
1219 stw_p(w++, -1); /* s16 power_pin */
1220 stw_p(w++, -1); /* s16 switch_pin */
1221 stw_p(w++, -1); /* s16 wp_pin */
1222 stw_p(w++, 0); /* unsigned flags */
1223 stw_p(w++, 0); /* s16 power_pin */
1224 stw_p(w++, 0); /* s16 switch_pin */
1225 stw_p(w++, 0); /* s16 wp_pin */
balroge927bb02008-05-07 14:30:38 +00001226 }
balrog7e7c5e42008-04-14 21:57:44 +00001227
Paolo Bonzini09839792014-03-28 18:43:14 +01001228 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */
1229 stw_p(w++, 4); /* u16 len */
1230 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001231 w++;
balrog7e7c5e42008-04-14 21:57:44 +00001232
balroge927bb02008-05-07 14:30:38 +00001233 partition = (model == 810) ? n810_part_info : n800_part_info;
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001234 for (; partition->name; partition++) {
Paolo Bonzini09839792014-03-28 18:43:14 +01001235 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */
1236 stw_p(w++, 28); /* u16 len */
balroge927bb02008-05-07 14:30:38 +00001237 strcpy((void *) w, partition->name); /* char name[16] */
1238 l = (void *) (w + 8);
Paolo Bonzini09839792014-03-28 18:43:14 +01001239 stl_p(l++, partition->size); /* unsigned int size */
1240 stl_p(l++, partition->offset); /* unsigned int offset */
1241 stl_p(l++, partition->mask); /* unsigned int mask_flags */
balroge927bb02008-05-07 14:30:38 +00001242 w = (void *) l;
1243 }
balrog7e7c5e42008-04-14 21:57:44 +00001244
Paolo Bonzini09839792014-03-28 18:43:14 +01001245 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1246 stw_p(w++, 12); /* u16 len */
balrog7e7c5e42008-04-14 21:57:44 +00001247#if 0
1248 strcpy((void *) w, "por"); /* char reason_str[12] */
1249 strcpy((void *) w, "charger"); /* char reason_str[12] */
1250 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1251 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1252 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1253 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1254 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1255 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1256 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1257 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1258#else
1259 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1260#endif
1261 w += 6;
1262
balroge927bb02008-05-07 14:30:38 +00001263 tag = (model == 810) ? "RX-44" : "RX-34";
Paolo Bonzini09839792014-03-28 18:43:14 +01001264 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1265 stw_p(w++, 24); /* u16 len */
balrog7e7c5e42008-04-14 21:57:44 +00001266 strcpy((void *) w, "product"); /* char component[12] */
1267 w += 6;
balroge927bb02008-05-07 14:30:38 +00001268 strcpy((void *) w, tag); /* char version[12] */
balrog7e7c5e42008-04-14 21:57:44 +00001269 w += 6;
1270
Paolo Bonzini09839792014-03-28 18:43:14 +01001271 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1272 stw_p(w++, 24); /* u16 len */
balrog7e7c5e42008-04-14 21:57:44 +00001273 strcpy((void *) w, "hw-build"); /* char component[12] */
1274 w += 6;
Crístian Viana93bfef42012-05-30 00:35:51 -03001275 strcpy((void *) w, "QEMU ");
Eduardo Habkost35c2c8d2015-10-30 17:36:08 -02001276 pstrcat((void *) w, 12, qemu_hw_version()); /* char version[12] */
balrog7e7c5e42008-04-14 21:57:44 +00001277 w += 6;
1278
balroge927bb02008-05-07 14:30:38 +00001279 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
Paolo Bonzini09839792014-03-28 18:43:14 +01001280 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1281 stw_p(w++, 24); /* u16 len */
balrog7e7c5e42008-04-14 21:57:44 +00001282 strcpy((void *) w, "nolo"); /* char component[12] */
1283 w += 6;
balroge927bb02008-05-07 14:30:38 +00001284 strcpy((void *) w, tag); /* char version[12] */
balrog7e7c5e42008-04-14 21:57:44 +00001285 w += 6;
balrog7e7c5e42008-04-14 21:57:44 +00001286
1287 return (void *) w - p;
1288}
1289
Stefan Weil462a8bc2011-06-23 17:53:48 +02001290static int n800_atag_setup(const struct arm_boot_info *info, void *p)
balroge927bb02008-05-07 14:30:38 +00001291{
1292 return n8x0_atag_setup(p, 800);
1293}
balrog7e7c5e42008-04-14 21:57:44 +00001294
Stefan Weil462a8bc2011-06-23 17:53:48 +02001295static int n810_atag_setup(const struct arm_boot_info *info, void *p)
balroge927bb02008-05-07 14:30:38 +00001296{
1297 return n8x0_atag_setup(p, 810);
1298}
1299
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +03001300static void n8x0_init(MachineState *machine,
Peter Maydell462b69b2012-10-30 07:45:08 +00001301 struct arm_boot_info *binfo, int model)
balrog7e7c5e42008-04-14 21:57:44 +00001302{
Markus Armbruster0a553c12022-09-23 14:00:24 +02001303 struct n800_s *s = g_malloc0(sizeof(*s));
Igor Mammedov7998beb2020-02-19 11:08:59 -05001304 MachineClass *mc = MACHINE_GET_CLASS(machine);
balrog7e7c5e42008-04-14 21:57:44 +00001305
Igor Mammedov7998beb2020-02-19 11:08:59 -05001306 if (machine->ram_size != mc->default_ram_size) {
1307 char *sz = size_to_str(mc->default_ram_size);
1308 error_report("Invalid RAM size, should be %s", sz);
1309 g_free(sz);
1310 exit(EXIT_FAILURE);
1311 }
Philippe Mathieu-Daudéb3267ff2020-10-19 11:51:48 +02001312 binfo->ram_size = machine->ram_size;
Philippe Mathieu-Daudée285e862019-10-22 16:50:38 +01001313
Igor Mammedov7998beb2020-02-19 11:08:59 -05001314 memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
1315 machine->ram);
1316
1317 s->mpu = omap2420_mpu_init(machine->ram, machine->cpu_type);
balrog7e7c5e42008-04-14 21:57:44 +00001318
balrog09410412008-05-18 13:14:29 +00001319 /* Setup peripherals
1320 *
1321 * Believed external peripherals layout in the N810:
1322 * (spi bus 1)
1323 * tsc2005
1324 * lcd_mipid
1325 * (spi bus 2)
1326 * Conexant cx3110x (WLAN)
1327 * optional: pc2400m (WiMAX)
1328 * (i2c bus 0)
1329 * TLV320AIC33 (audio codec)
1330 * TCM825x (camera by Toshiba)
1331 * lp5521 (clever LEDs)
1332 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1333 * lm8323 (keypad, manf 00, rev 04)
1334 * (i2c bus 1)
1335 * tmp105 (temperature sensor, hwmon)
1336 * menelaus (pm)
balrogd238db72008-05-18 13:58:19 +00001337 * (somewhere on i2c - maybe N800-only)
1338 * tea5761 (FM tuner)
1339 * (serial 0)
1340 * GPS
1341 * (some serial port)
1342 * csr41814 (Bluetooth)
balrog09410412008-05-18 13:14:29 +00001343 */
balroge927bb02008-05-07 14:30:38 +00001344 n8x0_gpio_setup(s);
balrog7e7c5e42008-04-14 21:57:44 +00001345 n8x0_nand_setup(s);
balroge927bb02008-05-07 14:30:38 +00001346 n8x0_i2c_setup(s);
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001347 if (model == 800) {
balroge927bb02008-05-07 14:30:38 +00001348 n800_tsc_kbd_setup(s);
Paolo Bonzinifddbd802014-05-12 10:03:05 +02001349 } else if (model == 810) {
balroge927bb02008-05-07 14:30:38 +00001350 n810_tsc_setup(s);
balrog1d4e5472008-05-09 22:16:11 +00001351 n810_kbd_setup(s);
1352 }
balroge927bb02008-05-07 14:30:38 +00001353 n8x0_spi_setup(s);
aliguori3023f332009-01-16 19:04:14 +00001354 n8x0_dss_setup(s);
balroge927bb02008-05-07 14:30:38 +00001355 n8x0_cbus_setup(s);
Eduardo Habkost4bcbe0b2016-06-08 17:50:25 -03001356 if (machine_usb(machine)) {
balroge927bb02008-05-07 14:30:38 +00001357 n8x0_usb_setup(s);
zhlcindy@gmail.com094b2872012-09-02 19:25:28 +00001358 }
balrog7e7c5e42008-04-14 21:57:44 +00001359
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +03001360 if (machine->kernel_filename) {
balrog7e7c5e42008-04-14 21:57:44 +00001361 /* Or at the linux loader. */
Tao Xu2744ece2019-08-09 14:57:21 +08001362 arm_load_kernel(s->mpu->cpu, machine, binfo);
balrog7e7c5e42008-04-14 21:57:44 +00001363
Jan Kiszkaa08d4362009-06-27 09:25:07 +02001364 qemu_register_reset(n8x0_boot_init, s);
balrog7e7c5e42008-04-14 21:57:44 +00001365 }
1366
Peter Maydell462b69b2012-10-30 07:45:08 +00001367 if (option_rom[0].name &&
Paolo Bonzini97ec4d22022-04-14 12:52:56 -04001368 (machine->boot_config.order[0] == 'n' || !machine->kernel_filename)) {
Zhou Jie0b062eb2016-05-12 13:22:25 +01001369 uint8_t *nolo_tags = g_new(uint8_t, 0x10000);
balrogd238db72008-05-18 13:58:19 +00001370 /* No, wait, better start at the ROM. */
Andreas Färber518ec132012-05-13 22:13:15 +02001371 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
balrogd238db72008-05-18 13:58:19 +00001372
Peter Maydell0e5dc772020-11-03 11:49:18 +00001373 /*
1374 * This is intended for loading the `secondary.bin' program from
balrogd238db72008-05-18 13:58:19 +00001375 * Nokia images (the NOLO bootloader). The entry point seems
1376 * to be at OMAP2_Q2_BASE + 0x400000.
1377 *
1378 * The `2nd.bin' files contain some kind of earlier boot code and
1379 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1380 *
1381 * The code above is for loading the `zImage' file from Nokia
Peter Maydell0e5dc772020-11-03 11:49:18 +00001382 * images.
1383 */
1384 if (load_image_targphys(option_rom[0].name,
1385 OMAP2_Q2_BASE + 0x400000,
1386 machine->ram_size - 0x400000) < 0) {
1387 error_report("Failed to load secondary bootloader %s",
1388 option_rom[0].name);
1389 exit(EXIT_FAILURE);
1390 }
balrogd238db72008-05-18 13:58:19 +00001391
pbrook5c130f62009-04-10 14:29:45 +00001392 n800_setup_nolo_tags(nolo_tags);
1393 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
Zhou Jie0b062eb2016-05-12 13:22:25 +01001394 g_free(nolo_tags);
balrogd238db72008-05-18 13:58:19 +00001395 }
balrog7e7c5e42008-04-14 21:57:44 +00001396}
1397
balroge927bb02008-05-07 14:30:38 +00001398static struct arm_boot_info n800_binfo = {
1399 .loader_start = OMAP2_Q2_BASE,
balroge927bb02008-05-07 14:30:38 +00001400 .board_id = 0x4f7,
1401 .atag_board = n800_atag_setup,
1402};
1403
1404static struct arm_boot_info n810_binfo = {
1405 .loader_start = OMAP2_Q2_BASE,
balroge927bb02008-05-07 14:30:38 +00001406 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1407 * used by some older versions of the bootloader and 5555 is used
1408 * instead (including versions that shipped with many devices). */
1409 .board_id = 0x60c,
1410 .atag_board = n810_atag_setup,
1411};
1412
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +03001413static void n800_init(MachineState *machine)
balroge927bb02008-05-07 14:30:38 +00001414{
Stefan Weil30d76f12015-03-08 19:22:48 +01001415 n8x0_init(machine, &n800_binfo, 800);
balroge927bb02008-05-07 14:30:38 +00001416}
1417
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +03001418static void n810_init(MachineState *machine)
balroge927bb02008-05-07 14:30:38 +00001419{
Stefan Weil30d76f12015-03-08 19:22:48 +01001420 n8x0_init(machine, &n810_binfo, 810);
balroge927bb02008-05-07 14:30:38 +00001421}
1422
Andreas Färber8a661ae2015-09-19 10:49:44 +02001423static void n800_class_init(ObjectClass *oc, void *data)
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001424{
Andreas Färber8a661ae2015-09-19 10:49:44 +02001425 MachineClass *mc = MACHINE_CLASS(oc);
1426
Eduardo Habkoste264d292015-09-04 15:37:08 -03001427 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1428 mc->init = n800_init;
1429 mc->default_boot_order = "";
Peter Maydell4672cbd2017-09-07 13:54:54 +01001430 mc->ignore_memory_transaction_failures = true;
Igor Mammedovba1ba5c2017-09-13 18:04:57 +02001431 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
Igor Mammedov7998beb2020-02-19 11:08:59 -05001432 /* Actually two chips of 0x4000000 bytes each */
1433 mc->default_ram_size = 0x08000000;
1434 mc->default_ram_id = "omap2.dram";
Martin Kletzanderb8ab0302023-09-22 17:21:39 +02001435
1436 machine_add_audiodev_property(mc);
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001437}
1438
Andreas Färber8a661ae2015-09-19 10:49:44 +02001439static const TypeInfo n800_type = {
1440 .name = MACHINE_TYPE_NAME("n800"),
1441 .parent = TYPE_MACHINE,
1442 .class_init = n800_class_init,
1443};
Eduardo Habkoste264d292015-09-04 15:37:08 -03001444
Andreas Färber8a661ae2015-09-19 10:49:44 +02001445static void n810_class_init(ObjectClass *oc, void *data)
Eduardo Habkoste264d292015-09-04 15:37:08 -03001446{
Andreas Färber8a661ae2015-09-19 10:49:44 +02001447 MachineClass *mc = MACHINE_CLASS(oc);
1448
Eduardo Habkoste264d292015-09-04 15:37:08 -03001449 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1450 mc->init = n810_init;
1451 mc->default_boot_order = "";
Peter Maydell4672cbd2017-09-07 13:54:54 +01001452 mc->ignore_memory_transaction_failures = true;
Igor Mammedovba1ba5c2017-09-13 18:04:57 +02001453 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2");
Igor Mammedov7998beb2020-02-19 11:08:59 -05001454 /* Actually two chips of 0x4000000 bytes each */
1455 mc->default_ram_size = 0x08000000;
1456 mc->default_ram_id = "omap2.dram";
Martin Kletzanderb8ab0302023-09-22 17:21:39 +02001457
1458 machine_add_audiodev_property(mc);
Eduardo Habkoste264d292015-09-04 15:37:08 -03001459}
1460
Andreas Färber8a661ae2015-09-19 10:49:44 +02001461static const TypeInfo n810_type = {
1462 .name = MACHINE_TYPE_NAME("n810"),
1463 .parent = TYPE_MACHINE,
1464 .class_init = n810_class_init,
1465};
1466
1467static void nseries_machine_init(void)
1468{
1469 type_register_static(&n800_type);
1470 type_register_static(&n810_type);
1471}
1472
Eduardo Habkost0e6aac82016-02-16 18:59:04 -02001473type_init(nseries_machine_init)