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bellardc896fe22008-02-01 10:05:41 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020024
25/*
26 * DEF(name, oargs, iargs, cargs, flags)
27 */
bellardc896fe22008-02-01 10:05:41 +000028
29/* predefined ops */
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020030DEF(end, 0, 0, 0, 0) /* must be kept first */
31DEF(nop, 0, 0, 0, 0)
32DEF(nop1, 0, 0, 1, 0)
33DEF(nop2, 0, 0, 2, 0)
34DEF(nop3, 0, 0, 3, 0)
35DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
bellardc896fe22008-02-01 10:05:41 +000036
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020037DEF(discard, 1, 0, 0, 0)
bellard5ff9d6a2008-02-04 00:37:54 +000038
Aurelien Jarno332864b2012-09-10 14:23:49 +020039DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
Aurelien Jarno344028b2012-10-09 21:53:08 +020040DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
41DEF(br, 0, 0, 1, TCG_OPF_BB_END)
bellardc896fe22008-02-01 10:05:41 +000042
Richard Henderson25c4d9c2011-08-17 14:11:46 -070043#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
44#if TCG_TARGET_REG_BITS == 32
45# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
46#else
47# define IMPL64 TCG_OPF_64BIT
48#endif
49
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020050DEF(mov_i32, 1, 1, 0, 0)
51DEF(movi_i32, 1, 0, 1, 0)
52DEF(setcond_i32, 1, 2, 1, 0)
Richard Hendersonffc5ea02012-09-21 10:13:34 -070053DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
bellardc896fe22008-02-01 10:05:41 +000054/* load/store */
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020055DEF(ld8u_i32, 1, 1, 1, 0)
56DEF(ld8s_i32, 1, 1, 1, 0)
57DEF(ld16u_i32, 1, 1, 1, 0)
58DEF(ld16s_i32, 1, 1, 1, 0)
59DEF(ld_i32, 1, 1, 1, 0)
Aurelien Jarnob202d412012-10-09 21:53:08 +020060DEF(st8_i32, 0, 2, 1, 0)
61DEF(st16_i32, 0, 2, 1, 0)
62DEF(st_i32, 0, 2, 1, 0)
bellardc896fe22008-02-01 10:05:41 +000063/* arith */
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020064DEF(add_i32, 1, 2, 0, 0)
65DEF(sub_i32, 1, 2, 0, 0)
66DEF(mul_i32, 1, 2, 0, 0)
Richard Henderson25c4d9c2011-08-17 14:11:46 -070067DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
68DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
69DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
70DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
71DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
72DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020073DEF(and_i32, 1, 2, 0, 0)
74DEF(or_i32, 1, 2, 0, 0)
75DEF(xor_i32, 1, 2, 0, 0)
aurel32d42f1832009-03-09 18:50:53 +000076/* shifts/rotates */
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +020077DEF(shl_i32, 1, 2, 0, 0)
78DEF(shr_i32, 1, 2, 0, 0)
79DEF(sar_i32, 1, 2, 0, 0)
Richard Henderson25c4d9c2011-08-17 14:11:46 -070080DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
81DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
82DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
bellardc896fe22008-02-01 10:05:41 +000083
Aurelien Jarno344028b2012-10-09 21:53:08 +020084DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
bellardc896fe22008-02-01 10:05:41 +000085
Richard Hendersone6a72732013-02-19 23:51:49 -080086DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
87DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
88DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
Richard Henderson4d3203f2013-02-19 23:51:53 -080089DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
Aurelien Jarno344028b2012-10-09 21:53:08 +020090DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
Richard Henderson25c4d9c2011-08-17 14:11:46 -070091DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
92
93DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
94DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
95DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
96DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
97DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
98DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
99DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
100DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
101DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
102DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
103DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
104DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
105DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
106
107DEF(mov_i64, 1, 1, 0, IMPL64)
108DEF(movi_i64, 1, 0, 1, IMPL64)
109DEF(setcond_i64, 1, 2, 1, IMPL64)
Richard Hendersonffc5ea02012-09-21 10:13:34 -0700110DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
bellardc896fe22008-02-01 10:05:41 +0000111/* load/store */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700112DEF(ld8u_i64, 1, 1, 1, IMPL64)
113DEF(ld8s_i64, 1, 1, 1, IMPL64)
114DEF(ld16u_i64, 1, 1, 1, IMPL64)
115DEF(ld16s_i64, 1, 1, 1, IMPL64)
116DEF(ld32u_i64, 1, 1, 1, IMPL64)
117DEF(ld32s_i64, 1, 1, 1, IMPL64)
118DEF(ld_i64, 1, 1, 1, IMPL64)
Aurelien Jarnob202d412012-10-09 21:53:08 +0200119DEF(st8_i64, 0, 2, 1, IMPL64)
120DEF(st16_i64, 0, 2, 1, IMPL64)
121DEF(st32_i64, 0, 2, 1, IMPL64)
122DEF(st_i64, 0, 2, 1, IMPL64)
bellardc896fe22008-02-01 10:05:41 +0000123/* arith */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700124DEF(add_i64, 1, 2, 0, IMPL64)
125DEF(sub_i64, 1, 2, 0, IMPL64)
126DEF(mul_i64, 1, 2, 0, IMPL64)
127DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
128DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
129DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
130DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
131DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
132DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
133DEF(and_i64, 1, 2, 0, IMPL64)
134DEF(or_i64, 1, 2, 0, IMPL64)
135DEF(xor_i64, 1, 2, 0, IMPL64)
aurel32d42f1832009-03-09 18:50:53 +0000136/* shifts/rotates */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700137DEF(shl_i64, 1, 2, 0, IMPL64)
138DEF(shr_i64, 1, 2, 0, IMPL64)
139DEF(sar_i64, 1, 2, 0, IMPL64)
140DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
141DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
142DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
bellardc896fe22008-02-01 10:05:41 +0000143
Aurelien Jarno344028b2012-10-09 21:53:08 +0200144DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700145DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
146DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
147DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
148DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
149DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
150DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
151DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
152DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
153DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
154DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
155DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
156DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
157DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
158DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
159DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
160DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
bellardc896fe22008-02-01 10:05:41 +0000161
Richard Hendersond7156f72013-02-19 23:51:52 -0800162DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
163DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
164DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
Richard Henderson4d3203f2013-02-19 23:51:53 -0800165DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
Richard Hendersond7156f72013-02-19 23:51:52 -0800166
bellardc896fe22008-02-01 10:05:41 +0000167/* QEMU specific */
bellard7e4597d2008-05-22 16:56:05 +0000168#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200169DEF(debug_insn_start, 0, 0, 2, 0)
bellard7e4597d2008-05-22 16:56:05 +0000170#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200171DEF(debug_insn_start, 0, 0, 1, 0)
bellard7e4597d2008-05-22 16:56:05 +0000172#endif
Aurelien Jarno344028b2012-10-09 21:53:08 +0200173DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
174DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
bellardc896fe22008-02-01 10:05:41 +0000175/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
176 constants must be defined */
177#if TCG_TARGET_REG_BITS == 32
178#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200179DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000180#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200181DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000182#endif
183#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200184DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000185#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200186DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000187#endif
188#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200189DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000190#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200191DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000192#endif
193#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200194DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000195#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200196DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000197#endif
198#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200199DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000200#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200201DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000202#endif
203#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200204DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000205#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200206DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000207#endif
208
209#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200210DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000211#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200212DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000213#endif
214#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200215DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000216#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200217DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000218#endif
219#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200220DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000221#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200222DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000223#endif
224#if TARGET_LONG_BITS == 32
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200225DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000226#else
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200227DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000228#endif
229
230#else /* TCG_TARGET_REG_BITS == 32 */
231
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200232DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
233DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
234DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
235DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
236DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
237DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
238DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
239DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000240
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200241DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
242DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
243DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
244DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
bellardc896fe22008-02-01 10:05:41 +0000245
246#endif /* TCG_TARGET_REG_BITS != 32 */
247
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700248#undef IMPL
249#undef IMPL64
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200250#undef DEF