bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PPC emulation for qemu: main translation routines. |
| 3 | * |
| 4 | * Copyright (c) 2003 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
bellard | c6a1c22 | 2004-05-20 13:10:49 +0000 | [diff] [blame] | 20 | #include <stdarg.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <stdio.h> |
| 23 | #include <string.h> |
| 24 | #include <inttypes.h> |
| 25 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 26 | #include "cpu.h" |
bellard | c6a1c22 | 2004-05-20 13:10:49 +0000 | [diff] [blame] | 27 | #include "exec-all.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 28 | #include "disas.h" |
| 29 | |
| 30 | //#define DO_SINGLE_STEP |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 31 | //#define PPC_DEBUG_DISAS |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 32 | |
| 33 | enum { |
| 34 | #define DEF(s, n, copy_size) INDEX_op_ ## s, |
| 35 | #include "opc.h" |
| 36 | #undef DEF |
| 37 | NB_OPS, |
| 38 | }; |
| 39 | |
| 40 | static uint16_t *gen_opc_ptr; |
| 41 | static uint32_t *gen_opparam_ptr; |
| 42 | |
| 43 | #include "gen-op.h" |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 44 | |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 45 | #define GEN8(func, NAME) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 46 | static GenOpFunc *NAME ## _table [8] = { \ |
| 47 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
| 48 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
| 49 | }; \ |
| 50 | static inline void func(int n) \ |
| 51 | { \ |
| 52 | NAME ## _table[n](); \ |
| 53 | } |
| 54 | |
| 55 | #define GEN16(func, NAME) \ |
| 56 | static GenOpFunc *NAME ## _table [16] = { \ |
| 57 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
| 58 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
| 59 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
| 60 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
| 61 | }; \ |
| 62 | static inline void func(int n) \ |
| 63 | { \ |
| 64 | NAME ## _table[n](); \ |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | #define GEN32(func, NAME) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 68 | static GenOpFunc *NAME ## _table [32] = { \ |
| 69 | NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
| 70 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
| 71 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
| 72 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
| 73 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
| 74 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
| 75 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
| 76 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
| 77 | }; \ |
| 78 | static inline void func(int n) \ |
| 79 | { \ |
| 80 | NAME ## _table[n](); \ |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 81 | } |
| 82 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 83 | /* Condition register moves */ |
| 84 | GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf); |
| 85 | GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf); |
| 86 | GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); |
| 87 | GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 88 | |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 89 | /* Floating point condition and status register moves */ |
| 90 | GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr); |
| 91 | GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr); |
| 92 | GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr); |
| 93 | static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = { |
| 94 | &gen_op_store_T0_fpscri_fpscr0, |
| 95 | &gen_op_store_T0_fpscri_fpscr1, |
| 96 | &gen_op_store_T0_fpscri_fpscr2, |
| 97 | &gen_op_store_T0_fpscri_fpscr3, |
| 98 | &gen_op_store_T0_fpscri_fpscr4, |
| 99 | &gen_op_store_T0_fpscri_fpscr5, |
| 100 | &gen_op_store_T0_fpscri_fpscr6, |
| 101 | &gen_op_store_T0_fpscri_fpscr7, |
| 102 | }; |
| 103 | static inline void gen_op_store_T0_fpscri(int n, uint8_t param) |
| 104 | { |
| 105 | (*gen_op_store_T0_fpscri_fpscr_table[n])(param); |
| 106 | } |
| 107 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 108 | /* Segment register moves */ |
| 109 | GEN16(gen_op_load_sr, gen_op_load_sr); |
| 110 | GEN16(gen_op_store_sr, gen_op_store_sr); |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 111 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 112 | /* General purpose registers moves */ |
| 113 | GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); |
| 114 | GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); |
| 115 | GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); |
| 116 | |
| 117 | GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); |
| 118 | GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); |
| 119 | GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr); |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 120 | |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 121 | /* floating point registers moves */ |
| 122 | GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); |
| 123 | GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); |
| 124 | GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); |
| 125 | GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); |
| 126 | GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); |
| 127 | GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 128 | |
| 129 | static uint8_t spr_access[1024 / 2]; |
| 130 | |
| 131 | /* internal defines */ |
| 132 | typedef struct DisasContext { |
| 133 | struct TranslationBlock *tb; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 134 | target_ulong nip; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 135 | uint32_t opcode; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 136 | uint32_t exception; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 137 | /* Execution mode */ |
| 138 | #if !defined(CONFIG_USER_ONLY) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 139 | int supervisor; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 140 | #endif |
| 141 | /* Routine used to access memory */ |
| 142 | int mem_idx; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 143 | } DisasContext; |
| 144 | |
| 145 | typedef struct opc_handler_t { |
| 146 | /* invalid bits */ |
| 147 | uint32_t inval; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 148 | /* instruction type */ |
| 149 | uint32_t type; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 150 | /* handler */ |
| 151 | void (*handler)(DisasContext *ctx); |
| 152 | } opc_handler_t; |
| 153 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 154 | #define RET_EXCP(ctx, excp, error) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 155 | do { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 156 | if ((ctx)->exception == EXCP_NONE) { \ |
| 157 | gen_op_update_nip((ctx)->nip); \ |
| 158 | } \ |
| 159 | gen_op_raise_exception_err((excp), (error)); \ |
| 160 | ctx->exception = (excp); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 161 | } while (0) |
| 162 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 163 | #define RET_INVAL(ctx) \ |
| 164 | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 165 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 166 | #define RET_PRIVOPC(ctx) \ |
| 167 | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 168 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 169 | #define RET_PRIVREG(ctx) \ |
| 170 | RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG) |
| 171 | |
| 172 | #define RET_MTMSR(ctx) \ |
| 173 | RET_EXCP((ctx), EXCP_MTMSR, 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 174 | |
| 175 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
| 176 | static void gen_##name (DisasContext *ctx); \ |
| 177 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \ |
| 178 | static void gen_##name (DisasContext *ctx) |
| 179 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 180 | typedef struct opcode_t { |
| 181 | unsigned char opc1, opc2, opc3; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 182 | opc_handler_t handler; |
| 183 | } opcode_t; |
| 184 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 185 | /*** Instruction decoding ***/ |
| 186 | #define EXTRACT_HELPER(name, shift, nb) \ |
| 187 | static inline uint32_t name (uint32_t opcode) \ |
| 188 | { \ |
| 189 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
| 190 | } |
| 191 | |
| 192 | #define EXTRACT_SHELPER(name, shift, nb) \ |
| 193 | static inline int32_t name (uint32_t opcode) \ |
| 194 | { \ |
| 195 | return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
| 196 | } |
| 197 | |
| 198 | /* Opcode part 1 */ |
| 199 | EXTRACT_HELPER(opc1, 26, 6); |
| 200 | /* Opcode part 2 */ |
| 201 | EXTRACT_HELPER(opc2, 1, 5); |
| 202 | /* Opcode part 3 */ |
| 203 | EXTRACT_HELPER(opc3, 6, 5); |
| 204 | /* Update Cr0 flags */ |
| 205 | EXTRACT_HELPER(Rc, 0, 1); |
| 206 | /* Destination */ |
| 207 | EXTRACT_HELPER(rD, 21, 5); |
| 208 | /* Source */ |
| 209 | EXTRACT_HELPER(rS, 21, 5); |
| 210 | /* First operand */ |
| 211 | EXTRACT_HELPER(rA, 16, 5); |
| 212 | /* Second operand */ |
| 213 | EXTRACT_HELPER(rB, 11, 5); |
| 214 | /* Third operand */ |
| 215 | EXTRACT_HELPER(rC, 6, 5); |
| 216 | /*** Get CRn ***/ |
| 217 | EXTRACT_HELPER(crfD, 23, 3); |
| 218 | EXTRACT_HELPER(crfS, 18, 3); |
| 219 | EXTRACT_HELPER(crbD, 21, 5); |
| 220 | EXTRACT_HELPER(crbA, 16, 5); |
| 221 | EXTRACT_HELPER(crbB, 11, 5); |
| 222 | /* SPR / TBL */ |
| 223 | EXTRACT_HELPER(SPR, 11, 10); |
| 224 | /*** Get constants ***/ |
| 225 | EXTRACT_HELPER(IMM, 12, 8); |
| 226 | /* 16 bits signed immediate value */ |
| 227 | EXTRACT_SHELPER(SIMM, 0, 16); |
| 228 | /* 16 bits unsigned immediate value */ |
| 229 | EXTRACT_HELPER(UIMM, 0, 16); |
| 230 | /* Bit count */ |
| 231 | EXTRACT_HELPER(NB, 11, 5); |
| 232 | /* Shift count */ |
| 233 | EXTRACT_HELPER(SH, 11, 5); |
| 234 | /* Mask start */ |
| 235 | EXTRACT_HELPER(MB, 6, 5); |
| 236 | /* Mask end */ |
| 237 | EXTRACT_HELPER(ME, 1, 5); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 238 | /* Trap operand */ |
| 239 | EXTRACT_HELPER(TO, 21, 5); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 240 | |
| 241 | EXTRACT_HELPER(CRM, 12, 8); |
| 242 | EXTRACT_HELPER(FM, 17, 8); |
| 243 | EXTRACT_HELPER(SR, 16, 4); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 244 | EXTRACT_HELPER(FPIMM, 20, 4); |
| 245 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 246 | /*** Jump target decoding ***/ |
| 247 | /* Displacement */ |
| 248 | EXTRACT_SHELPER(d, 0, 16); |
| 249 | /* Immediate address */ |
| 250 | static inline uint32_t LI (uint32_t opcode) |
| 251 | { |
| 252 | return (opcode >> 0) & 0x03FFFFFC; |
| 253 | } |
| 254 | |
| 255 | static inline uint32_t BD (uint32_t opcode) |
| 256 | { |
| 257 | return (opcode >> 0) & 0xFFFC; |
| 258 | } |
| 259 | |
| 260 | EXTRACT_HELPER(BO, 21, 5); |
| 261 | EXTRACT_HELPER(BI, 16, 5); |
| 262 | /* Absolute/relative address */ |
| 263 | EXTRACT_HELPER(AA, 1, 1); |
| 264 | /* Link */ |
| 265 | EXTRACT_HELPER(LK, 0, 1); |
| 266 | |
| 267 | /* Create a mask between <start> and <end> bits */ |
| 268 | static inline uint32_t MASK (uint32_t start, uint32_t end) |
| 269 | { |
| 270 | uint32_t ret; |
| 271 | |
| 272 | ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1); |
| 273 | if (start > end) |
| 274 | return ~ret; |
| 275 | |
| 276 | return ret; |
| 277 | } |
| 278 | |
bellard | 1b039c0 | 2004-07-12 18:39:45 +0000 | [diff] [blame] | 279 | #if defined(__APPLE__) |
| 280 | #define OPCODES_SECTION \ |
| 281 | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (8) )) |
| 282 | #else |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 283 | #define OPCODES_SECTION \ |
| 284 | __attribute__ ((section(".opcodes"), unused, aligned (8) )) |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 285 | #endif |
| 286 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 287 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 288 | OPCODES_SECTION static opcode_t opc_##name = { \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 289 | .opc1 = op1, \ |
| 290 | .opc2 = op2, \ |
| 291 | .opc3 = op3, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 292 | .handler = { \ |
| 293 | .inval = invl, \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 294 | .type = _typ, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 295 | .handler = &gen_##name, \ |
| 296 | }, \ |
| 297 | } |
| 298 | |
| 299 | #define GEN_OPCODE_MARK(name) \ |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 300 | OPCODES_SECTION static opcode_t opc_##name = { \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 301 | .opc1 = 0xFF, \ |
| 302 | .opc2 = 0xFF, \ |
| 303 | .opc3 = 0xFF, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 304 | .handler = { \ |
| 305 | .inval = 0x00000000, \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 306 | .type = 0x00, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 307 | .handler = NULL, \ |
| 308 | }, \ |
| 309 | } |
| 310 | |
| 311 | /* Start opcode list */ |
| 312 | GEN_OPCODE_MARK(start); |
| 313 | |
| 314 | /* Invalid instruction */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 315 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 316 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 317 | RET_INVAL(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | /* Special opcode to stop emulation */ |
| 321 | GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON) |
| 322 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 323 | RET_EXCP(ctx, EXCP_HLT, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | /* Special opcode to call open-firmware */ |
| 327 | GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON) |
| 328 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 329 | RET_EXCP(ctx, EXCP_OFCALL, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 330 | } |
| 331 | |
| 332 | /* Special opcode to call RTAS */ |
| 333 | GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON) |
| 334 | { |
| 335 | printf("RTAS entry point !\n"); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 336 | RET_EXCP(ctx, EXCP_RTASCALL, 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | static opc_handler_t invalid_handler = { |
| 340 | .inval = 0xFFFFFFFF, |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 341 | .type = PPC_NONE, |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 342 | .handler = gen_invalid, |
| 343 | }; |
| 344 | |
| 345 | /*** Integer arithmetic ***/ |
| 346 | #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \ |
| 347 | GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
| 348 | { \ |
| 349 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 350 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
| 351 | gen_op_##name(); \ |
| 352 | if (Rc(ctx->opcode) != 0) \ |
| 353 | gen_op_set_Rc0(); \ |
| 354 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \ |
| 358 | GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \ |
| 359 | { \ |
| 360 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 361 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
| 362 | gen_op_##name(); \ |
| 363 | if (Rc(ctx->opcode) != 0) \ |
| 364 | gen_op_set_Rc0_ov(); \ |
| 365 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \ |
| 369 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \ |
| 370 | { \ |
| 371 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 372 | gen_op_##name(); \ |
| 373 | if (Rc(ctx->opcode) != 0) \ |
| 374 | gen_op_set_Rc0(); \ |
| 375 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 376 | } |
| 377 | #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \ |
| 378 | GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \ |
| 379 | { \ |
| 380 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 381 | gen_op_##name(); \ |
| 382 | if (Rc(ctx->opcode) != 0) \ |
| 383 | gen_op_set_Rc0_ov(); \ |
| 384 | gen_op_store_T0_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 385 | } |
| 386 | |
| 387 | /* Two operands arithmetic functions */ |
| 388 | #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \ |
| 389 | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \ |
| 390 | __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000) |
| 391 | |
| 392 | /* Two operands arithmetic functions with no overflow allowed */ |
| 393 | #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \ |
| 394 | __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400) |
| 395 | |
| 396 | /* One operand arithmetic functions */ |
| 397 | #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \ |
| 398 | __GEN_INT_ARITH1(name, opc1, opc2, opc3) \ |
| 399 | __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10) |
| 400 | |
| 401 | /* add add. addo addo. */ |
| 402 | GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08); |
| 403 | /* addc addc. addco addco. */ |
| 404 | GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00); |
| 405 | /* adde adde. addeo addeo. */ |
| 406 | GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04); |
| 407 | /* addme addme. addmeo addmeo. */ |
| 408 | GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07); |
| 409 | /* addze addze. addzeo addzeo. */ |
| 410 | GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06); |
| 411 | /* divw divw. divwo divwo. */ |
| 412 | GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F); |
| 413 | /* divwu divwu. divwuo divwuo. */ |
| 414 | GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E); |
| 415 | /* mulhw mulhw. */ |
| 416 | GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02); |
| 417 | /* mulhwu mulhwu. */ |
| 418 | GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00); |
| 419 | /* mullw mullw. mullwo mullwo. */ |
| 420 | GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07); |
| 421 | /* neg neg. nego nego. */ |
| 422 | GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03); |
| 423 | /* subf subf. subfo subfo. */ |
| 424 | GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01); |
| 425 | /* subfc subfc. subfco subfco. */ |
| 426 | GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00); |
| 427 | /* subfe subfe. subfeo subfeo. */ |
| 428 | GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04); |
| 429 | /* subfme subfme. subfmeo subfmeo. */ |
| 430 | GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07); |
| 431 | /* subfze subfze. subfzeo subfzeo. */ |
| 432 | GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06); |
| 433 | /* addi */ |
| 434 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 435 | { |
| 436 | int32_t simm = SIMM(ctx->opcode); |
| 437 | |
| 438 | if (rA(ctx->opcode) == 0) { |
| 439 | gen_op_set_T0(simm); |
| 440 | } else { |
| 441 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 442 | gen_op_addi(simm); |
| 443 | } |
| 444 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 445 | } |
| 446 | /* addic */ |
| 447 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 448 | { |
| 449 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 450 | gen_op_addic(SIMM(ctx->opcode)); |
| 451 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 452 | } |
| 453 | /* addic. */ |
| 454 | GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 455 | { |
| 456 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 457 | gen_op_addic(SIMM(ctx->opcode)); |
| 458 | gen_op_set_Rc0(); |
| 459 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 460 | } |
| 461 | /* addis */ |
| 462 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 463 | { |
| 464 | int32_t simm = SIMM(ctx->opcode); |
| 465 | |
| 466 | if (rA(ctx->opcode) == 0) { |
| 467 | gen_op_set_T0(simm << 16); |
| 468 | } else { |
| 469 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 470 | gen_op_addi(simm << 16); |
| 471 | } |
| 472 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 473 | } |
| 474 | /* mulli */ |
| 475 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 476 | { |
| 477 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 478 | gen_op_mulli(SIMM(ctx->opcode)); |
| 479 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 480 | } |
| 481 | /* subfic */ |
| 482 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 483 | { |
| 484 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 485 | gen_op_subfic(SIMM(ctx->opcode)); |
| 486 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | /*** Integer comparison ***/ |
| 490 | #define GEN_CMP(name, opc) \ |
| 491 | GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \ |
| 492 | { \ |
| 493 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 494 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
| 495 | gen_op_##name(); \ |
| 496 | gen_op_store_T0_crf(crfD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | /* cmp */ |
| 500 | GEN_CMP(cmp, 0x00); |
| 501 | /* cmpi */ |
| 502 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
| 503 | { |
| 504 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 505 | gen_op_cmpi(SIMM(ctx->opcode)); |
| 506 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 507 | } |
| 508 | /* cmpl */ |
| 509 | GEN_CMP(cmpl, 0x01); |
| 510 | /* cmpli */ |
| 511 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) |
| 512 | { |
| 513 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 514 | gen_op_cmpli(UIMM(ctx->opcode)); |
| 515 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | /*** Integer logical ***/ |
| 519 | #define __GEN_LOGICAL2(name, opc2, opc3) \ |
| 520 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \ |
| 521 | { \ |
| 522 | gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
| 523 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
| 524 | gen_op_##name(); \ |
| 525 | if (Rc(ctx->opcode) != 0) \ |
| 526 | gen_op_set_Rc0(); \ |
| 527 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 528 | } |
| 529 | #define GEN_LOGICAL2(name, opc) \ |
| 530 | __GEN_LOGICAL2(name, 0x1C, opc) |
| 531 | |
| 532 | #define GEN_LOGICAL1(name, opc) \ |
| 533 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \ |
| 534 | { \ |
| 535 | gen_op_load_gpr_T0(rS(ctx->opcode)); \ |
| 536 | gen_op_##name(); \ |
| 537 | if (Rc(ctx->opcode) != 0) \ |
| 538 | gen_op_set_Rc0(); \ |
| 539 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 540 | } |
| 541 | |
| 542 | /* and & and. */ |
| 543 | GEN_LOGICAL2(and, 0x00); |
| 544 | /* andc & andc. */ |
| 545 | GEN_LOGICAL2(andc, 0x01); |
| 546 | /* andi. */ |
| 547 | GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 548 | { |
| 549 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 550 | gen_op_andi_(UIMM(ctx->opcode)); |
| 551 | gen_op_set_Rc0(); |
| 552 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 553 | } |
| 554 | /* andis. */ |
| 555 | GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 556 | { |
| 557 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 558 | gen_op_andi_(UIMM(ctx->opcode) << 16); |
| 559 | gen_op_set_Rc0(); |
| 560 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | /* cntlzw */ |
| 564 | GEN_LOGICAL1(cntlzw, 0x00); |
| 565 | /* eqv & eqv. */ |
| 566 | GEN_LOGICAL2(eqv, 0x08); |
| 567 | /* extsb & extsb. */ |
| 568 | GEN_LOGICAL1(extsb, 0x1D); |
| 569 | /* extsh & extsh. */ |
| 570 | GEN_LOGICAL1(extsh, 0x1C); |
| 571 | /* nand & nand. */ |
| 572 | GEN_LOGICAL2(nand, 0x0E); |
| 573 | /* nor & nor. */ |
| 574 | GEN_LOGICAL2(nor, 0x03); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 575 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 576 | /* or & or. */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 577 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) |
| 578 | { |
| 579 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 580 | /* Optimisation for mr case */ |
| 581 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
| 582 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 583 | gen_op_or(); |
| 584 | } |
| 585 | if (Rc(ctx->opcode) != 0) |
| 586 | gen_op_set_Rc0(); |
| 587 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
| 588 | } |
| 589 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 590 | /* orc & orc. */ |
| 591 | GEN_LOGICAL2(orc, 0x0C); |
| 592 | /* xor & xor. */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 593 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) |
| 594 | { |
| 595 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 596 | /* Optimisation for "set to zero" case */ |
| 597 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
| 598 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 599 | gen_op_xor(); |
| 600 | } else { |
| 601 | gen_op_set_T0(0); |
| 602 | } |
| 603 | if (Rc(ctx->opcode) != 0) |
| 604 | gen_op_set_Rc0(); |
| 605 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
| 606 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 607 | /* ori */ |
| 608 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 609 | { |
| 610 | uint32_t uimm = UIMM(ctx->opcode); |
| 611 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 612 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 613 | /* NOP */ |
| 614 | return; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 615 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 616 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 617 | if (uimm != 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 618 | gen_op_ori(uimm); |
| 619 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 620 | } |
| 621 | /* oris */ |
| 622 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 623 | { |
| 624 | uint32_t uimm = UIMM(ctx->opcode); |
| 625 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 626 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 627 | /* NOP */ |
| 628 | return; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 629 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 630 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 631 | if (uimm != 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 632 | gen_op_ori(uimm << 16); |
| 633 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 634 | } |
| 635 | /* xori */ |
| 636 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 637 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 638 | uint32_t uimm = UIMM(ctx->opcode); |
| 639 | |
| 640 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 641 | /* NOP */ |
| 642 | return; |
| 643 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 644 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 645 | if (uimm != 0) |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 646 | gen_op_xori(uimm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 647 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | /* xoris */ |
| 651 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 652 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 653 | uint32_t uimm = UIMM(ctx->opcode); |
| 654 | |
| 655 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 656 | /* NOP */ |
| 657 | return; |
| 658 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 659 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 660 | if (uimm != 0) |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 661 | gen_op_xori(uimm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 662 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | /*** Integer rotate ***/ |
| 666 | /* rlwimi & rlwimi. */ |
| 667 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 668 | { |
| 669 | uint32_t mb, me; |
| 670 | |
| 671 | mb = MB(ctx->opcode); |
| 672 | me = ME(ctx->opcode); |
| 673 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 674 | gen_op_load_gpr_T1(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 675 | gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me)); |
| 676 | if (Rc(ctx->opcode) != 0) |
| 677 | gen_op_set_Rc0(); |
| 678 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 679 | } |
| 680 | /* rlwinm & rlwinm. */ |
| 681 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 682 | { |
| 683 | uint32_t mb, me, sh; |
| 684 | |
| 685 | sh = SH(ctx->opcode); |
| 686 | mb = MB(ctx->opcode); |
| 687 | me = ME(ctx->opcode); |
| 688 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 689 | #if 1 // TRY |
| 690 | if (sh == 0) { |
| 691 | gen_op_andi_(MASK(mb, me)); |
| 692 | goto store; |
| 693 | } |
| 694 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 695 | if (mb == 0) { |
| 696 | if (me == 31) { |
| 697 | gen_op_rotlwi(sh); |
| 698 | goto store; |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 699 | #if 0 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 700 | } else if (me == (31 - sh)) { |
| 701 | gen_op_slwi(sh); |
| 702 | goto store; |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 703 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 704 | } |
| 705 | } else if (me == 31) { |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 706 | #if 0 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 707 | if (sh == (32 - mb)) { |
| 708 | gen_op_srwi(mb); |
| 709 | goto store; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 710 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 711 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 712 | } |
| 713 | gen_op_rlwinm(sh, MASK(mb, me)); |
| 714 | store: |
| 715 | if (Rc(ctx->opcode) != 0) |
| 716 | gen_op_set_Rc0(); |
| 717 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 718 | } |
| 719 | /* rlwnm & rlwnm. */ |
| 720 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 721 | { |
| 722 | uint32_t mb, me; |
| 723 | |
| 724 | mb = MB(ctx->opcode); |
| 725 | me = ME(ctx->opcode); |
| 726 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 727 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 728 | if (mb == 0 && me == 31) { |
| 729 | gen_op_rotl(); |
| 730 | } else |
| 731 | { |
| 732 | gen_op_rlwnm(MASK(mb, me)); |
| 733 | } |
| 734 | if (Rc(ctx->opcode) != 0) |
| 735 | gen_op_set_Rc0(); |
| 736 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | /*** Integer shift ***/ |
| 740 | /* slw & slw. */ |
| 741 | __GEN_LOGICAL2(slw, 0x18, 0x00); |
| 742 | /* sraw & sraw. */ |
| 743 | __GEN_LOGICAL2(sraw, 0x18, 0x18); |
| 744 | /* srawi & srawi. */ |
| 745 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) |
| 746 | { |
| 747 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 748 | gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31)); |
| 749 | if (Rc(ctx->opcode) != 0) |
| 750 | gen_op_set_Rc0(); |
| 751 | gen_op_store_T0_gpr(rA(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 752 | } |
| 753 | /* srw & srw. */ |
| 754 | __GEN_LOGICAL2(srw, 0x18, 0x10); |
| 755 | |
| 756 | /*** Floating-Point arithmetic ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 757 | #define _GEN_FLOAT_ACB(name, op1, op2) \ |
| 758 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \ |
| 759 | { \ |
| 760 | gen_op_reset_scrfx(); \ |
| 761 | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 762 | gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
| 763 | gen_op_load_fpr_FT2(rB(ctx->opcode)); \ |
| 764 | gen_op_f##name(); \ |
| 765 | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 766 | if (Rc(ctx->opcode)) \ |
| 767 | gen_op_set_Rc1(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 768 | } |
| 769 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 770 | #define GEN_FLOAT_ACB(name, op2) \ |
| 771 | _GEN_FLOAT_ACB(name, 0x3F, op2); \ |
| 772 | _GEN_FLOAT_ACB(name##s, 0x3B, op2); |
| 773 | |
| 774 | #define _GEN_FLOAT_AB(name, op1, op2, inval) \ |
| 775 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
| 776 | { \ |
| 777 | gen_op_reset_scrfx(); \ |
| 778 | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 779 | gen_op_load_fpr_FT1(rB(ctx->opcode)); \ |
| 780 | gen_op_f##name(); \ |
| 781 | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 782 | if (Rc(ctx->opcode)) \ |
| 783 | gen_op_set_Rc1(); \ |
| 784 | } |
| 785 | #define GEN_FLOAT_AB(name, op2, inval) \ |
| 786 | _GEN_FLOAT_AB(name, 0x3F, op2, inval); \ |
| 787 | _GEN_FLOAT_AB(name##s, 0x3B, op2, inval); |
| 788 | |
| 789 | #define _GEN_FLOAT_AC(name, op1, op2, inval) \ |
| 790 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \ |
| 791 | { \ |
| 792 | gen_op_reset_scrfx(); \ |
| 793 | gen_op_load_fpr_FT0(rA(ctx->opcode)); \ |
| 794 | gen_op_load_fpr_FT1(rC(ctx->opcode)); \ |
| 795 | gen_op_f##name(); \ |
| 796 | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 797 | if (Rc(ctx->opcode)) \ |
| 798 | gen_op_set_Rc1(); \ |
| 799 | } |
| 800 | #define GEN_FLOAT_AC(name, op2, inval) \ |
| 801 | _GEN_FLOAT_AC(name, 0x3F, op2, inval); \ |
| 802 | _GEN_FLOAT_AC(name##s, 0x3B, op2, inval); |
| 803 | |
| 804 | #define GEN_FLOAT_B(name, op2, op3) \ |
| 805 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \ |
| 806 | { \ |
| 807 | gen_op_reset_scrfx(); \ |
| 808 | gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
| 809 | gen_op_f##name(); \ |
| 810 | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 811 | if (Rc(ctx->opcode)) \ |
| 812 | gen_op_set_Rc1(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 813 | } |
| 814 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 815 | #define GEN_FLOAT_BS(name, op2) \ |
| 816 | GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \ |
| 817 | { \ |
| 818 | gen_op_reset_scrfx(); \ |
| 819 | gen_op_load_fpr_FT0(rB(ctx->opcode)); \ |
| 820 | gen_op_f##name(); \ |
| 821 | gen_op_store_FT0_fpr(rD(ctx->opcode)); \ |
| 822 | if (Rc(ctx->opcode)) \ |
| 823 | gen_op_set_Rc1(); \ |
| 824 | } |
| 825 | |
| 826 | /* fadd - fadds */ |
| 827 | GEN_FLOAT_AB(add, 0x15, 0x000007C0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 828 | /* fdiv */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 829 | GEN_FLOAT_AB(div, 0x12, 0x000007C0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 830 | /* fmul */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 831 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 832 | |
| 833 | /* fres */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 834 | GEN_FLOAT_BS(res, 0x18); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 835 | |
| 836 | /* frsqrte */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 837 | GEN_FLOAT_BS(rsqrte, 0x1A); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 838 | |
| 839 | /* fsel */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 840 | _GEN_FLOAT_ACB(sel, 0x3F, 0x17); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 841 | /* fsub */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 842 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 843 | /* Optional: */ |
| 844 | /* fsqrt */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 845 | GEN_FLOAT_BS(sqrt, 0x16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 846 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 847 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 848 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 849 | gen_op_reset_scrfx(); |
| 850 | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
| 851 | gen_op_fsqrts(); |
| 852 | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
| 853 | if (Rc(ctx->opcode)) |
| 854 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 855 | } |
| 856 | |
| 857 | /*** Floating-Point multiply-and-add ***/ |
| 858 | /* fmadd */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 859 | GEN_FLOAT_ACB(madd, 0x1D); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 860 | /* fmsub */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 861 | GEN_FLOAT_ACB(msub, 0x1C); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 862 | /* fnmadd */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 863 | GEN_FLOAT_ACB(nmadd, 0x1F); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 864 | /* fnmsub */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 865 | GEN_FLOAT_ACB(nmsub, 0x1E); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 866 | |
| 867 | /*** Floating-Point round & convert ***/ |
| 868 | /* fctiw */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 869 | GEN_FLOAT_B(ctiw, 0x0E, 0x00); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 870 | /* fctiwz */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 871 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 872 | /* frsp */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 873 | GEN_FLOAT_B(rsp, 0x0C, 0x00); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 874 | |
| 875 | /*** Floating-Point compare ***/ |
| 876 | /* fcmpo */ |
| 877 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) |
| 878 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 879 | gen_op_reset_scrfx(); |
| 880 | gen_op_load_fpr_FT0(rA(ctx->opcode)); |
| 881 | gen_op_load_fpr_FT1(rB(ctx->opcode)); |
| 882 | gen_op_fcmpo(); |
| 883 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 884 | } |
| 885 | |
| 886 | /* fcmpu */ |
| 887 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) |
| 888 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 889 | gen_op_reset_scrfx(); |
| 890 | gen_op_load_fpr_FT0(rA(ctx->opcode)); |
| 891 | gen_op_load_fpr_FT1(rB(ctx->opcode)); |
| 892 | gen_op_fcmpu(); |
| 893 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 894 | } |
| 895 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 896 | /*** Floating-point move ***/ |
| 897 | /* fabs */ |
| 898 | GEN_FLOAT_B(abs, 0x08, 0x08); |
| 899 | |
| 900 | /* fmr - fmr. */ |
| 901 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) |
| 902 | { |
| 903 | gen_op_reset_scrfx(); |
| 904 | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
| 905 | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
| 906 | if (Rc(ctx->opcode)) |
| 907 | gen_op_set_Rc1(); |
| 908 | } |
| 909 | |
| 910 | /* fnabs */ |
| 911 | GEN_FLOAT_B(nabs, 0x08, 0x04); |
| 912 | /* fneg */ |
| 913 | GEN_FLOAT_B(neg, 0x08, 0x01); |
| 914 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 915 | /*** Floating-Point status & ctrl register ***/ |
| 916 | /* mcrfs */ |
| 917 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT) |
| 918 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 919 | gen_op_load_fpscr_T0(crfS(ctx->opcode)); |
| 920 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
| 921 | gen_op_clear_fpscr(crfS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 922 | } |
| 923 | |
| 924 | /* mffs */ |
| 925 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) |
| 926 | { |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 927 | gen_op_load_fpscr(); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 928 | gen_op_store_FT0_fpr(rD(ctx->opcode)); |
| 929 | if (Rc(ctx->opcode)) |
| 930 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 931 | } |
| 932 | |
| 933 | /* mtfsb0 */ |
| 934 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT) |
| 935 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 936 | uint8_t crb; |
| 937 | |
| 938 | crb = crbD(ctx->opcode) >> 2; |
| 939 | gen_op_load_fpscr_T0(crb); |
| 940 | gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03))); |
| 941 | gen_op_store_T0_fpscr(crb); |
| 942 | if (Rc(ctx->opcode)) |
| 943 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 944 | } |
| 945 | |
| 946 | /* mtfsb1 */ |
| 947 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT) |
| 948 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 949 | uint8_t crb; |
| 950 | |
| 951 | crb = crbD(ctx->opcode) >> 2; |
| 952 | gen_op_load_fpscr_T0(crb); |
| 953 | gen_op_ori(1 << (crbD(ctx->opcode) & 0x03)); |
| 954 | gen_op_store_T0_fpscr(crb); |
| 955 | if (Rc(ctx->opcode)) |
| 956 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 957 | } |
| 958 | |
| 959 | /* mtfsf */ |
| 960 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) |
| 961 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 962 | gen_op_load_fpr_FT0(rB(ctx->opcode)); |
bellard | 28b6751 | 2003-11-23 16:58:08 +0000 | [diff] [blame] | 963 | gen_op_store_fpscr(FM(ctx->opcode)); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 964 | if (Rc(ctx->opcode)) |
| 965 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 966 | } |
| 967 | |
| 968 | /* mtfsfi */ |
| 969 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) |
| 970 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 971 | gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode)); |
| 972 | if (Rc(ctx->opcode)) |
| 973 | gen_op_set_Rc1(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 974 | } |
| 975 | |
| 976 | /*** Integer load ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 977 | #if defined(CONFIG_USER_ONLY) |
| 978 | #define op_ldst(name) gen_op_##name##_raw() |
| 979 | #define OP_LD_TABLE(width) |
| 980 | #define OP_ST_TABLE(width) |
| 981 | #else |
| 982 | #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() |
| 983 | #define OP_LD_TABLE(width) \ |
| 984 | static GenOpFunc *gen_op_l##width[] = { \ |
| 985 | &gen_op_l##width##_user, \ |
| 986 | &gen_op_l##width##_kernel, \ |
| 987 | } |
| 988 | #define OP_ST_TABLE(width) \ |
| 989 | static GenOpFunc *gen_op_st##width[] = { \ |
| 990 | &gen_op_st##width##_user, \ |
| 991 | &gen_op_st##width##_kernel, \ |
| 992 | } |
| 993 | #endif |
| 994 | |
| 995 | #define GEN_LD(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 996 | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 997 | { \ |
| 998 | uint32_t simm = SIMM(ctx->opcode); \ |
| 999 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1000 | gen_op_set_T0(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1001 | } else { \ |
| 1002 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1003 | if (simm != 0) \ |
| 1004 | gen_op_addi(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1005 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1006 | op_ldst(l##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1007 | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1008 | } |
| 1009 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1010 | #define GEN_LDU(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1011 | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1012 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1013 | uint32_t simm = SIMM(ctx->opcode); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1014 | if (rA(ctx->opcode) == 0 || \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1015 | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1016 | RET_INVAL(ctx); \ |
| 1017 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1018 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1019 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1020 | if (simm != 0) \ |
| 1021 | gen_op_addi(simm); \ |
| 1022 | op_ldst(l##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1023 | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
| 1024 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1025 | } |
| 1026 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1027 | #define GEN_LDUX(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1028 | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
| 1029 | { \ |
| 1030 | if (rA(ctx->opcode) == 0 || \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1031 | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1032 | RET_INVAL(ctx); \ |
| 1033 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1034 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1035 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1036 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1037 | gen_op_add(); \ |
| 1038 | op_ldst(l##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1039 | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
| 1040 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1041 | } |
| 1042 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1043 | #define GEN_LDX(width, opc2, opc3) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1044 | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
| 1045 | { \ |
| 1046 | if (rA(ctx->opcode) == 0) { \ |
| 1047 | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1048 | } else { \ |
| 1049 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1050 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1051 | gen_op_add(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1052 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1053 | op_ldst(l##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1054 | gen_op_store_T1_gpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1055 | } |
| 1056 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1057 | #define GEN_LDS(width, op) \ |
| 1058 | OP_LD_TABLE(width); \ |
| 1059 | GEN_LD(width, op | 0x20); \ |
| 1060 | GEN_LDU(width, op | 0x21); \ |
| 1061 | GEN_LDUX(width, op | 0x01); \ |
| 1062 | GEN_LDX(width, 0x17, op | 0x00) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1063 | |
| 1064 | /* lbz lbzu lbzux lbzx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1065 | GEN_LDS(bz, 0x02); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1066 | /* lha lhau lhaux lhax */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1067 | GEN_LDS(ha, 0x0A); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1068 | /* lhz lhzu lhzux lhzx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1069 | GEN_LDS(hz, 0x08); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1070 | /* lwz lwzu lwzux lwzx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1071 | GEN_LDS(wz, 0x00); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1072 | |
| 1073 | /*** Integer store ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1074 | #define GEN_ST(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1075 | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1076 | { \ |
| 1077 | uint32_t simm = SIMM(ctx->opcode); \ |
| 1078 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1079 | gen_op_set_T0(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1080 | } else { \ |
| 1081 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1082 | if (simm != 0) \ |
| 1083 | gen_op_addi(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1084 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1085 | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
| 1086 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1087 | } |
| 1088 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1089 | #define GEN_STU(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1090 | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
| 1091 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1092 | uint32_t simm = SIMM(ctx->opcode); \ |
| 1093 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1094 | RET_INVAL(ctx); \ |
| 1095 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1096 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1097 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1098 | if (simm != 0) \ |
| 1099 | gen_op_addi(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1100 | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1101 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1102 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1103 | } |
| 1104 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1105 | #define GEN_STUX(width, opc) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1106 | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
| 1107 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1108 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1109 | RET_INVAL(ctx); \ |
| 1110 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1111 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1112 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1113 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1114 | gen_op_add(); \ |
| 1115 | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
| 1116 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1117 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1118 | } |
| 1119 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1120 | #define GEN_STX(width, opc2, opc3) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1121 | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
| 1122 | { \ |
| 1123 | if (rA(ctx->opcode) == 0) { \ |
| 1124 | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1125 | } else { \ |
| 1126 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1127 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1128 | gen_op_add(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1129 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1130 | gen_op_load_gpr_T1(rS(ctx->opcode)); \ |
| 1131 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1132 | } |
| 1133 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1134 | #define GEN_STS(width, op) \ |
| 1135 | OP_ST_TABLE(width); \ |
| 1136 | GEN_ST(width, op | 0x20); \ |
| 1137 | GEN_STU(width, op | 0x21); \ |
| 1138 | GEN_STUX(width, op | 0x01); \ |
| 1139 | GEN_STX(width, 0x17, op | 0x00) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1140 | |
| 1141 | /* stb stbu stbux stbx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1142 | GEN_STS(b, 0x06); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1143 | /* sth sthu sthux sthx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1144 | GEN_STS(h, 0x0C); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1145 | /* stw stwu stwux stwx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1146 | GEN_STS(w, 0x04); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1147 | |
| 1148 | /*** Integer load and store with byte reverse ***/ |
| 1149 | /* lhbrx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1150 | OP_LD_TABLE(hbr); |
| 1151 | GEN_LDX(hbr, 0x16, 0x18); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1152 | /* lwbrx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1153 | OP_LD_TABLE(wbr); |
| 1154 | GEN_LDX(wbr, 0x16, 0x10); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1155 | /* sthbrx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1156 | OP_ST_TABLE(hbr); |
| 1157 | GEN_STX(hbr, 0x16, 0x1C); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1158 | /* stwbrx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1159 | OP_ST_TABLE(wbr); |
| 1160 | GEN_STX(wbr, 0x16, 0x14); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1161 | |
| 1162 | /*** Integer load and store multiple ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1163 | #if defined(CONFIG_USER_ONLY) |
| 1164 | #define op_ldstm(name, reg) gen_op_##name##_raw(reg) |
| 1165 | #else |
| 1166 | #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg) |
| 1167 | static GenOpFunc1 *gen_op_lmw[] = { |
| 1168 | &gen_op_lmw_user, |
| 1169 | &gen_op_lmw_kernel, |
| 1170 | }; |
| 1171 | static GenOpFunc1 *gen_op_stmw[] = { |
| 1172 | &gen_op_stmw_user, |
| 1173 | &gen_op_stmw_kernel, |
| 1174 | }; |
| 1175 | #endif |
| 1176 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1177 | /* lmw */ |
| 1178 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1179 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1180 | int simm = SIMM(ctx->opcode); |
| 1181 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1182 | if (rA(ctx->opcode) == 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1183 | gen_op_set_T0(simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1184 | } else { |
| 1185 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1186 | if (simm != 0) |
| 1187 | gen_op_addi(simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1188 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1189 | op_ldstm(lmw, rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1190 | } |
| 1191 | |
| 1192 | /* stmw */ |
| 1193 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) |
| 1194 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1195 | int simm = SIMM(ctx->opcode); |
| 1196 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1197 | if (rA(ctx->opcode) == 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1198 | gen_op_set_T0(simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1199 | } else { |
| 1200 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1201 | if (simm != 0) |
| 1202 | gen_op_addi(simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1203 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1204 | op_ldstm(stmw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1205 | } |
| 1206 | |
| 1207 | /*** Integer load and store strings ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1208 | #if defined(CONFIG_USER_ONLY) |
| 1209 | #define op_ldsts(name, start) gen_op_##name##_raw(start) |
| 1210 | #define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb) |
| 1211 | #else |
| 1212 | #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start) |
| 1213 | #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb) |
| 1214 | static GenOpFunc1 *gen_op_lswi[] = { |
| 1215 | &gen_op_lswi_user, |
| 1216 | &gen_op_lswi_kernel, |
| 1217 | }; |
| 1218 | static GenOpFunc3 *gen_op_lswx[] = { |
| 1219 | &gen_op_lswx_user, |
| 1220 | &gen_op_lswx_kernel, |
| 1221 | }; |
| 1222 | static GenOpFunc1 *gen_op_stsw[] = { |
| 1223 | &gen_op_stsw_user, |
| 1224 | &gen_op_stsw_kernel, |
| 1225 | }; |
| 1226 | #endif |
| 1227 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1228 | /* lswi */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1229 | /* PPC32 specification says we must generate an exception if |
| 1230 | * rA is in the range of registers to be loaded. |
| 1231 | * In an other hand, IBM says this is valid, but rA won't be loaded. |
| 1232 | * For now, I'll follow the spec... |
| 1233 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1234 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER) |
| 1235 | { |
| 1236 | int nb = NB(ctx->opcode); |
| 1237 | int start = rD(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1238 | int ra = rA(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1239 | int nr; |
| 1240 | |
| 1241 | if (nb == 0) |
| 1242 | nb = 32; |
| 1243 | nr = nb / 4; |
bellard | 297d8e6 | 2004-02-21 14:11:27 +0000 | [diff] [blame] | 1244 | if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) || |
| 1245 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1246 | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
| 1247 | return; |
bellard | 297d8e6 | 2004-02-21 14:11:27 +0000 | [diff] [blame] | 1248 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1249 | if (ra == 0) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1250 | gen_op_set_T0(0); |
| 1251 | } else { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1252 | gen_op_load_gpr_T0(ra); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1253 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1254 | gen_op_set_T1(nb); |
| 1255 | op_ldsts(lswi, start); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1256 | } |
| 1257 | |
| 1258 | /* lswx */ |
| 1259 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER) |
| 1260 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1261 | int ra = rA(ctx->opcode); |
| 1262 | int rb = rB(ctx->opcode); |
| 1263 | |
| 1264 | if (ra == 0) { |
| 1265 | gen_op_load_gpr_T0(rb); |
| 1266 | ra = rb; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1267 | } else { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1268 | gen_op_load_gpr_T0(ra); |
| 1269 | gen_op_load_gpr_T1(rb); |
| 1270 | gen_op_add(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1271 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1272 | gen_op_load_xer_bc(); |
| 1273 | op_ldstsx(lswx, rD(ctx->opcode), ra, rb); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1274 | } |
| 1275 | |
| 1276 | /* stswi */ |
| 1277 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER) |
| 1278 | { |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 1279 | int nb = NB(ctx->opcode); |
| 1280 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1281 | if (rA(ctx->opcode) == 0) { |
| 1282 | gen_op_set_T0(0); |
| 1283 | } else { |
| 1284 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1285 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 1286 | if (nb == 0) |
| 1287 | nb = 32; |
| 1288 | gen_op_set_T1(nb); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1289 | op_ldsts(stsw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | /* stswx */ |
| 1293 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER) |
| 1294 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1295 | int ra = rA(ctx->opcode); |
| 1296 | |
| 1297 | if (ra == 0) { |
| 1298 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 1299 | ra = rB(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1300 | } else { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1301 | gen_op_load_gpr_T0(ra); |
| 1302 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 1303 | gen_op_add(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1304 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1305 | gen_op_load_xer_bc(); |
| 1306 | op_ldsts(stsw, rS(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1307 | } |
| 1308 | |
| 1309 | /*** Memory synchronisation ***/ |
| 1310 | /* eieio */ |
| 1311 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM) |
| 1312 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1313 | } |
| 1314 | |
| 1315 | /* isync */ |
| 1316 | GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM) |
| 1317 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1318 | } |
| 1319 | |
| 1320 | /* lwarx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1321 | #if defined(CONFIG_USER_ONLY) |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 1322 | #define op_lwarx() gen_op_lwarx_raw() |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1323 | #define op_stwcx() gen_op_stwcx_raw() |
| 1324 | #else |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 1325 | #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])() |
| 1326 | static GenOpFunc *gen_op_lwarx[] = { |
| 1327 | &gen_op_lwarx_user, |
| 1328 | &gen_op_lwarx_kernel, |
| 1329 | }; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1330 | #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])() |
| 1331 | static GenOpFunc *gen_op_stwcx[] = { |
| 1332 | &gen_op_stwcx_user, |
| 1333 | &gen_op_stwcx_kernel, |
| 1334 | }; |
| 1335 | #endif |
| 1336 | |
| 1337 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1338 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1339 | if (rA(ctx->opcode) == 0) { |
| 1340 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1341 | } else { |
| 1342 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1343 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1344 | gen_op_add(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1345 | } |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 1346 | op_lwarx(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1347 | gen_op_store_T1_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1348 | } |
| 1349 | |
| 1350 | /* stwcx. */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1351 | GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1352 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1353 | if (rA(ctx->opcode) == 0) { |
| 1354 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1355 | } else { |
| 1356 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1357 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1358 | gen_op_add(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1359 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1360 | gen_op_load_gpr_T1(rS(ctx->opcode)); |
| 1361 | op_stwcx(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1362 | } |
| 1363 | |
| 1364 | /* sync */ |
| 1365 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM) |
| 1366 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1367 | } |
| 1368 | |
| 1369 | /*** Floating-point load ***/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1370 | #define GEN_LDF(width, opc) \ |
| 1371 | GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1372 | { \ |
| 1373 | uint32_t simm = SIMM(ctx->opcode); \ |
| 1374 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1375 | gen_op_set_T0(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1376 | } else { \ |
| 1377 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1378 | if (simm != 0) \ |
| 1379 | gen_op_addi(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1380 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1381 | op_ldst(l##width); \ |
| 1382 | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1383 | } |
| 1384 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1385 | #define GEN_LDUF(width, opc) \ |
| 1386 | GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1387 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1388 | uint32_t simm = SIMM(ctx->opcode); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1389 | if (rA(ctx->opcode) == 0 || \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1390 | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1391 | RET_INVAL(ctx); \ |
| 1392 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1393 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1394 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1395 | if (simm != 0) \ |
| 1396 | gen_op_addi(simm); \ |
| 1397 | op_ldst(l##width); \ |
| 1398 | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1399 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1400 | } |
| 1401 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1402 | #define GEN_LDUXF(width, opc) \ |
| 1403 | GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1404 | { \ |
| 1405 | if (rA(ctx->opcode) == 0 || \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1406 | rA(ctx->opcode) == rD(ctx->opcode)) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1407 | RET_INVAL(ctx); \ |
| 1408 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1409 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1410 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1411 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1412 | gen_op_add(); \ |
| 1413 | op_ldst(l##width); \ |
| 1414 | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1415 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1416 | } |
| 1417 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1418 | #define GEN_LDXF(width, opc2, opc3) \ |
| 1419 | GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1420 | { \ |
| 1421 | if (rA(ctx->opcode) == 0) { \ |
| 1422 | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1423 | } else { \ |
| 1424 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1425 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1426 | gen_op_add(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1427 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1428 | op_ldst(l##width); \ |
| 1429 | gen_op_store_FT1_fpr(rD(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1430 | } |
| 1431 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1432 | #define GEN_LDFS(width, op) \ |
| 1433 | OP_LD_TABLE(width); \ |
| 1434 | GEN_LDF(width, op | 0x20); \ |
| 1435 | GEN_LDUF(width, op | 0x21); \ |
| 1436 | GEN_LDUXF(width, op | 0x01); \ |
| 1437 | GEN_LDXF(width, 0x17, op | 0x00) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1438 | |
| 1439 | /* lfd lfdu lfdux lfdx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1440 | GEN_LDFS(fd, 0x12); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1441 | /* lfs lfsu lfsux lfsx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1442 | GEN_LDFS(fs, 0x10); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1443 | |
| 1444 | /*** Floating-point store ***/ |
| 1445 | #define GEN_STF(width, opc) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1446 | GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1447 | { \ |
| 1448 | uint32_t simm = SIMM(ctx->opcode); \ |
| 1449 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1450 | gen_op_set_T0(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1451 | } else { \ |
| 1452 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1453 | if (simm != 0) \ |
| 1454 | gen_op_addi(simm); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1455 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1456 | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
| 1457 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1458 | } |
| 1459 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1460 | #define GEN_STUF(width, opc) \ |
| 1461 | GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1462 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1463 | uint32_t simm = SIMM(ctx->opcode); \ |
| 1464 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1465 | RET_INVAL(ctx); \ |
| 1466 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1467 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1468 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1469 | if (simm != 0) \ |
| 1470 | gen_op_addi(simm); \ |
| 1471 | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
| 1472 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1473 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1474 | } |
| 1475 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1476 | #define GEN_STUXF(width, opc) \ |
| 1477 | GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1478 | { \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1479 | if (rA(ctx->opcode) == 0) { \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1480 | RET_INVAL(ctx); \ |
| 1481 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1482 | } \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1483 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1484 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1485 | gen_op_add(); \ |
| 1486 | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
| 1487 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1488 | gen_op_store_T0_gpr(rA(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1489 | } |
| 1490 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1491 | #define GEN_STXF(width, opc2, opc3) \ |
| 1492 | GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1493 | { \ |
| 1494 | if (rA(ctx->opcode) == 0) { \ |
| 1495 | gen_op_load_gpr_T0(rB(ctx->opcode)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1496 | } else { \ |
| 1497 | gen_op_load_gpr_T0(rA(ctx->opcode)); \ |
| 1498 | gen_op_load_gpr_T1(rB(ctx->opcode)); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1499 | gen_op_add(); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1500 | } \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1501 | gen_op_load_fpr_FT1(rS(ctx->opcode)); \ |
| 1502 | op_ldst(st##width); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1503 | } |
| 1504 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1505 | #define GEN_STFS(width, op) \ |
| 1506 | OP_ST_TABLE(width); \ |
| 1507 | GEN_STF(width, op | 0x20); \ |
| 1508 | GEN_STUF(width, op | 0x21); \ |
| 1509 | GEN_STUXF(width, op | 0x01); \ |
| 1510 | GEN_STXF(width, 0x17, op | 0x00) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1511 | |
| 1512 | /* stfd stfdu stfdux stfdx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1513 | GEN_STFS(fd, 0x16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1514 | /* stfs stfsu stfsux stfsx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1515 | GEN_STFS(fs, 0x14); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1516 | |
| 1517 | /* Optional: */ |
| 1518 | /* stfiwx */ |
| 1519 | GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT) |
| 1520 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1521 | RET_INVAL(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1522 | } |
| 1523 | |
| 1524 | /*** Branch ***/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1525 | |
| 1526 | /* b ba bl bla */ |
| 1527 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 1528 | { |
bellard | 38a64f9 | 2004-07-07 22:06:01 +0000 | [diff] [blame] | 1529 | uint32_t li, target; |
| 1530 | |
| 1531 | /* sign extend LI */ |
| 1532 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1533 | |
| 1534 | if (AA(ctx->opcode) == 0) |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1535 | target = ctx->nip + li - 4; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1536 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1537 | target = li; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1538 | if (LK(ctx->opcode)) { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1539 | gen_op_setlr(ctx->nip); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1540 | } |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1541 | gen_op_b((long)ctx->tb, target); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1542 | ctx->exception = EXCP_BRANCH; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1543 | } |
| 1544 | |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1545 | #define BCOND_IM 0 |
| 1546 | #define BCOND_LR 1 |
| 1547 | #define BCOND_CTR 2 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1548 | |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1549 | static inline void gen_bcond(DisasContext *ctx, int type) |
| 1550 | { |
| 1551 | uint32_t target = 0; |
| 1552 | uint32_t bo = BO(ctx->opcode); |
| 1553 | uint32_t bi = BI(ctx->opcode); |
| 1554 | uint32_t mask; |
| 1555 | uint32_t li; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1556 | |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1557 | if ((bo & 0x4) == 0) |
| 1558 | gen_op_dec_ctr(); |
| 1559 | switch(type) { |
| 1560 | case BCOND_IM: |
| 1561 | li = s_ext16(BD(ctx->opcode)); |
| 1562 | if (AA(ctx->opcode) == 0) { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1563 | target = ctx->nip + li - 4; |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1564 | } else { |
| 1565 | target = li; |
| 1566 | } |
| 1567 | break; |
| 1568 | case BCOND_CTR: |
| 1569 | gen_op_movl_T1_ctr(); |
| 1570 | break; |
| 1571 | default: |
| 1572 | case BCOND_LR: |
| 1573 | gen_op_movl_T1_lr(); |
| 1574 | break; |
| 1575 | } |
| 1576 | if (LK(ctx->opcode)) { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1577 | gen_op_setlr(ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1578 | } |
| 1579 | if (bo & 0x10) { |
| 1580 | /* No CR condition */ |
| 1581 | switch (bo & 0x6) { |
| 1582 | case 0: |
| 1583 | gen_op_test_ctr(); |
| 1584 | break; |
| 1585 | case 2: |
| 1586 | gen_op_test_ctrz(); |
| 1587 | break; |
| 1588 | default: |
| 1589 | case 4: |
| 1590 | case 6: |
| 1591 | if (type == BCOND_IM) { |
| 1592 | gen_op_b((long)ctx->tb, target); |
| 1593 | } else { |
| 1594 | gen_op_b_T1(); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1595 | } |
| 1596 | goto no_test; |
| 1597 | } |
| 1598 | } else { |
| 1599 | mask = 1 << (3 - (bi & 0x03)); |
| 1600 | gen_op_load_crf_T0(bi >> 2); |
| 1601 | if (bo & 0x8) { |
| 1602 | switch (bo & 0x6) { |
| 1603 | case 0: |
| 1604 | gen_op_test_ctr_true(mask); |
| 1605 | break; |
| 1606 | case 2: |
| 1607 | gen_op_test_ctrz_true(mask); |
| 1608 | break; |
| 1609 | default: |
| 1610 | case 4: |
| 1611 | case 6: |
| 1612 | gen_op_test_true(mask); |
| 1613 | break; |
| 1614 | } |
| 1615 | } else { |
| 1616 | switch (bo & 0x6) { |
| 1617 | case 0: |
| 1618 | gen_op_test_ctr_false(mask); |
| 1619 | break; |
| 1620 | case 2: |
| 1621 | gen_op_test_ctrz_false(mask); |
| 1622 | break; |
| 1623 | default: |
| 1624 | case 4: |
| 1625 | case 6: |
| 1626 | gen_op_test_false(mask); |
| 1627 | break; |
| 1628 | } |
| 1629 | } |
| 1630 | } |
| 1631 | if (type == BCOND_IM) { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1632 | gen_op_btest((long)ctx->tb, target, ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1633 | } else { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 1634 | gen_op_btest_T1(ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 1635 | } |
| 1636 | no_test: |
| 1637 | ctx->exception = EXCP_BRANCH; |
| 1638 | } |
| 1639 | |
| 1640 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 1641 | { |
| 1642 | gen_bcond(ctx, BCOND_IM); |
| 1643 | } |
| 1644 | |
| 1645 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW) |
| 1646 | { |
| 1647 | gen_bcond(ctx, BCOND_CTR); |
| 1648 | } |
| 1649 | |
| 1650 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW) |
| 1651 | { |
| 1652 | gen_bcond(ctx, BCOND_LR); |
| 1653 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1654 | |
| 1655 | /*** Condition register logical ***/ |
| 1656 | #define GEN_CRLOGIC(op, opc) \ |
| 1657 | GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \ |
| 1658 | { \ |
| 1659 | gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \ |
| 1660 | gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \ |
| 1661 | gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \ |
| 1662 | gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \ |
| 1663 | gen_op_##op(); \ |
| 1664 | gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \ |
| 1665 | gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \ |
| 1666 | 3 - (crbD(ctx->opcode) & 0x03)); \ |
| 1667 | gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1668 | } |
| 1669 | |
| 1670 | /* crand */ |
| 1671 | GEN_CRLOGIC(and, 0x08) |
| 1672 | /* crandc */ |
| 1673 | GEN_CRLOGIC(andc, 0x04) |
| 1674 | /* creqv */ |
| 1675 | GEN_CRLOGIC(eqv, 0x09) |
| 1676 | /* crnand */ |
| 1677 | GEN_CRLOGIC(nand, 0x07) |
| 1678 | /* crnor */ |
| 1679 | GEN_CRLOGIC(nor, 0x01) |
| 1680 | /* cror */ |
| 1681 | GEN_CRLOGIC(or, 0x0E) |
| 1682 | /* crorc */ |
| 1683 | GEN_CRLOGIC(orc, 0x0D) |
| 1684 | /* crxor */ |
| 1685 | GEN_CRLOGIC(xor, 0x06) |
| 1686 | /* mcrf */ |
| 1687 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER) |
| 1688 | { |
| 1689 | gen_op_load_crf_T0(crfS(ctx->opcode)); |
| 1690 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1691 | } |
| 1692 | |
| 1693 | /*** System linkage ***/ |
| 1694 | /* rfi (supervisor only) */ |
| 1695 | GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW) |
| 1696 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1697 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1698 | RET_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1699 | #else |
| 1700 | /* Restore CPU state */ |
| 1701 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1702 | RET_PRIVOPC(ctx); |
| 1703 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1704 | } |
| 1705 | gen_op_rfi(); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1706 | RET_EXCP(ctx, EXCP_RFI, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1707 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1708 | } |
| 1709 | |
| 1710 | /* sc */ |
| 1711 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW) |
| 1712 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1713 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1714 | RET_EXCP(ctx, EXCP_SYSCALL_USER, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1715 | #else |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1716 | RET_EXCP(ctx, EXCP_SYSCALL, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1717 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1718 | } |
| 1719 | |
| 1720 | /*** Trap ***/ |
| 1721 | /* tw */ |
| 1722 | GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW) |
| 1723 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1724 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1725 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 1726 | gen_op_tw(TO(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1727 | } |
| 1728 | |
| 1729 | /* twi */ |
| 1730 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 1731 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1732 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1733 | #if 0 |
| 1734 | printf("%s: param=0x%04x T0=0x%04x\n", __func__, |
| 1735 | SIMM(ctx->opcode), TO(ctx->opcode)); |
| 1736 | #endif |
| 1737 | gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | /*** Processor control ***/ |
| 1741 | static inline int check_spr_access (int spr, int rw, int supervisor) |
| 1742 | { |
| 1743 | uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1)); |
| 1744 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1745 | #if 0 |
| 1746 | if (spr != LR && spr != CTR) { |
| 1747 | if (loglevel > 0) { |
| 1748 | fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__, |
| 1749 | SPR_ENCODE(spr), supervisor, rw, rights, |
| 1750 | (rights >> ((2 * supervisor) + rw)) & 1); |
| 1751 | } else { |
| 1752 | printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__, |
| 1753 | SPR_ENCODE(spr), supervisor, rw, rights, |
| 1754 | (rights >> ((2 * supervisor) + rw)) & 1); |
| 1755 | } |
| 1756 | } |
| 1757 | #endif |
| 1758 | if (rights == 0) |
| 1759 | return -1; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1760 | rights = rights >> (2 * supervisor); |
| 1761 | rights = rights >> rw; |
| 1762 | |
| 1763 | return rights & 1; |
| 1764 | } |
| 1765 | |
| 1766 | /* mcrxr */ |
| 1767 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC) |
| 1768 | { |
| 1769 | gen_op_load_xer_cr(); |
| 1770 | gen_op_store_T0_crf(crfD(ctx->opcode)); |
| 1771 | gen_op_clear_xer_cr(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1772 | } |
| 1773 | |
| 1774 | /* mfcr */ |
| 1775 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC) |
| 1776 | { |
| 1777 | gen_op_load_cr(); |
| 1778 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1779 | } |
| 1780 | |
| 1781 | /* mfmsr */ |
| 1782 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) |
| 1783 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1784 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1785 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1786 | #else |
| 1787 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1788 | RET_PRIVREG(ctx); |
| 1789 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1790 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1791 | gen_op_load_msr(); |
| 1792 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1793 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1794 | } |
| 1795 | |
| 1796 | /* mfspr */ |
| 1797 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC) |
| 1798 | { |
| 1799 | uint32_t sprn = SPR(ctx->opcode); |
| 1800 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1801 | #if defined(CONFIG_USER_ONLY) |
| 1802 | switch (check_spr_access(sprn, 0, 0)) |
| 1803 | #else |
| 1804 | switch (check_spr_access(sprn, 0, ctx->supervisor)) |
| 1805 | #endif |
| 1806 | { |
| 1807 | case -1: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1808 | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
| 1809 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1810 | case 0: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1811 | RET_PRIVREG(ctx); |
| 1812 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1813 | default: |
| 1814 | break; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1815 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1816 | switch (sprn) { |
| 1817 | case XER: |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1818 | gen_op_load_xer(); |
| 1819 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1820 | case LR: |
| 1821 | gen_op_load_lr(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1822 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1823 | case CTR: |
| 1824 | gen_op_load_ctr(); |
| 1825 | break; |
| 1826 | case IBAT0U: |
| 1827 | gen_op_load_ibat(0, 0); |
| 1828 | break; |
| 1829 | case IBAT1U: |
| 1830 | gen_op_load_ibat(0, 1); |
| 1831 | break; |
| 1832 | case IBAT2U: |
| 1833 | gen_op_load_ibat(0, 2); |
| 1834 | break; |
| 1835 | case IBAT3U: |
| 1836 | gen_op_load_ibat(0, 3); |
| 1837 | break; |
| 1838 | case IBAT4U: |
| 1839 | gen_op_load_ibat(0, 4); |
| 1840 | break; |
| 1841 | case IBAT5U: |
| 1842 | gen_op_load_ibat(0, 5); |
| 1843 | break; |
| 1844 | case IBAT6U: |
| 1845 | gen_op_load_ibat(0, 6); |
| 1846 | break; |
| 1847 | case IBAT7U: |
| 1848 | gen_op_load_ibat(0, 7); |
| 1849 | break; |
| 1850 | case IBAT0L: |
| 1851 | gen_op_load_ibat(1, 0); |
| 1852 | break; |
| 1853 | case IBAT1L: |
| 1854 | gen_op_load_ibat(1, 1); |
| 1855 | break; |
| 1856 | case IBAT2L: |
| 1857 | gen_op_load_ibat(1, 2); |
| 1858 | break; |
| 1859 | case IBAT3L: |
| 1860 | gen_op_load_ibat(1, 3); |
| 1861 | break; |
| 1862 | case IBAT4L: |
| 1863 | gen_op_load_ibat(1, 4); |
| 1864 | break; |
| 1865 | case IBAT5L: |
| 1866 | gen_op_load_ibat(1, 5); |
| 1867 | break; |
| 1868 | case IBAT6L: |
| 1869 | gen_op_load_ibat(1, 6); |
| 1870 | break; |
| 1871 | case IBAT7L: |
| 1872 | gen_op_load_ibat(1, 7); |
| 1873 | break; |
| 1874 | case DBAT0U: |
| 1875 | gen_op_load_dbat(0, 0); |
| 1876 | break; |
| 1877 | case DBAT1U: |
| 1878 | gen_op_load_dbat(0, 1); |
| 1879 | break; |
| 1880 | case DBAT2U: |
| 1881 | gen_op_load_dbat(0, 2); |
| 1882 | break; |
| 1883 | case DBAT3U: |
| 1884 | gen_op_load_dbat(0, 3); |
| 1885 | break; |
| 1886 | case DBAT4U: |
| 1887 | gen_op_load_dbat(0, 4); |
| 1888 | break; |
| 1889 | case DBAT5U: |
| 1890 | gen_op_load_dbat(0, 5); |
| 1891 | break; |
| 1892 | case DBAT6U: |
| 1893 | gen_op_load_dbat(0, 6); |
| 1894 | break; |
| 1895 | case DBAT7U: |
| 1896 | gen_op_load_dbat(0, 7); |
| 1897 | break; |
| 1898 | case DBAT0L: |
| 1899 | gen_op_load_dbat(1, 0); |
| 1900 | break; |
| 1901 | case DBAT1L: |
| 1902 | gen_op_load_dbat(1, 1); |
| 1903 | break; |
| 1904 | case DBAT2L: |
| 1905 | gen_op_load_dbat(1, 2); |
| 1906 | break; |
| 1907 | case DBAT3L: |
| 1908 | gen_op_load_dbat(1, 3); |
| 1909 | break; |
| 1910 | case DBAT4L: |
| 1911 | gen_op_load_dbat(1, 4); |
| 1912 | break; |
| 1913 | case DBAT5L: |
| 1914 | gen_op_load_dbat(1, 5); |
| 1915 | break; |
| 1916 | case DBAT6L: |
| 1917 | gen_op_load_dbat(1, 6); |
| 1918 | break; |
| 1919 | case DBAT7L: |
| 1920 | gen_op_load_dbat(1, 7); |
| 1921 | break; |
| 1922 | case SDR1: |
| 1923 | gen_op_load_sdr1(); |
| 1924 | break; |
| 1925 | case V_TBL: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1926 | gen_op_load_tbl(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1927 | break; |
| 1928 | case V_TBU: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1929 | gen_op_load_tbu(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1930 | break; |
| 1931 | case DECR: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1932 | gen_op_load_decr(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1933 | break; |
| 1934 | default: |
| 1935 | gen_op_load_spr(sprn); |
| 1936 | break; |
| 1937 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1938 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1939 | } |
| 1940 | |
| 1941 | /* mftb */ |
| 1942 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC) |
| 1943 | { |
| 1944 | uint32_t sprn = SPR(ctx->opcode); |
| 1945 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1946 | /* We need to update the time base before reading it */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1947 | switch (sprn) { |
| 1948 | case V_TBL: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1949 | gen_op_load_tbl(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1950 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1951 | case V_TBU: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1952 | gen_op_load_tbu(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1953 | break; |
| 1954 | default: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1955 | RET_INVAL(ctx); |
| 1956 | return; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1957 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1958 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1959 | } |
| 1960 | |
| 1961 | /* mtcrf */ |
| 1962 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC) |
| 1963 | { |
| 1964 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 1965 | gen_op_store_cr(CRM(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1966 | } |
| 1967 | |
| 1968 | /* mtmsr */ |
| 1969 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) |
| 1970 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1971 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1972 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1973 | #else |
| 1974 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1975 | RET_PRIVREG(ctx); |
| 1976 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1977 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1978 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 1979 | gen_op_store_msr(); |
| 1980 | /* Must stop the translation as machine state (may have) changed */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1981 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1982 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1983 | } |
| 1984 | |
| 1985 | /* mtspr */ |
| 1986 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) |
| 1987 | { |
| 1988 | uint32_t sprn = SPR(ctx->opcode); |
| 1989 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1990 | #if 0 |
| 1991 | if (loglevel > 0) { |
| 1992 | fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn), |
| 1993 | rS(ctx->opcode), sprn); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1994 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1995 | #endif |
| 1996 | #if defined(CONFIG_USER_ONLY) |
| 1997 | switch (check_spr_access(sprn, 1, 0)) |
| 1998 | #else |
| 1999 | switch (check_spr_access(sprn, 1, ctx->supervisor)) |
| 2000 | #endif |
| 2001 | { |
| 2002 | case -1: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2003 | RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2004 | break; |
| 2005 | case 0: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2006 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2007 | break; |
| 2008 | default: |
| 2009 | break; |
| 2010 | } |
| 2011 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 2012 | switch (sprn) { |
| 2013 | case XER: |
| 2014 | gen_op_store_xer(); |
| 2015 | break; |
| 2016 | case LR: |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2017 | gen_op_store_lr(); |
| 2018 | break; |
| 2019 | case CTR: |
| 2020 | gen_op_store_ctr(); |
| 2021 | break; |
| 2022 | case IBAT0U: |
| 2023 | gen_op_store_ibat(0, 0); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2024 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2025 | break; |
| 2026 | case IBAT1U: |
| 2027 | gen_op_store_ibat(0, 1); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2028 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2029 | break; |
| 2030 | case IBAT2U: |
| 2031 | gen_op_store_ibat(0, 2); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2032 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2033 | break; |
| 2034 | case IBAT3U: |
| 2035 | gen_op_store_ibat(0, 3); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2036 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2037 | break; |
| 2038 | case IBAT4U: |
| 2039 | gen_op_store_ibat(0, 4); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2040 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2041 | break; |
| 2042 | case IBAT5U: |
| 2043 | gen_op_store_ibat(0, 5); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2044 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2045 | break; |
| 2046 | case IBAT6U: |
| 2047 | gen_op_store_ibat(0, 6); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2048 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2049 | break; |
| 2050 | case IBAT7U: |
| 2051 | gen_op_store_ibat(0, 7); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2052 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2053 | break; |
| 2054 | case IBAT0L: |
| 2055 | gen_op_store_ibat(1, 0); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2056 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2057 | break; |
| 2058 | case IBAT1L: |
| 2059 | gen_op_store_ibat(1, 1); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2060 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2061 | break; |
| 2062 | case IBAT2L: |
| 2063 | gen_op_store_ibat(1, 2); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2064 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2065 | break; |
| 2066 | case IBAT3L: |
| 2067 | gen_op_store_ibat(1, 3); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2068 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2069 | break; |
| 2070 | case IBAT4L: |
| 2071 | gen_op_store_ibat(1, 4); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2072 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2073 | break; |
| 2074 | case IBAT5L: |
| 2075 | gen_op_store_ibat(1, 5); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2076 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2077 | break; |
| 2078 | case IBAT6L: |
| 2079 | gen_op_store_ibat(1, 6); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2080 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2081 | break; |
| 2082 | case IBAT7L: |
| 2083 | gen_op_store_ibat(1, 7); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2084 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2085 | break; |
| 2086 | case DBAT0U: |
| 2087 | gen_op_store_dbat(0, 0); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2088 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2089 | break; |
| 2090 | case DBAT1U: |
| 2091 | gen_op_store_dbat(0, 1); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2092 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2093 | break; |
| 2094 | case DBAT2U: |
| 2095 | gen_op_store_dbat(0, 2); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2096 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2097 | break; |
| 2098 | case DBAT3U: |
| 2099 | gen_op_store_dbat(0, 3); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2100 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2101 | break; |
| 2102 | case DBAT4U: |
| 2103 | gen_op_store_dbat(0, 4); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2104 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2105 | break; |
| 2106 | case DBAT5U: |
| 2107 | gen_op_store_dbat(0, 5); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2108 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2109 | break; |
| 2110 | case DBAT6U: |
| 2111 | gen_op_store_dbat(0, 6); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2112 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2113 | break; |
| 2114 | case DBAT7U: |
| 2115 | gen_op_store_dbat(0, 7); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2116 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2117 | break; |
| 2118 | case DBAT0L: |
| 2119 | gen_op_store_dbat(1, 0); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2120 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2121 | break; |
| 2122 | case DBAT1L: |
| 2123 | gen_op_store_dbat(1, 1); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2124 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2125 | break; |
| 2126 | case DBAT2L: |
| 2127 | gen_op_store_dbat(1, 2); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2128 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2129 | break; |
| 2130 | case DBAT3L: |
| 2131 | gen_op_store_dbat(1, 3); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2132 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2133 | break; |
| 2134 | case DBAT4L: |
| 2135 | gen_op_store_dbat(1, 4); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2136 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2137 | break; |
| 2138 | case DBAT5L: |
| 2139 | gen_op_store_dbat(1, 5); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2140 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2141 | break; |
| 2142 | case DBAT6L: |
| 2143 | gen_op_store_dbat(1, 6); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2144 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2145 | break; |
| 2146 | case DBAT7L: |
| 2147 | gen_op_store_dbat(1, 7); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2148 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2149 | break; |
| 2150 | case SDR1: |
| 2151 | gen_op_store_sdr1(); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2152 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2153 | break; |
| 2154 | case O_TBL: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2155 | gen_op_store_tbl(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2156 | break; |
| 2157 | case O_TBU: |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2158 | gen_op_store_tbu(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2159 | break; |
| 2160 | case DECR: |
| 2161 | gen_op_store_decr(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2162 | break; |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2163 | #if 0 |
| 2164 | case HID0: |
| 2165 | gen_op_store_hid0(); |
| 2166 | break; |
| 2167 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2168 | default: |
| 2169 | gen_op_store_spr(sprn); |
| 2170 | break; |
| 2171 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2172 | } |
| 2173 | |
| 2174 | /*** Cache management ***/ |
| 2175 | /* For now, all those will be implemented as nop: |
| 2176 | * this is valid, regarding the PowerPC specs... |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2177 | * We just have to flush tb while invalidating instruction cache lines... |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2178 | */ |
| 2179 | /* dcbf */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2180 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2181 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2182 | if (rA(ctx->opcode) == 0) { |
| 2183 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2184 | } else { |
| 2185 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2186 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2187 | gen_op_add(); |
| 2188 | } |
| 2189 | op_ldst(lbz); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2190 | } |
| 2191 | |
| 2192 | /* dcbi (Supervisor only) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2193 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2194 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2195 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2196 | RET_PRIVOPC(ctx); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2197 | #else |
| 2198 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2199 | RET_PRIVOPC(ctx); |
| 2200 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2201 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2202 | if (rA(ctx->opcode) == 0) { |
| 2203 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2204 | } else { |
| 2205 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2206 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2207 | gen_op_add(); |
| 2208 | } |
| 2209 | op_ldst(lbz); |
| 2210 | op_ldst(stb); |
| 2211 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2212 | } |
| 2213 | |
| 2214 | /* dcdst */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2215 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2216 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2217 | if (rA(ctx->opcode) == 0) { |
| 2218 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2219 | } else { |
| 2220 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2221 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2222 | gen_op_add(); |
| 2223 | } |
| 2224 | op_ldst(lbz); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2225 | } |
| 2226 | |
| 2227 | /* dcbt */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2228 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2229 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2230 | } |
| 2231 | |
| 2232 | /* dcbtst */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2233 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2234 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2235 | } |
| 2236 | |
| 2237 | /* dcbz */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2238 | #if defined(CONFIG_USER_ONLY) |
| 2239 | #define op_dcbz() gen_op_dcbz_raw() |
| 2240 | #else |
| 2241 | #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])() |
| 2242 | static GenOpFunc *gen_op_dcbz[] = { |
| 2243 | &gen_op_dcbz_user, |
| 2244 | &gen_op_dcbz_kernel, |
| 2245 | }; |
| 2246 | #endif |
| 2247 | |
| 2248 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2249 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2250 | if (rA(ctx->opcode) == 0) { |
| 2251 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2252 | } else { |
| 2253 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2254 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2255 | gen_op_add(); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2256 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2257 | op_dcbz(); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2258 | gen_op_check_reservation(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2259 | } |
| 2260 | |
| 2261 | /* icbi */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2262 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2263 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2264 | if (rA(ctx->opcode) == 0) { |
| 2265 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2266 | } else { |
| 2267 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2268 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2269 | gen_op_add(); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2270 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2271 | gen_op_icbi(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2272 | } |
| 2273 | |
| 2274 | /* Optional: */ |
| 2275 | /* dcba */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2276 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2277 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2278 | } |
| 2279 | |
| 2280 | /*** Segment register manipulation ***/ |
| 2281 | /* Supervisor only: */ |
| 2282 | /* mfsr */ |
| 2283 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) |
| 2284 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2285 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2286 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2287 | #else |
| 2288 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2289 | RET_PRIVREG(ctx); |
| 2290 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2291 | } |
| 2292 | gen_op_load_sr(SR(ctx->opcode)); |
| 2293 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
| 2294 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2295 | } |
| 2296 | |
| 2297 | /* mfsrin */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2298 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2299 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2300 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2301 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2302 | #else |
| 2303 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2304 | RET_PRIVREG(ctx); |
| 2305 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2306 | } |
| 2307 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2308 | gen_op_load_srin(); |
| 2309 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
| 2310 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2311 | } |
| 2312 | |
| 2313 | /* mtsr */ |
bellard | e63c59c | 2004-05-17 21:05:06 +0000 | [diff] [blame] | 2314 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2315 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2316 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2317 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2318 | #else |
| 2319 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2320 | RET_PRIVREG(ctx); |
| 2321 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2322 | } |
| 2323 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 2324 | gen_op_store_sr(SR(ctx->opcode)); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2325 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2326 | } |
| 2327 | |
| 2328 | /* mtsrin */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2329 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2330 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2331 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2332 | RET_PRIVREG(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2333 | #else |
| 2334 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2335 | RET_PRIVREG(ctx); |
| 2336 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2337 | } |
| 2338 | gen_op_load_gpr_T0(rS(ctx->opcode)); |
| 2339 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2340 | gen_op_store_srin(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2341 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2342 | } |
| 2343 | |
| 2344 | /*** Lookaside buffer management ***/ |
| 2345 | /* Optional & supervisor only: */ |
| 2346 | /* tlbia */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2347 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2348 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2349 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2350 | RET_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2351 | #else |
| 2352 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2353 | if (loglevel) |
| 2354 | fprintf(logfile, "%s: ! supervisor\n", __func__); |
| 2355 | RET_PRIVOPC(ctx); |
| 2356 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2357 | } |
| 2358 | gen_op_tlbia(); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2359 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2360 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2361 | } |
| 2362 | |
| 2363 | /* tlbie */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2364 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2365 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2366 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2367 | RET_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2368 | #else |
| 2369 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2370 | RET_PRIVOPC(ctx); |
| 2371 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2372 | } |
| 2373 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2374 | gen_op_tlbie(); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2375 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2376 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2377 | } |
| 2378 | |
| 2379 | /* tlbsync */ |
bellard | e63c59c | 2004-05-17 21:05:06 +0000 | [diff] [blame] | 2380 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2381 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2382 | #if defined(CONFIG_USER_ONLY) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2383 | RET_PRIVOPC(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2384 | #else |
| 2385 | if (!ctx->supervisor) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2386 | RET_PRIVOPC(ctx); |
| 2387 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2388 | } |
| 2389 | /* This has no effect: it should ensure that all previous |
| 2390 | * tlbie have completed |
| 2391 | */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2392 | RET_MTMSR(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2393 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2394 | } |
| 2395 | |
| 2396 | /*** External control ***/ |
| 2397 | /* Optional: */ |
| 2398 | /* eciwx */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2399 | #if defined(CONFIG_USER_ONLY) |
| 2400 | #define op_eciwx() gen_op_eciwx_raw() |
| 2401 | #define op_ecowx() gen_op_ecowx_raw() |
| 2402 | #else |
| 2403 | #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])() |
| 2404 | #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])() |
| 2405 | static GenOpFunc *gen_op_eciwx[] = { |
| 2406 | &gen_op_eciwx_user, |
| 2407 | &gen_op_eciwx_kernel, |
| 2408 | }; |
| 2409 | static GenOpFunc *gen_op_ecowx[] = { |
| 2410 | &gen_op_ecowx_user, |
| 2411 | &gen_op_ecowx_kernel, |
| 2412 | }; |
| 2413 | #endif |
| 2414 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2415 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) |
| 2416 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2417 | /* Should check EAR[E] & alignment ! */ |
| 2418 | if (rA(ctx->opcode) == 0) { |
| 2419 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2420 | } else { |
| 2421 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2422 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2423 | gen_op_add(); |
| 2424 | } |
| 2425 | op_eciwx(); |
| 2426 | gen_op_store_T0_gpr(rD(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2427 | } |
| 2428 | |
| 2429 | /* ecowx */ |
| 2430 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) |
| 2431 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2432 | /* Should check EAR[E] & alignment ! */ |
| 2433 | if (rA(ctx->opcode) == 0) { |
| 2434 | gen_op_load_gpr_T0(rB(ctx->opcode)); |
| 2435 | } else { |
| 2436 | gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2437 | gen_op_load_gpr_T1(rB(ctx->opcode)); |
| 2438 | gen_op_add(); |
| 2439 | } |
| 2440 | gen_op_load_gpr_T2(rS(ctx->opcode)); |
| 2441 | op_ecowx(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2442 | } |
| 2443 | |
| 2444 | /* End opcode list */ |
| 2445 | GEN_OPCODE_MARK(end); |
| 2446 | |
| 2447 | /*****************************************************************************/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2448 | #include <stdlib.h> |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2449 | #include <string.h> |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2450 | |
| 2451 | int fflush (FILE *stream); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2452 | |
| 2453 | /* Main ppc opcodes table: |
| 2454 | * at init, all opcodes are invalids |
| 2455 | */ |
| 2456 | static opc_handler_t *ppc_opcodes[0x40]; |
| 2457 | |
| 2458 | /* Opcode types */ |
| 2459 | enum { |
| 2460 | PPC_DIRECT = 0, /* Opcode routine */ |
| 2461 | PPC_INDIRECT = 1, /* Indirect opcode table */ |
| 2462 | }; |
| 2463 | |
| 2464 | static inline int is_indirect_opcode (void *handler) |
| 2465 | { |
| 2466 | return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
| 2467 | } |
| 2468 | |
| 2469 | static inline opc_handler_t **ind_table(void *handler) |
| 2470 | { |
| 2471 | return (opc_handler_t **)((unsigned long)handler & ~3); |
| 2472 | } |
| 2473 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2474 | /* Instruction table creation */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2475 | /* Opcodes tables creation */ |
| 2476 | static void fill_new_table (opc_handler_t **table, int len) |
| 2477 | { |
| 2478 | int i; |
| 2479 | |
| 2480 | for (i = 0; i < len; i++) |
| 2481 | table[i] = &invalid_handler; |
| 2482 | } |
| 2483 | |
| 2484 | static int create_new_table (opc_handler_t **table, unsigned char idx) |
| 2485 | { |
| 2486 | opc_handler_t **tmp; |
| 2487 | |
| 2488 | tmp = malloc(0x20 * sizeof(opc_handler_t)); |
| 2489 | if (tmp == NULL) |
| 2490 | return -1; |
| 2491 | fill_new_table(tmp, 0x20); |
| 2492 | table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
| 2493 | |
| 2494 | return 0; |
| 2495 | } |
| 2496 | |
| 2497 | static int insert_in_table (opc_handler_t **table, unsigned char idx, |
| 2498 | opc_handler_t *handler) |
| 2499 | { |
| 2500 | if (table[idx] != &invalid_handler) |
| 2501 | return -1; |
| 2502 | table[idx] = handler; |
| 2503 | |
| 2504 | return 0; |
| 2505 | } |
| 2506 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2507 | static int register_direct_insn (opc_handler_t **ppc_opcodes, |
| 2508 | unsigned char idx, opc_handler_t *handler) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2509 | { |
| 2510 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2511 | printf("*** ERROR: opcode %02x already assigned in main " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2512 | "opcode table\n", idx); |
| 2513 | return -1; |
| 2514 | } |
| 2515 | |
| 2516 | return 0; |
| 2517 | } |
| 2518 | |
| 2519 | static int register_ind_in_table (opc_handler_t **table, |
| 2520 | unsigned char idx1, unsigned char idx2, |
| 2521 | opc_handler_t *handler) |
| 2522 | { |
| 2523 | if (table[idx1] == &invalid_handler) { |
| 2524 | if (create_new_table(table, idx1) < 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2525 | printf("*** ERROR: unable to create indirect table " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2526 | "idx=%02x\n", idx1); |
| 2527 | return -1; |
| 2528 | } |
| 2529 | } else { |
| 2530 | if (!is_indirect_opcode(table[idx1])) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2531 | printf("*** ERROR: idx %02x already assigned to a direct " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2532 | "opcode\n", idx1); |
| 2533 | return -1; |
| 2534 | } |
| 2535 | } |
| 2536 | if (handler != NULL && |
| 2537 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2538 | printf("*** ERROR: opcode %02x already assigned in " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2539 | "opcode table %02x\n", idx2, idx1); |
| 2540 | return -1; |
| 2541 | } |
| 2542 | |
| 2543 | return 0; |
| 2544 | } |
| 2545 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2546 | static int register_ind_insn (opc_handler_t **ppc_opcodes, |
| 2547 | unsigned char idx1, unsigned char idx2, |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2548 | opc_handler_t *handler) |
| 2549 | { |
| 2550 | int ret; |
| 2551 | |
| 2552 | ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
| 2553 | |
| 2554 | return ret; |
| 2555 | } |
| 2556 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2557 | static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
| 2558 | unsigned char idx1, unsigned char idx2, |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2559 | unsigned char idx3, opc_handler_t *handler) |
| 2560 | { |
| 2561 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2562 | printf("*** ERROR: unable to join indirect table idx " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2563 | "[%02x-%02x]\n", idx1, idx2); |
| 2564 | return -1; |
| 2565 | } |
| 2566 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, |
| 2567 | handler) < 0) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2568 | printf("*** ERROR: unable to insert opcode " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2569 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); |
| 2570 | return -1; |
| 2571 | } |
| 2572 | |
| 2573 | return 0; |
| 2574 | } |
| 2575 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2576 | static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2577 | { |
| 2578 | if (insn->opc2 != 0xFF) { |
| 2579 | if (insn->opc3 != 0xFF) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2580 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, |
| 2581 | insn->opc3, &insn->handler) < 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2582 | return -1; |
| 2583 | } else { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2584 | if (register_ind_insn(ppc_opcodes, insn->opc1, |
| 2585 | insn->opc2, &insn->handler) < 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2586 | return -1; |
| 2587 | } |
| 2588 | } else { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2589 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2590 | return -1; |
| 2591 | } |
| 2592 | |
| 2593 | return 0; |
| 2594 | } |
| 2595 | |
| 2596 | static int test_opcode_table (opc_handler_t **table, int len) |
| 2597 | { |
| 2598 | int i, count, tmp; |
| 2599 | |
| 2600 | for (i = 0, count = 0; i < len; i++) { |
| 2601 | /* Consistency fixup */ |
| 2602 | if (table[i] == NULL) |
| 2603 | table[i] = &invalid_handler; |
| 2604 | if (table[i] != &invalid_handler) { |
| 2605 | if (is_indirect_opcode(table[i])) { |
| 2606 | tmp = test_opcode_table(ind_table(table[i]), 0x20); |
| 2607 | if (tmp == 0) { |
| 2608 | free(table[i]); |
| 2609 | table[i] = &invalid_handler; |
| 2610 | } else { |
| 2611 | count++; |
| 2612 | } |
| 2613 | } else { |
| 2614 | count++; |
| 2615 | } |
| 2616 | } |
| 2617 | } |
| 2618 | |
| 2619 | return count; |
| 2620 | } |
| 2621 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2622 | static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2623 | { |
| 2624 | if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2625 | printf("*** WARNING: no opcode defined !\n"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2626 | } |
| 2627 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2628 | #define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw))) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2629 | #define SPR_UR SPR_RIGHTS(0, 0) |
| 2630 | #define SPR_UW SPR_RIGHTS(1, 0) |
| 2631 | #define SPR_SR SPR_RIGHTS(0, 1) |
| 2632 | #define SPR_SW SPR_RIGHTS(1, 1) |
| 2633 | |
| 2634 | #define spr_set_rights(spr, rights) \ |
| 2635 | do { \ |
| 2636 | spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \ |
| 2637 | } while (0) |
| 2638 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2639 | static void init_spr_rights (uint32_t pvr) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2640 | { |
| 2641 | /* XER (SPR 1) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2642 | spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2643 | /* LR (SPR 8) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2644 | spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2645 | /* CTR (SPR 9) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2646 | spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2647 | /* TBL (SPR 268) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2648 | spr_set_rights(V_TBL, SPR_UR | SPR_SR); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2649 | /* TBU (SPR 269) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2650 | spr_set_rights(V_TBU, SPR_UR | SPR_SR); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2651 | /* DSISR (SPR 18) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2652 | spr_set_rights(DSISR, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2653 | /* DAR (SPR 19) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2654 | spr_set_rights(DAR, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2655 | /* DEC (SPR 22) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2656 | spr_set_rights(DECR, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2657 | /* SDR1 (SPR 25) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2658 | spr_set_rights(SDR1, SPR_SR | SPR_SW); |
| 2659 | /* SRR0 (SPR 26) */ |
| 2660 | spr_set_rights(SRR0, SPR_SR | SPR_SW); |
| 2661 | /* SRR1 (SPR 27) */ |
| 2662 | spr_set_rights(SRR1, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2663 | /* SPRG0 (SPR 272) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2664 | spr_set_rights(SPRG0, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2665 | /* SPRG1 (SPR 273) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2666 | spr_set_rights(SPRG1, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2667 | /* SPRG2 (SPR 274) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2668 | spr_set_rights(SPRG2, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2669 | /* SPRG3 (SPR 275) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2670 | spr_set_rights(SPRG3, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2671 | /* ASR (SPR 280) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2672 | spr_set_rights(ASR, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2673 | /* EAR (SPR 282) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2674 | spr_set_rights(EAR, SPR_SR | SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2675 | /* TBL (SPR 284) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2676 | spr_set_rights(O_TBL, SPR_SW); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2677 | /* TBU (SPR 285) */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2678 | spr_set_rights(O_TBU, SPR_SW); |
| 2679 | /* PVR (SPR 287) */ |
| 2680 | spr_set_rights(PVR, SPR_SR); |
| 2681 | /* IBAT0U (SPR 528) */ |
| 2682 | spr_set_rights(IBAT0U, SPR_SR | SPR_SW); |
| 2683 | /* IBAT0L (SPR 529) */ |
| 2684 | spr_set_rights(IBAT0L, SPR_SR | SPR_SW); |
| 2685 | /* IBAT1U (SPR 530) */ |
| 2686 | spr_set_rights(IBAT1U, SPR_SR | SPR_SW); |
| 2687 | /* IBAT1L (SPR 531) */ |
| 2688 | spr_set_rights(IBAT1L, SPR_SR | SPR_SW); |
| 2689 | /* IBAT2U (SPR 532) */ |
| 2690 | spr_set_rights(IBAT2U, SPR_SR | SPR_SW); |
| 2691 | /* IBAT2L (SPR 533) */ |
| 2692 | spr_set_rights(IBAT2L, SPR_SR | SPR_SW); |
| 2693 | /* IBAT3U (SPR 534) */ |
| 2694 | spr_set_rights(IBAT3U, SPR_SR | SPR_SW); |
| 2695 | /* IBAT3L (SPR 535) */ |
| 2696 | spr_set_rights(IBAT3L, SPR_SR | SPR_SW); |
| 2697 | /* DBAT0U (SPR 536) */ |
| 2698 | spr_set_rights(DBAT0U, SPR_SR | SPR_SW); |
| 2699 | /* DBAT0L (SPR 537) */ |
| 2700 | spr_set_rights(DBAT0L, SPR_SR | SPR_SW); |
| 2701 | /* DBAT1U (SPR 538) */ |
| 2702 | spr_set_rights(DBAT1U, SPR_SR | SPR_SW); |
| 2703 | /* DBAT1L (SPR 539) */ |
| 2704 | spr_set_rights(DBAT1L, SPR_SR | SPR_SW); |
| 2705 | /* DBAT2U (SPR 540) */ |
| 2706 | spr_set_rights(DBAT2U, SPR_SR | SPR_SW); |
| 2707 | /* DBAT2L (SPR 541) */ |
| 2708 | spr_set_rights(DBAT2L, SPR_SR | SPR_SW); |
| 2709 | /* DBAT3U (SPR 542) */ |
| 2710 | spr_set_rights(DBAT3U, SPR_SR | SPR_SW); |
| 2711 | /* DBAT3L (SPR 543) */ |
| 2712 | spr_set_rights(DBAT3L, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2713 | /* FPECR (SPR 1022) */ |
| 2714 | spr_set_rights(FPECR, SPR_SR | SPR_SW); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2715 | /* Special registers for PPC 604 */ |
| 2716 | if ((pvr & 0xFFFF0000) == 0x00040000) { |
| 2717 | /* IABR */ |
| 2718 | spr_set_rights(IABR , SPR_SR | SPR_SW); |
| 2719 | /* DABR (SPR 1013) */ |
| 2720 | spr_set_rights(DABR, SPR_SR | SPR_SW); |
| 2721 | /* HID0 */ |
| 2722 | spr_set_rights(HID0, SPR_SR | SPR_SW); |
| 2723 | /* PIR */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2724 | spr_set_rights(PIR, SPR_SR | SPR_SW); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2725 | /* PMC1 */ |
| 2726 | spr_set_rights(PMC1, SPR_SR | SPR_SW); |
| 2727 | /* PMC2 */ |
| 2728 | spr_set_rights(PMC2, SPR_SR | SPR_SW); |
| 2729 | /* MMCR0 */ |
| 2730 | spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
| 2731 | /* SIA */ |
| 2732 | spr_set_rights(SIA, SPR_SR | SPR_SW); |
| 2733 | /* SDA */ |
| 2734 | spr_set_rights(SDA, SPR_SR | SPR_SW); |
| 2735 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2736 | /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */ |
| 2737 | if ((pvr & 0xFFFF0000) == 0x00080000 || |
| 2738 | (pvr & 0xFFFF0000) == 0x70000000) { |
| 2739 | /* HID0 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2740 | spr_set_rights(HID0, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2741 | /* HID1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2742 | spr_set_rights(HID1, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2743 | /* IABR */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2744 | spr_set_rights(IABR, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2745 | /* ICTC */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2746 | spr_set_rights(ICTC, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2747 | /* L2CR */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2748 | spr_set_rights(L2CR, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2749 | /* MMCR0 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2750 | spr_set_rights(MMCR0, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2751 | /* MMCR1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2752 | spr_set_rights(MMCR1, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2753 | /* PMC1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2754 | spr_set_rights(PMC1, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2755 | /* PMC2 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2756 | spr_set_rights(PMC2, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2757 | /* PMC3 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2758 | spr_set_rights(PMC3, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2759 | /* PMC4 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2760 | spr_set_rights(PMC4, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2761 | /* SIA */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2762 | spr_set_rights(SIA, SPR_SR | SPR_SW); |
| 2763 | /* SDA */ |
| 2764 | spr_set_rights(SDA, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2765 | /* THRM1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2766 | spr_set_rights(THRM1, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2767 | /* THRM2 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2768 | spr_set_rights(THRM2, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2769 | /* THRM3 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2770 | spr_set_rights(THRM3, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2771 | /* UMMCR0 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2772 | spr_set_rights(UMMCR0, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2773 | /* UMMCR1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2774 | spr_set_rights(UMMCR1, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2775 | /* UPMC1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2776 | spr_set_rights(UPMC1, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2777 | /* UPMC2 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2778 | spr_set_rights(UPMC2, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2779 | /* UPMC3 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2780 | spr_set_rights(UPMC3, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2781 | /* UPMC4 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2782 | spr_set_rights(UPMC4, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2783 | /* USIA */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2784 | spr_set_rights(USIA, SPR_UR | SPR_UW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2785 | } |
| 2786 | /* MPC755 has special registers */ |
| 2787 | if (pvr == 0x00083100) { |
| 2788 | /* SPRG4 */ |
| 2789 | spr_set_rights(SPRG4, SPR_SR | SPR_SW); |
| 2790 | /* SPRG5 */ |
| 2791 | spr_set_rights(SPRG5, SPR_SR | SPR_SW); |
| 2792 | /* SPRG6 */ |
| 2793 | spr_set_rights(SPRG6, SPR_SR | SPR_SW); |
| 2794 | /* SPRG7 */ |
| 2795 | spr_set_rights(SPRG7, SPR_SR | SPR_SW); |
| 2796 | /* IBAT4U */ |
| 2797 | spr_set_rights(IBAT4U, SPR_SR | SPR_SW); |
| 2798 | /* IBAT4L */ |
| 2799 | spr_set_rights(IBAT4L, SPR_SR | SPR_SW); |
| 2800 | /* IBAT5U */ |
| 2801 | spr_set_rights(IBAT5U, SPR_SR | SPR_SW); |
| 2802 | /* IBAT5L */ |
| 2803 | spr_set_rights(IBAT5L, SPR_SR | SPR_SW); |
| 2804 | /* IBAT6U */ |
| 2805 | spr_set_rights(IBAT6U, SPR_SR | SPR_SW); |
| 2806 | /* IBAT6L */ |
| 2807 | spr_set_rights(IBAT6L, SPR_SR | SPR_SW); |
| 2808 | /* IBAT7U */ |
| 2809 | spr_set_rights(IBAT7U, SPR_SR | SPR_SW); |
| 2810 | /* IBAT7L */ |
| 2811 | spr_set_rights(IBAT7L, SPR_SR | SPR_SW); |
| 2812 | /* DBAT4U */ |
| 2813 | spr_set_rights(DBAT4U, SPR_SR | SPR_SW); |
| 2814 | /* DBAT4L */ |
| 2815 | spr_set_rights(DBAT4L, SPR_SR | SPR_SW); |
| 2816 | /* DBAT5U */ |
| 2817 | spr_set_rights(DBAT5U, SPR_SR | SPR_SW); |
| 2818 | /* DBAT5L */ |
| 2819 | spr_set_rights(DBAT5L, SPR_SR | SPR_SW); |
| 2820 | /* DBAT6U */ |
| 2821 | spr_set_rights(DBAT6U, SPR_SR | SPR_SW); |
| 2822 | /* DBAT6L */ |
| 2823 | spr_set_rights(DBAT6L, SPR_SR | SPR_SW); |
| 2824 | /* DBAT7U */ |
| 2825 | spr_set_rights(DBAT7U, SPR_SR | SPR_SW); |
| 2826 | /* DBAT7L */ |
| 2827 | spr_set_rights(DBAT7L, SPR_SR | SPR_SW); |
| 2828 | /* DMISS */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2829 | spr_set_rights(DMISS, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2830 | /* DCMP */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2831 | spr_set_rights(DCMP, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2832 | /* DHASH1 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2833 | spr_set_rights(DHASH1, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2834 | /* DHASH2 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2835 | spr_set_rights(DHASH2, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2836 | /* IMISS */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2837 | spr_set_rights(IMISS, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2838 | /* ICMP */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2839 | spr_set_rights(ICMP, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2840 | /* RPA */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2841 | spr_set_rights(RPA, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2842 | /* HID2 */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2843 | spr_set_rights(HID2, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2844 | /* L2PM */ |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2845 | spr_set_rights(L2PM, SPR_SR | SPR_SW); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2846 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2847 | } |
| 2848 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2849 | /*****************************************************************************/ |
| 2850 | /* PPC "main stream" common instructions (no optional ones) */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2851 | |
| 2852 | typedef struct ppc_proc_t { |
| 2853 | int flags; |
| 2854 | void *specific; |
| 2855 | } ppc_proc_t; |
| 2856 | |
| 2857 | typedef struct ppc_def_t { |
| 2858 | unsigned long pvr; |
| 2859 | unsigned long pvr_mask; |
| 2860 | ppc_proc_t *proc; |
| 2861 | } ppc_def_t; |
| 2862 | |
| 2863 | static ppc_proc_t ppc_proc_common = { |
| 2864 | .flags = PPC_COMMON, |
| 2865 | .specific = NULL, |
| 2866 | }; |
| 2867 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2868 | static ppc_proc_t ppc_proc_G3 = { |
| 2869 | .flags = PPC_750, |
| 2870 | .specific = NULL, |
| 2871 | }; |
| 2872 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2873 | static ppc_def_t ppc_defs[] = |
| 2874 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2875 | /* MPC740/745/750/755 (G3) */ |
| 2876 | { |
| 2877 | .pvr = 0x00080000, |
| 2878 | .pvr_mask = 0xFFFF0000, |
| 2879 | .proc = &ppc_proc_G3, |
| 2880 | }, |
| 2881 | /* IBM 750FX (G3 embedded) */ |
| 2882 | { |
| 2883 | .pvr = 0x70000000, |
| 2884 | .pvr_mask = 0xFFFF0000, |
| 2885 | .proc = &ppc_proc_G3, |
| 2886 | }, |
| 2887 | /* Fallback (generic PPC) */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2888 | { |
| 2889 | .pvr = 0x00000000, |
| 2890 | .pvr_mask = 0x00000000, |
| 2891 | .proc = &ppc_proc_common, |
| 2892 | }, |
| 2893 | }; |
| 2894 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2895 | static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2896 | { |
| 2897 | opcode_t *opc; |
| 2898 | int i, flags; |
| 2899 | |
| 2900 | fill_new_table(ppc_opcodes, 0x40); |
| 2901 | for (i = 0; ; i++) { |
| 2902 | if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) == |
| 2903 | (pvr & ppc_defs[i].pvr_mask)) { |
| 2904 | flags = ppc_defs[i].proc->flags; |
| 2905 | break; |
| 2906 | } |
| 2907 | } |
| 2908 | |
| 2909 | for (opc = &opc_start + 1; opc != &opc_end; opc++) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2910 | if ((opc->handler.type & flags) != 0) |
| 2911 | if (register_insn(ppc_opcodes, opc) < 0) { |
| 2912 | printf("*** ERROR initializing PPC instruction " |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2913 | "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2, |
| 2914 | opc->opc3); |
| 2915 | return -1; |
| 2916 | } |
| 2917 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2918 | fix_opcode_tables(ppc_opcodes); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2919 | |
| 2920 | return 0; |
| 2921 | } |
| 2922 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2923 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2924 | /*****************************************************************************/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2925 | /* Misc PPC helpers */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2926 | |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2927 | void cpu_dump_state(CPUState *env, FILE *f, |
| 2928 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 2929 | int flags) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2930 | { |
| 2931 | int i; |
| 2932 | |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2933 | cpu_fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x " |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2934 | "MSR=0x%08x\n", env->nip, env->lr, env->ctr, |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 2935 | _load_xer(env), _load_msr(env)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2936 | for (i = 0; i < 32; i++) { |
| 2937 | if ((i & 7) == 0) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2938 | cpu_fprintf(f, "GPR%02d:", i); |
| 2939 | cpu_fprintf(f, " %08x", env->gpr[i]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2940 | if ((i & 7) == 7) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2941 | cpu_fprintf(f, "\n"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2942 | } |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2943 | cpu_fprintf(f, "CR: 0x"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2944 | for (i = 0; i < 8; i++) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2945 | cpu_fprintf(f, "%01x", env->crf[i]); |
| 2946 | cpu_fprintf(f, " ["); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2947 | for (i = 0; i < 8; i++) { |
| 2948 | char a = '-'; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2949 | if (env->crf[i] & 0x08) |
| 2950 | a = 'L'; |
| 2951 | else if (env->crf[i] & 0x04) |
| 2952 | a = 'G'; |
| 2953 | else if (env->crf[i] & 0x02) |
| 2954 | a = 'E'; |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2955 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2956 | } |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2957 | cpu_fprintf(f, " ] "); |
| 2958 | cpu_fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env), |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2959 | cpu_ppc_load_tbl(env)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2960 | for (i = 0; i < 16; i++) { |
| 2961 | if ((i & 3) == 0) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2962 | cpu_fprintf(f, "FPR%02d:", i); |
| 2963 | cpu_fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i])); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2964 | if ((i & 3) == 3) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2965 | cpu_fprintf(f, "\n"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2966 | } |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2967 | cpu_fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n", |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2968 | env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env)); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 2969 | cpu_fprintf(f, "reservation 0x%08x\n", env->reserve); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2970 | } |
| 2971 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2972 | #if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE) |
| 2973 | int setup_machine (CPUPPCState *env, uint32_t mid); |
| 2974 | #endif |
| 2975 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2976 | CPUPPCState *cpu_ppc_init(void) |
| 2977 | { |
| 2978 | CPUPPCState *env; |
| 2979 | |
| 2980 | cpu_exec_init(); |
| 2981 | |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2982 | env = qemu_mallocz(sizeof(CPUPPCState)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2983 | if (!env) |
| 2984 | return NULL; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2985 | #if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE) |
| 2986 | setup_machine(env, 0); |
| 2987 | #else |
| 2988 | // env->spr[PVR] = 0; /* Basic PPC */ |
| 2989 | env->spr[PVR] = 0x00080100; /* G3 CPU */ |
| 2990 | // env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */ |
| 2991 | // env->spr[PVR] = 0x00070100; /* IBM 750FX */ |
| 2992 | #endif |
bellard | ad08132 | 2004-02-03 23:39:42 +0000 | [diff] [blame] | 2993 | tlb_flush(env, 1); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2994 | #if defined (DO_SINGLE_STEP) |
| 2995 | /* Single step trace mode */ |
| 2996 | msr_se = 1; |
| 2997 | #endif |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 2998 | msr_fp = 1; /* Allow floating point exceptions */ |
| 2999 | msr_me = 1; /* Allow machine check exceptions */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3000 | #if defined(CONFIG_USER_ONLY) |
| 3001 | msr_pr = 1; |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3002 | cpu_ppc_register(env, 0x00080000); |
| 3003 | #else |
| 3004 | env->nip = 0xFFFFFFFC; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3005 | #endif |
bellard | 7496f52 | 2004-06-22 10:56:50 +0000 | [diff] [blame] | 3006 | cpu_single_env = env; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3007 | return env; |
| 3008 | } |
| 3009 | |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3010 | int cpu_ppc_register (CPUPPCState *env, uint32_t pvr) |
| 3011 | { |
| 3012 | env->spr[PVR] = pvr; |
| 3013 | if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0) |
| 3014 | return -1; |
| 3015 | init_spr_rights(env->spr[PVR]); |
| 3016 | |
| 3017 | return 0; |
| 3018 | } |
| 3019 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3020 | void cpu_ppc_close(CPUPPCState *env) |
| 3021 | { |
| 3022 | /* Should also remove all opcode tables... */ |
| 3023 | free(env); |
| 3024 | } |
| 3025 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3026 | /*****************************************************************************/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3027 | int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, |
| 3028 | int search_pc) |
| 3029 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3030 | DisasContext ctx, *ctxp = &ctx; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3031 | opc_handler_t **table, *handler; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 3032 | target_ulong pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3033 | uint16_t *gen_opc_end; |
| 3034 | int j, lj = -1; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3035 | |
| 3036 | pc_start = tb->pc; |
| 3037 | gen_opc_ptr = gen_opc_buf; |
| 3038 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
| 3039 | gen_opparam_ptr = gen_opparam_buf; |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3040 | ctx.nip = pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3041 | ctx.tb = tb; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3042 | ctx.exception = EXCP_NONE; |
| 3043 | #if defined(CONFIG_USER_ONLY) |
| 3044 | ctx.mem_idx = 0; |
| 3045 | #else |
| 3046 | ctx.supervisor = 1 - msr_pr; |
| 3047 | ctx.mem_idx = (1 - msr_pr); |
| 3048 | #endif |
| 3049 | #if defined (DO_SINGLE_STEP) |
| 3050 | /* Single step trace mode */ |
| 3051 | msr_se = 1; |
| 3052 | #endif |
| 3053 | /* Set env in case of segfault during code fetch */ |
| 3054 | while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3055 | if (search_pc) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3056 | j = gen_opc_ptr - gen_opc_buf; |
| 3057 | if (lj < j) { |
| 3058 | lj++; |
| 3059 | while (lj < j) |
| 3060 | gen_opc_instr_start[lj++] = 0; |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3061 | gen_opc_pc[lj] = ctx.nip; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3062 | gen_opc_instr_start[lj] = 1; |
| 3063 | } |
| 3064 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3065 | #if defined PPC_DEBUG_DISAS |
| 3066 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3067 | fprintf(logfile, "----------------\n"); |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3068 | fprintf(logfile, "nip=%08x super=%d ir=%d\n", |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3069 | ctx.nip, 1 - msr_pr, msr_ir); |
| 3070 | } |
| 3071 | #endif |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 3072 | ctx.opcode = ldl_code(ctx.nip); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3073 | #if defined PPC_DEBUG_DISAS |
| 3074 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3075 | fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n", |
| 3076 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
| 3077 | opc3(ctx.opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3078 | } |
| 3079 | #endif |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3080 | ctx.nip += 4; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3081 | table = ppc_opcodes; |
| 3082 | handler = table[opc1(ctx.opcode)]; |
| 3083 | if (is_indirect_opcode(handler)) { |
| 3084 | table = ind_table(handler); |
| 3085 | handler = table[opc2(ctx.opcode)]; |
| 3086 | if (is_indirect_opcode(handler)) { |
| 3087 | table = ind_table(handler); |
| 3088 | handler = table[opc3(ctx.opcode)]; |
| 3089 | } |
| 3090 | } |
| 3091 | /* Is opcode *REALLY* valid ? */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3092 | if (handler->handler == &gen_invalid) { |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3093 | if (loglevel > 0) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3094 | fprintf(logfile, "invalid/unsupported opcode: " |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3095 | "%02x - %02x - %02x (%08x) 0x%08x %d\n", |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3096 | opc1(ctx.opcode), opc2(ctx.opcode), |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3097 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir); |
| 3098 | } else { |
| 3099 | printf("invalid/unsupported opcode: " |
| 3100 | "%02x - %02x - %02x (%08x) 0x%08x %d\n", |
| 3101 | opc1(ctx.opcode), opc2(ctx.opcode), |
| 3102 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir); |
| 3103 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3104 | } else { |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3105 | if ((ctx.opcode & handler->inval) != 0) { |
| 3106 | if (loglevel > 0) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3107 | fprintf(logfile, "invalid bits: %08x for opcode: " |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3108 | "%02x -%02x - %02x (0x%08x) (0x%08x)\n", |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3109 | ctx.opcode & handler->inval, opc1(ctx.opcode), |
| 3110 | opc2(ctx.opcode), opc3(ctx.opcode), |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3111 | ctx.opcode, ctx.nip - 4); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3112 | } else { |
| 3113 | printf("invalid bits: %08x for opcode: " |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3114 | "%02x -%02x - %02x (0x%08x) (0x%08x)\n", |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3115 | ctx.opcode & handler->inval, opc1(ctx.opcode), |
| 3116 | opc2(ctx.opcode), opc3(ctx.opcode), |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3117 | ctx.opcode, ctx.nip - 4); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3118 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3119 | RET_INVAL(ctxp); |
| 3120 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3121 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3122 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3123 | (*(handler->handler))(&ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3124 | /* Check trace mode exceptions */ |
| 3125 | if ((msr_be && ctx.exception == EXCP_BRANCH) || |
| 3126 | /* Check in single step trace mode |
| 3127 | * we need to stop except if: |
| 3128 | * - rfi, trap or syscall |
| 3129 | * - first instruction of an exception handler |
| 3130 | */ |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3131 | (msr_se && (ctx.nip < 0x100 || |
| 3132 | ctx.nip > 0xF00 || |
| 3133 | (ctx.nip & 0xFC) != 0x04) && |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3134 | ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI && |
| 3135 | ctx.exception != EXCP_TRAP)) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3136 | RET_EXCP(ctxp, EXCP_TRACE, 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3137 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 3138 | /* if we reach a page boundary, stop generation */ |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3139 | if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3140 | RET_EXCP(ctxp, EXCP_BRANCH, 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3141 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3142 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3143 | if (ctx.exception == EXCP_NONE) { |
| 3144 | gen_op_b((unsigned long)ctx.tb, ctx.nip); |
| 3145 | } else if (ctx.exception != EXCP_BRANCH) { |
| 3146 | gen_op_set_T0(0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3147 | } |
| 3148 | #if 1 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3149 | /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump |
| 3150 | * do bad business and then qemu crashes ! |
| 3151 | */ |
| 3152 | gen_op_set_T0(0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3153 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3154 | /* Generate the return instruction */ |
| 3155 | gen_op_exit_tb(); |
| 3156 | *gen_opc_ptr = INDEX_op_end; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3157 | if (search_pc) { |
| 3158 | j = gen_opc_ptr - gen_opc_buf; |
| 3159 | lj++; |
| 3160 | while (lj <= j) |
| 3161 | gen_opc_instr_start[lj++] = 0; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3162 | tb->size = 0; |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 3163 | #if 0 |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3164 | if (loglevel > 0) { |
| 3165 | page_dump(logfile); |
| 3166 | } |
bellard | 985a19d | 2004-01-18 22:49:57 +0000 | [diff] [blame] | 3167 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3168 | } else { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3169 | tb->size = ctx.nip - pc_start; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3170 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3171 | #ifdef DEBUG_DISAS |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3172 | if (loglevel & CPU_LOG_TB_CPU) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3173 | fprintf(logfile, "---------------- excp: %04x\n", ctx.exception); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 3174 | cpu_dump_state(env, logfile, fprintf, 0); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3175 | } |
| 3176 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 3177 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
| 3178 | target_disas(logfile, pc_start, ctx.nip - pc_start, 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3179 | fprintf(logfile, "\n"); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3180 | } |
| 3181 | if (loglevel & CPU_LOG_TB_OP) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3182 | fprintf(logfile, "OP:\n"); |
| 3183 | dump_ops(gen_opc_buf, gen_opparam_buf); |
| 3184 | fprintf(logfile, "\n"); |
| 3185 | } |
| 3186 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3187 | return 0; |
| 3188 | } |
| 3189 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3190 | int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3191 | { |
| 3192 | return gen_intermediate_code_internal(env, tb, 0); |
| 3193 | } |
| 3194 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3195 | int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3196 | { |
| 3197 | return gen_intermediate_code_internal(env, tb, 1); |
| 3198 | } |