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Blue Swirl5918fff2012-04-29 12:21:21 +00001/*
2 * x86 condition code helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "cpu.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070021#include "exec/helper-proto.h"
Blue Swirl5918fff2012-04-29 12:21:21 +000022
23const uint8_t parity_table[256] = {
24 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
25 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
26 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
27 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
28 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
29 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
30 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
31 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
32 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
33 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
34 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
37 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
41 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
42 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
43 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
44 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
45 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
46 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
47 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
48 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
49 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
53 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56};
57
58#define SHIFT 0
59#include "cc_helper_template.h"
60#undef SHIFT
61
62#define SHIFT 1
63#include "cc_helper_template.h"
64#undef SHIFT
65
66#define SHIFT 2
67#include "cc_helper_template.h"
68#undef SHIFT
69
70#ifdef TARGET_X86_64
71
72#define SHIFT 3
73#include "cc_helper_template.h"
74#undef SHIFT
75
76#endif
77
Richard Hendersoncd7f97c2013-01-23 18:17:33 -080078static target_ulong compute_all_adcx(target_ulong dst, target_ulong src1,
79 target_ulong src2)
80{
81 return (src1 & ~CC_C) | (dst * CC_C);
82}
83
84static target_ulong compute_all_adox(target_ulong dst, target_ulong src1,
85 target_ulong src2)
86{
87 return (src1 & ~CC_O) | (src2 * CC_O);
88}
89
90static target_ulong compute_all_adcox(target_ulong dst, target_ulong src1,
91 target_ulong src2)
92{
93 return (src1 & ~(CC_C | CC_O)) | (dst * CC_C) | (src2 * CC_O);
94}
95
Richard Henderson988c3eb2013-01-23 16:03:16 -080096target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
97 target_ulong src2, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +000098{
99 switch (op) {
100 default: /* should never happen */
101 return 0;
102
103 case CC_OP_EFLAGS:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800104 return src1;
Richard Henderson436ff2d2013-01-29 13:38:43 -0800105 case CC_OP_CLR:
Richard Hendersond2fe51b2014-01-10 12:38:40 -0800106 return CC_Z | CC_P;
Blue Swirl5918fff2012-04-29 12:21:21 +0000107
108 case CC_OP_MULB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800109 return compute_all_mulb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000110 case CC_OP_MULW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800111 return compute_all_mulw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000112 case CC_OP_MULL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800113 return compute_all_mull(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000114
115 case CC_OP_ADDB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800116 return compute_all_addb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000117 case CC_OP_ADDW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800118 return compute_all_addw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000119 case CC_OP_ADDL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800120 return compute_all_addl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000121
122 case CC_OP_ADCB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800123 return compute_all_adcb(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000124 case CC_OP_ADCW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800125 return compute_all_adcw(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000126 case CC_OP_ADCL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800127 return compute_all_adcl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000128
129 case CC_OP_SUBB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800130 return compute_all_subb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000131 case CC_OP_SUBW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800132 return compute_all_subw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000133 case CC_OP_SUBL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800134 return compute_all_subl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000135
136 case CC_OP_SBBB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800137 return compute_all_sbbb(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000138 case CC_OP_SBBW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800139 return compute_all_sbbw(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000140 case CC_OP_SBBL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800141 return compute_all_sbbl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000142
143 case CC_OP_LOGICB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800144 return compute_all_logicb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000145 case CC_OP_LOGICW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800146 return compute_all_logicw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000147 case CC_OP_LOGICL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800148 return compute_all_logicl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000149
150 case CC_OP_INCB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800151 return compute_all_incb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000152 case CC_OP_INCW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800153 return compute_all_incw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000154 case CC_OP_INCL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800155 return compute_all_incl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000156
157 case CC_OP_DECB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800158 return compute_all_decb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000159 case CC_OP_DECW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800160 return compute_all_decw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000161 case CC_OP_DECL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800162 return compute_all_decl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000163
164 case CC_OP_SHLB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800165 return compute_all_shlb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000166 case CC_OP_SHLW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800167 return compute_all_shlw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000168 case CC_OP_SHLL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800169 return compute_all_shll(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000170
171 case CC_OP_SARB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800172 return compute_all_sarb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000173 case CC_OP_SARW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800174 return compute_all_sarw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000175 case CC_OP_SARL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800176 return compute_all_sarl(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000177
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800178 case CC_OP_BMILGB:
179 return compute_all_bmilgb(dst, src1);
180 case CC_OP_BMILGW:
181 return compute_all_bmilgw(dst, src1);
182 case CC_OP_BMILGL:
183 return compute_all_bmilgl(dst, src1);
184
Richard Hendersoncd7f97c2013-01-23 18:17:33 -0800185 case CC_OP_ADCX:
186 return compute_all_adcx(dst, src1, src2);
187 case CC_OP_ADOX:
188 return compute_all_adox(dst, src1, src2);
189 case CC_OP_ADCOX:
190 return compute_all_adcox(dst, src1, src2);
191
Blue Swirl5918fff2012-04-29 12:21:21 +0000192#ifdef TARGET_X86_64
193 case CC_OP_MULQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800194 return compute_all_mulq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000195 case CC_OP_ADDQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800196 return compute_all_addq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000197 case CC_OP_ADCQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800198 return compute_all_adcq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000199 case CC_OP_SUBQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800200 return compute_all_subq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000201 case CC_OP_SBBQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800202 return compute_all_sbbq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000203 case CC_OP_LOGICQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800204 return compute_all_logicq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000205 case CC_OP_INCQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800206 return compute_all_incq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000207 case CC_OP_DECQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800208 return compute_all_decq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000209 case CC_OP_SHLQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800210 return compute_all_shlq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000211 case CC_OP_SARQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800212 return compute_all_sarq(dst, src1);
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800213 case CC_OP_BMILGQ:
214 return compute_all_bmilgq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000215#endif
216 }
217}
218
Blue Swirlf0967a12012-04-29 12:45:34 +0000219uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +0000220{
Richard Henderson988c3eb2013-01-23 16:03:16 -0800221 return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
Blue Swirl5918fff2012-04-29 12:21:21 +0000222}
223
Richard Henderson988c3eb2013-01-23 16:03:16 -0800224target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
225 target_ulong src2, int op)
Blue Swirl5918fff2012-04-29 12:21:21 +0000226{
227 switch (op) {
228 default: /* should never happen */
Richard Henderson8601c0b2013-01-23 16:06:38 -0800229 case CC_OP_LOGICB:
230 case CC_OP_LOGICW:
231 case CC_OP_LOGICL:
232 case CC_OP_LOGICQ:
Richard Henderson436ff2d2013-01-29 13:38:43 -0800233 case CC_OP_CLR:
Blue Swirl5918fff2012-04-29 12:21:21 +0000234 return 0;
235
236 case CC_OP_EFLAGS:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800237 case CC_OP_SARB:
238 case CC_OP_SARW:
239 case CC_OP_SARL:
240 case CC_OP_SARQ:
Richard Hendersoncd7f97c2013-01-23 18:17:33 -0800241 case CC_OP_ADOX:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800242 return src1 & 1;
Blue Swirl5918fff2012-04-29 12:21:21 +0000243
244 case CC_OP_INCB:
Blue Swirl5918fff2012-04-29 12:21:21 +0000245 case CC_OP_INCW:
Blue Swirl5918fff2012-04-29 12:21:21 +0000246 case CC_OP_INCL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800247 case CC_OP_INCQ:
Blue Swirl5918fff2012-04-29 12:21:21 +0000248 case CC_OP_DECB:
Blue Swirl5918fff2012-04-29 12:21:21 +0000249 case CC_OP_DECW:
Blue Swirl5918fff2012-04-29 12:21:21 +0000250 case CC_OP_DECL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800251 case CC_OP_DECQ:
252 return src1;
253
254 case CC_OP_MULB:
255 case CC_OP_MULW:
256 case CC_OP_MULL:
257 case CC_OP_MULQ:
258 return src1 != 0;
259
Richard Hendersoncd7f97c2013-01-23 18:17:33 -0800260 case CC_OP_ADCX:
261 case CC_OP_ADCOX:
262 return dst;
263
Richard Henderson8601c0b2013-01-23 16:06:38 -0800264 case CC_OP_ADDB:
265 return compute_c_addb(dst, src1);
266 case CC_OP_ADDW:
267 return compute_c_addw(dst, src1);
268 case CC_OP_ADDL:
269 return compute_c_addl(dst, src1);
270
271 case CC_OP_ADCB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800272 return compute_c_adcb(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800273 case CC_OP_ADCW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800274 return compute_c_adcw(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800275 case CC_OP_ADCL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800276 return compute_c_adcl(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800277
278 case CC_OP_SUBB:
279 return compute_c_subb(dst, src1);
280 case CC_OP_SUBW:
281 return compute_c_subw(dst, src1);
282 case CC_OP_SUBL:
283 return compute_c_subl(dst, src1);
284
285 case CC_OP_SBBB:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800286 return compute_c_sbbb(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800287 case CC_OP_SBBW:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800288 return compute_c_sbbw(dst, src1, src2);
Richard Henderson8601c0b2013-01-23 16:06:38 -0800289 case CC_OP_SBBL:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800290 return compute_c_sbbl(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000291
292 case CC_OP_SHLB:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800293 return compute_c_shlb(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000294 case CC_OP_SHLW:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800295 return compute_c_shlw(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000296 case CC_OP_SHLL:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800297 return compute_c_shll(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000298
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800299 case CC_OP_BMILGB:
300 return compute_c_bmilgb(dst, src1);
301 case CC_OP_BMILGW:
302 return compute_c_bmilgw(dst, src1);
303 case CC_OP_BMILGL:
304 return compute_c_bmilgl(dst, src1);
305
Blue Swirl5918fff2012-04-29 12:21:21 +0000306#ifdef TARGET_X86_64
Blue Swirl5918fff2012-04-29 12:21:21 +0000307 case CC_OP_ADDQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800308 return compute_c_addq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000309 case CC_OP_ADCQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800310 return compute_c_adcq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000311 case CC_OP_SUBQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800312 return compute_c_subq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000313 case CC_OP_SBBQ:
Richard Henderson988c3eb2013-01-23 16:03:16 -0800314 return compute_c_sbbq(dst, src1, src2);
Blue Swirl5918fff2012-04-29 12:21:21 +0000315 case CC_OP_SHLQ:
Richard Henderson8601c0b2013-01-23 16:06:38 -0800316 return compute_c_shlq(dst, src1);
Richard Hendersonbc4b43d2013-01-23 16:44:37 -0800317 case CC_OP_BMILGQ:
318 return compute_c_bmilgq(dst, src1);
Blue Swirl5918fff2012-04-29 12:21:21 +0000319#endif
320 }
321}
322
Blue Swirlf0967a12012-04-29 12:45:34 +0000323void helper_write_eflags(CPUX86State *env, target_ulong t0,
324 uint32_t update_mask)
Blue Swirl5918fff2012-04-29 12:21:21 +0000325{
326 cpu_load_eflags(env, t0, update_mask);
327}
328
Blue Swirlf0967a12012-04-29 12:45:34 +0000329target_ulong helper_read_eflags(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000330{
331 uint32_t eflags;
332
Richard Hendersondb9f2592013-01-23 16:10:49 -0800333 eflags = cpu_cc_compute_all(env, CC_OP);
liguang80cf2c82013-05-28 16:21:08 +0800334 eflags |= (env->df & DF_MASK);
Blue Swirl5918fff2012-04-29 12:21:21 +0000335 eflags |= env->eflags & ~(VM_MASK | RF_MASK);
336 return eflags;
337}
338
Blue Swirlf0967a12012-04-29 12:45:34 +0000339void helper_clts(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000340{
341 env->cr[0] &= ~CR0_TS_MASK;
342 env->hflags &= ~HF_TS_MASK;
343}
344
Blue Swirlf0967a12012-04-29 12:45:34 +0000345void helper_reset_rf(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000346{
347 env->eflags &= ~RF_MASK;
348}
349
Blue Swirlf0967a12012-04-29 12:45:34 +0000350void helper_cli(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000351{
352 env->eflags &= ~IF_MASK;
353}
354
Blue Swirlf0967a12012-04-29 12:45:34 +0000355void helper_sti(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000356{
357 env->eflags |= IF_MASK;
358}
359
H. Peter Anvina9321a42012-09-26 13:18:43 -0700360void helper_clac(CPUX86State *env)
361{
362 env->eflags &= ~AC_MASK;
363}
364
365void helper_stac(CPUX86State *env)
366{
367 env->eflags |= AC_MASK;
368}
369
Blue Swirl5918fff2012-04-29 12:21:21 +0000370#if 0
371/* vm86plus instructions */
Blue Swirlf0967a12012-04-29 12:45:34 +0000372void helper_cli_vm(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000373{
374 env->eflags &= ~VIF_MASK;
375}
376
Blue Swirlf0967a12012-04-29 12:45:34 +0000377void helper_sti_vm(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000378{
379 env->eflags |= VIF_MASK;
380 if (env->eflags & VIP_MASK) {
381 raise_exception(env, EXCP0D_GPF);
382 }
383}
384#endif
385
Blue Swirlf0967a12012-04-29 12:45:34 +0000386void helper_set_inhibit_irq(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000387{
388 env->hflags |= HF_INHIBIT_IRQ_MASK;
389}
390
Blue Swirlf0967a12012-04-29 12:45:34 +0000391void helper_reset_inhibit_irq(CPUX86State *env)
Blue Swirl5918fff2012-04-29 12:21:21 +0000392{
393 env->hflags &= ~HF_INHIBIT_IRQ_MASK;
394}