Chen Gang | 9f64170 | 2015-08-21 05:41:01 +0800 | [diff] [blame] | 1 | /* |
| 2 | * QEMU TILE-Gx CPU |
| 3 | * |
| 4 | * Copyright (c) 2015 Chen Gang |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see |
| 18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 19 | */ |
| 20 | |
Peter Maydell | b98ba68 | 2016-01-26 18:17:27 +0000 | [diff] [blame] | 21 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 22 | #include "qapi/error.h" |
Chen Gang | 9f64170 | 2015-08-21 05:41:01 +0800 | [diff] [blame] | 23 | #include "cpu.h" |
| 24 | #include "qemu-common.h" |
| 25 | #include "hw/qdev-properties.h" |
| 26 | #include "migration/vmstate.h" |
Richard Henderson | a0577d2 | 2015-09-27 14:26:04 -0700 | [diff] [blame] | 27 | #include "linux-user/syscall_defs.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 28 | #include "exec/exec-all.h" |
Chen Gang | 9f64170 | 2015-08-21 05:41:01 +0800 | [diff] [blame] | 29 | |
| 30 | static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, |
| 31 | fprintf_function cpu_fprintf, int flags) |
| 32 | { |
| 33 | static const char * const reg_names[TILEGX_R_COUNT] = { |
| 34 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 35 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 36 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 37 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 38 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
| 39 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", |
| 40 | "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr" |
| 41 | }; |
| 42 | |
| 43 | TileGXCPU *cpu = TILEGX_CPU(cs); |
| 44 | CPUTLGState *env = &cpu->env; |
| 45 | int i; |
| 46 | |
| 47 | for (i = 0; i < TILEGX_R_COUNT; i++) { |
| 48 | cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s", |
| 49 | reg_names[i], env->regs[i], |
| 50 | (i % 4) == 3 ? "\n" : " "); |
| 51 | } |
| 52 | cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n", |
| 53 | env->pc, env->spregs[TILEGX_SPR_CMPEXCH]); |
| 54 | } |
| 55 | |
| 56 | TileGXCPU *cpu_tilegx_init(const char *cpu_model) |
| 57 | { |
| 58 | TileGXCPU *cpu; |
| 59 | |
| 60 | cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU)); |
| 61 | |
| 62 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
| 63 | |
| 64 | return cpu; |
| 65 | } |
| 66 | |
| 67 | static void tilegx_cpu_set_pc(CPUState *cs, vaddr value) |
| 68 | { |
| 69 | TileGXCPU *cpu = TILEGX_CPU(cs); |
| 70 | |
| 71 | cpu->env.pc = value; |
| 72 | } |
| 73 | |
| 74 | static bool tilegx_cpu_has_work(CPUState *cs) |
| 75 | { |
| 76 | return true; |
| 77 | } |
| 78 | |
| 79 | static void tilegx_cpu_reset(CPUState *s) |
| 80 | { |
| 81 | TileGXCPU *cpu = TILEGX_CPU(s); |
| 82 | TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu); |
| 83 | CPUTLGState *env = &cpu->env; |
| 84 | |
| 85 | tcc->parent_reset(s); |
| 86 | |
| 87 | memset(env, 0, sizeof(CPUTLGState)); |
| 88 | tlb_flush(s, 1); |
| 89 | } |
| 90 | |
| 91 | static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp) |
| 92 | { |
| 93 | CPUState *cs = CPU(dev); |
| 94 | TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev); |
| 95 | |
| 96 | cpu_reset(cs); |
| 97 | qemu_init_vcpu(cs); |
| 98 | |
| 99 | tcc->parent_realize(dev, errp); |
| 100 | } |
| 101 | |
| 102 | static void tilegx_cpu_initfn(Object *obj) |
| 103 | { |
| 104 | CPUState *cs = CPU(obj); |
| 105 | TileGXCPU *cpu = TILEGX_CPU(obj); |
| 106 | CPUTLGState *env = &cpu->env; |
| 107 | static bool tcg_initialized; |
| 108 | |
| 109 | cs->env_ptr = env; |
| 110 | cpu_exec_init(cs, &error_abort); |
| 111 | |
| 112 | if (tcg_enabled() && !tcg_initialized) { |
| 113 | tcg_initialized = true; |
| 114 | tilegx_tcg_init(); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void tilegx_cpu_do_interrupt(CPUState *cs) |
| 119 | { |
| 120 | cs->exception_index = -1; |
| 121 | } |
| 122 | |
| 123 | static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
| 124 | int mmu_idx) |
| 125 | { |
Richard Henderson | 9b9dc7a | 2015-08-21 11:49:38 -0700 | [diff] [blame] | 126 | TileGXCPU *cpu = TILEGX_CPU(cs); |
| 127 | |
Richard Henderson | a0577d2 | 2015-09-27 14:26:04 -0700 | [diff] [blame] | 128 | /* The sigcode field will be filled in by do_signal in main.c. */ |
| 129 | cs->exception_index = TILEGX_EXCP_SIGNAL; |
Richard Henderson | 9b9dc7a | 2015-08-21 11:49:38 -0700 | [diff] [blame] | 130 | cpu->env.excaddr = address; |
Richard Henderson | a0577d2 | 2015-09-27 14:26:04 -0700 | [diff] [blame] | 131 | cpu->env.signo = TARGET_SIGSEGV; |
| 132 | cpu->env.sigcode = 0; |
| 133 | |
Chen Gang | 9f64170 | 2015-08-21 05:41:01 +0800 | [diff] [blame] | 134 | return 1; |
| 135 | } |
| 136 | |
| 137 | static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 138 | { |
| 139 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 140 | tilegx_cpu_do_interrupt(cs); |
| 141 | return true; |
| 142 | } |
| 143 | return false; |
| 144 | } |
| 145 | |
| 146 | static void tilegx_cpu_class_init(ObjectClass *oc, void *data) |
| 147 | { |
| 148 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 149 | CPUClass *cc = CPU_CLASS(oc); |
| 150 | TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc); |
| 151 | |
| 152 | tcc->parent_realize = dc->realize; |
| 153 | dc->realize = tilegx_cpu_realizefn; |
| 154 | |
| 155 | tcc->parent_reset = cc->reset; |
| 156 | cc->reset = tilegx_cpu_reset; |
| 157 | |
| 158 | cc->has_work = tilegx_cpu_has_work; |
| 159 | cc->do_interrupt = tilegx_cpu_do_interrupt; |
| 160 | cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt; |
| 161 | cc->dump_state = tilegx_cpu_dump_state; |
| 162 | cc->set_pc = tilegx_cpu_set_pc; |
| 163 | cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault; |
| 164 | cc->gdb_num_core_regs = 0; |
Markus Armbruster | 4c315c2 | 2015-10-01 10:59:58 +0200 | [diff] [blame] | 165 | |
| 166 | /* |
| 167 | * Reason: tilegx_cpu_initfn() calls cpu_exec_init(), which saves |
| 168 | * the object in cpus -> dangling pointer after final |
| 169 | * object_unref(). |
| 170 | */ |
| 171 | dc->cannot_destroy_with_object_finalize_yet = true; |
Chen Gang | 9f64170 | 2015-08-21 05:41:01 +0800 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | static const TypeInfo tilegx_cpu_type_info = { |
| 175 | .name = TYPE_TILEGX_CPU, |
| 176 | .parent = TYPE_CPU, |
| 177 | .instance_size = sizeof(TileGXCPU), |
| 178 | .instance_init = tilegx_cpu_initfn, |
| 179 | .class_size = sizeof(TileGXCPUClass), |
| 180 | .class_init = tilegx_cpu_class_init, |
| 181 | }; |
| 182 | |
| 183 | static void tilegx_cpu_register_types(void) |
| 184 | { |
| 185 | type_register_static(&tilegx_cpu_type_info); |
| 186 | } |
| 187 | |
| 188 | type_init(tilegx_cpu_register_types) |