Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU SPAPR Dynamic Reconfiguration Connector Implementation |
| 3 | * |
| 4 | * Copyright IBM Corp. 2014 |
| 5 | * |
| 6 | * Authors: |
| 7 | * Michael Roth <mdroth@linux.vnet.ibm.com> |
| 8 | * |
| 9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 10 | * See the COPYING file in the top-level directory. |
| 11 | */ |
| 12 | |
Peter Maydell | 0d75590 | 2016-01-26 18:16:58 +0000 | [diff] [blame] | 13 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 14 | #include "qapi/error.h" |
Markus Armbruster | 15280c3 | 2018-02-01 12:18:36 +0100 | [diff] [blame] | 15 | #include "qapi/qmp/qnull.h" |
Veronia Bahaa | f348b6d | 2016-03-20 19:16:19 +0200 | [diff] [blame] | 16 | #include "qemu/cutils.h" |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 17 | #include "hw/ppc/spapr_drc.h" |
| 18 | #include "qom/object.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 19 | #include "migration/vmstate.h" |
Daniel Henrique Barboza | 4b08cd5 | 2021-09-06 21:47:54 -0300 | [diff] [blame] | 20 | #include "qapi/error.h" |
| 21 | #include "qapi/qapi-events-qdev.h" |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 22 | #include "qapi/visitor.h" |
| 23 | #include "qemu/error-report.h" |
Michael Roth | 0cb688d | 2015-09-10 16:11:02 -0500 | [diff] [blame] | 24 | #include "hw/ppc/spapr.h" /* for RTAS return codes */ |
Daniel Henrique Barboza | 3183472 | 2017-05-22 16:35:48 -0300 | [diff] [blame] | 25 | #include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback */ |
Shivaprasad G Bhat | ee3a71e | 2020-02-09 22:56:31 -0600 | [diff] [blame] | 26 | #include "hw/ppc/spapr_nvdimm.h" |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 27 | #include "sysemu/device_tree.h" |
Markus Armbruster | 71e8a91 | 2019-08-12 07:23:38 +0200 | [diff] [blame] | 28 | #include "sysemu/reset.h" |
Laurent Vivier | 24ac775 | 2016-09-14 20:48:23 +0200 | [diff] [blame] | 29 | #include "trace.h" |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 30 | |
| 31 | #define DRC_CONTAINER_PATH "/dr-connector" |
| 32 | #define DRC_INDEX_TYPE_SHIFT 28 |
David Gibson | 627c2ef | 2015-09-03 10:08:23 +1000 | [diff] [blame] | 33 | #define DRC_INDEX_ID_MASK ((1ULL << DRC_INDEX_TYPE_SHIFT) - 1) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 34 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 35 | SpaprDrcType spapr_drc_type(SpaprDrc *drc) |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 36 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 37 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 38 | |
| 39 | return 1 << drck->typeshift; |
| 40 | } |
| 41 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 42 | uint32_t spapr_drc_index(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 43 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 44 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 45 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 46 | /* no set format for a drc index: it only needs to be globally |
| 47 | * unique. this is how we encode the DRC type on bare-metal |
| 48 | * however, so might as well do that here |
| 49 | */ |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 50 | return (drck->typeshift << DRC_INDEX_TYPE_SHIFT) |
| 51 | | (drc->id & DRC_INDEX_ID_MASK); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 52 | } |
| 53 | |
Daniel Henrique Barboza | 66d10d3 | 2021-02-22 16:45:27 -0300 | [diff] [blame] | 54 | static void spapr_drc_release(SpaprDrc *drc) |
| 55 | { |
| 56 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
| 57 | |
| 58 | drck->release(drc->dev); |
| 59 | |
| 60 | drc->unplug_requested = false; |
| 61 | g_free(drc->fdt); |
| 62 | drc->fdt = NULL; |
| 63 | drc->fdt_start_offset = 0; |
| 64 | object_property_del(OBJECT(drc), "device"); |
| 65 | drc->dev = NULL; |
| 66 | } |
| 67 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 68 | static uint32_t drc_isolate_physical(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 69 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 70 | switch (drc->state) { |
| 71 | case SPAPR_DRC_STATE_PHYSICAL_POWERON: |
| 72 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 73 | case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED: |
| 74 | break; /* see below */ |
| 75 | case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE: |
| 76 | return RTAS_OUT_PARAM_ERROR; /* not allowed */ |
| 77 | default: |
| 78 | g_assert_not_reached(); |
| 79 | } |
| 80 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 81 | drc->state = SPAPR_DRC_STATE_PHYSICAL_POWERON; |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 82 | |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 83 | if (drc->unplug_requested) { |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 84 | uint32_t drc_index = spapr_drc_index(drc); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 85 | trace_spapr_drc_set_isolation_state_finalizing(drc_index); |
Daniel Henrique Barboza | 66d10d3 | 2021-02-22 16:45:27 -0300 | [diff] [blame] | 86 | spapr_drc_release(drc); |
Michael Roth | 9d1852c | 2015-09-10 16:11:03 -0500 | [diff] [blame] | 87 | } |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 88 | |
| 89 | return RTAS_OUT_SUCCESS; |
| 90 | } |
| 91 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 92 | static uint32_t drc_unisolate_physical(SpaprDrc *drc) |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 93 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 94 | switch (drc->state) { |
| 95 | case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE: |
| 96 | case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED: |
| 97 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 98 | case SPAPR_DRC_STATE_PHYSICAL_POWERON: |
| 99 | break; /* see below */ |
| 100 | default: |
| 101 | g_assert_not_reached(); |
| 102 | } |
| 103 | |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 104 | /* cannot unisolate a non-existent resource, and, or resources |
| 105 | * which are in an 'UNUSABLE' allocation state. (PAPR 2.7, |
| 106 | * 13.5.3.5) |
| 107 | */ |
| 108 | if (!drc->dev) { |
| 109 | return RTAS_OUT_NO_SUCH_INDICATOR; |
| 110 | } |
| 111 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 112 | drc->state = SPAPR_DRC_STATE_PHYSICAL_UNISOLATE; |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 113 | drc->ccs_offset = drc->fdt_start_offset; |
| 114 | drc->ccs_depth = 0; |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 115 | |
| 116 | return RTAS_OUT_SUCCESS; |
| 117 | } |
| 118 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 119 | static uint32_t drc_isolate_logical(SpaprDrc *drc) |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 120 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 121 | switch (drc->state) { |
| 122 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
| 123 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: |
| 124 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 125 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: |
| 126 | break; /* see below */ |
| 127 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: |
| 128 | return RTAS_OUT_PARAM_ERROR; /* not allowed */ |
| 129 | default: |
| 130 | g_assert_not_reached(); |
| 131 | } |
| 132 | |
Bharata B Rao | cf63246 | 2016-10-26 21:20:30 -0500 | [diff] [blame] | 133 | /* |
| 134 | * Fail any requests to ISOLATE the LMB DRC if this LMB doesn't |
| 135 | * belong to a DIMM device that is marked for removal. |
| 136 | * |
| 137 | * Currently the guest userspace tool drmgr that drives the memory |
| 138 | * hotplug/unplug will just try to remove a set of 'removable' LMBs |
| 139 | * in response to a hot unplug request that is based on drc-count. |
| 140 | * If the LMB being removed doesn't belong to a DIMM device that is |
| 141 | * actually being unplugged, fail the isolation request here. |
| 142 | */ |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 143 | if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 144 | && !drc->unplug_requested) { |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 145 | return RTAS_OUT_HW_ERROR; |
Bharata B Rao | cf63246 | 2016-10-26 21:20:30 -0500 | [diff] [blame] | 146 | } |
| 147 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 148 | drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 149 | |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 150 | return RTAS_OUT_SUCCESS; |
| 151 | } |
| 152 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 153 | static uint32_t drc_unisolate_logical(SpaprDrc *drc) |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 154 | { |
Daniel Henrique Barboza | 87758fe | 2021-04-20 13:51:00 -0300 | [diff] [blame] | 155 | SpaprMachineState *spapr = NULL; |
| 156 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 157 | switch (drc->state) { |
| 158 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: |
| 159 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: |
Daniel Henrique Barboza | 87758fe | 2021-04-20 13:51:00 -0300 | [diff] [blame] | 160 | /* |
| 161 | * Unisolating a logical DRC that was marked for unplug |
| 162 | * means that the kernel is refusing the removal. |
| 163 | */ |
| 164 | if (drc->unplug_requested && drc->dev) { |
| 165 | if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB) { |
| 166 | spapr = SPAPR_MACHINE(qdev_get_machine()); |
| 167 | |
| 168 | spapr_memory_unplug_rollback(spapr, drc->dev); |
| 169 | } |
| 170 | |
| 171 | drc->unplug_requested = false; |
Daniel Henrique Barboza | 91bd95c | 2021-09-06 21:47:51 -0300 | [diff] [blame] | 172 | |
| 173 | if (drc->dev->id) { |
| 174 | error_report("Device hotunplug rejected by the guest " |
| 175 | "for device %s", drc->dev->id); |
| 176 | } |
Daniel Henrique Barboza | 87758fe | 2021-04-20 13:51:00 -0300 | [diff] [blame] | 177 | |
Daniel Henrique Barboza | 4b08cd5 | 2021-09-06 21:47:54 -0300 | [diff] [blame] | 178 | qapi_event_send_device_unplug_guest_error(!!drc->dev->id, |
| 179 | drc->dev->id, |
| 180 | drc->dev->canonical_path); |
Daniel Henrique Barboza | 87758fe | 2021-04-20 13:51:00 -0300 | [diff] [blame] | 181 | } |
| 182 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 183 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 184 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
| 185 | break; /* see below */ |
| 186 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: |
| 187 | return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */ |
| 188 | default: |
| 189 | g_assert_not_reached(); |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 190 | } |
| 191 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 192 | /* Move to AVAILABLE state should have ensured device was present */ |
| 193 | g_assert(drc->dev); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 194 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 195 | drc->state = SPAPR_DRC_STATE_LOGICAL_UNISOLATE; |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 196 | drc->ccs_offset = drc->fdt_start_offset; |
| 197 | drc->ccs_depth = 0; |
| 198 | |
Michael Roth | 0cb688d | 2015-09-10 16:11:02 -0500 | [diff] [blame] | 199 | return RTAS_OUT_SUCCESS; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 200 | } |
| 201 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 202 | static uint32_t drc_set_usable(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 203 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 204 | switch (drc->state) { |
| 205 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
| 206 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: |
| 207 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: |
| 208 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 209 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: |
| 210 | break; /* see below */ |
| 211 | default: |
| 212 | g_assert_not_reached(); |
| 213 | } |
| 214 | |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 215 | /* if there's no resource/device associated with the DRC, there's |
| 216 | * no way for us to put it in an allocation state consistent with |
| 217 | * being 'USABLE'. PAPR 2.7, 13.5.3.4 documents that this should |
| 218 | * result in an RTAS return code of -3 / "no such indicator" |
| 219 | */ |
| 220 | if (!drc->dev) { |
| 221 | return RTAS_OUT_NO_SUCH_INDICATOR; |
| 222 | } |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 223 | if (drc->unplug_requested) { |
David Gibson | 82a93a1 | 2017-07-03 20:20:53 +1000 | [diff] [blame] | 224 | /* Don't allow the guest to move a device away from UNUSABLE |
| 225 | * state when we want to unplug it */ |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 226 | return RTAS_OUT_NO_SUCH_INDICATOR; |
Michael Roth | 9d1852c | 2015-09-10 16:11:03 -0500 | [diff] [blame] | 227 | } |
| 228 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 229 | drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE; |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 230 | |
| 231 | return RTAS_OUT_SUCCESS; |
| 232 | } |
| 233 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 234 | static uint32_t drc_set_unusable(SpaprDrc *drc) |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 235 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 236 | switch (drc->state) { |
| 237 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: |
| 238 | return RTAS_OUT_SUCCESS; /* Nothing to do */ |
| 239 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
| 240 | break; /* see below */ |
| 241 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: |
| 242 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: |
| 243 | return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */ |
| 244 | default: |
| 245 | g_assert_not_reached(); |
| 246 | } |
| 247 | |
| 248 | drc->state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE; |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 249 | if (drc->unplug_requested) { |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 250 | uint32_t drc_index = spapr_drc_index(drc); |
| 251 | trace_spapr_drc_set_allocation_state_finalizing(drc_index); |
Daniel Henrique Barboza | 66d10d3 | 2021-02-22 16:45:27 -0300 | [diff] [blame] | 252 | spapr_drc_release(drc); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 253 | } |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 254 | |
Michael Roth | 0cb688d | 2015-09-10 16:11:02 -0500 | [diff] [blame] | 255 | return RTAS_OUT_SUCCESS; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 256 | } |
| 257 | |
Shivaprasad G Bhat | dbd26f2 | 2019-07-17 03:20:01 -0500 | [diff] [blame] | 258 | static char *spapr_drc_name(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 259 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 260 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | 7980833 | 2017-06-07 12:00:11 +1000 | [diff] [blame] | 261 | |
| 262 | /* human-readable name for a DRC to encode into the DT |
| 263 | * description. this is mainly only used within a guest in place |
| 264 | * of the unique DRC index. |
| 265 | * |
| 266 | * in the case of VIO/PCI devices, it corresponds to a "location |
| 267 | * code" that maps a logical device/function (DRC index) to a |
| 268 | * physical (or virtual in the case of VIO) location in the system |
| 269 | * by chaining together the "location label" for each |
| 270 | * encapsulating component. |
| 271 | * |
| 272 | * since this is more to do with diagnosing physical hardware |
| 273 | * issues than guest compatibility, we choose location codes/DRC |
| 274 | * names that adhere to the documented format, but avoid encoding |
| 275 | * the entire topology information into the label/code, instead |
| 276 | * just using the location codes based on the labels for the |
| 277 | * endpoints (VIO/PCI adaptor connectors), which is basically just |
| 278 | * "C" followed by an integer ID. |
| 279 | * |
| 280 | * DRC names as documented by PAPR+ v2.7, 13.5.2.4 |
| 281 | * location codes as documented by PAPR+ v2.7, 12.3.1.5 |
| 282 | */ |
| 283 | return g_strdup_printf("%s%d", drck->drc_name_prefix, drc->id); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 284 | } |
| 285 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 286 | /* |
| 287 | * dr-entity-sense sensor value |
| 288 | * returned via get-sensor-state RTAS calls |
| 289 | * as expected by state diagram in PAPR+ 2.7, 13.4 |
| 290 | * based on the current allocation/indicator/power states |
| 291 | * for the DR connector. |
| 292 | */ |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 293 | static SpaprDREntitySense physical_entity_sense(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 294 | { |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 295 | /* this assumes all PCI devices are assigned to a 'live insertion' |
| 296 | * power domain, where QEMU manages power state automatically as |
| 297 | * opposed to the guest. present, non-PCI resources are unaffected |
| 298 | * by power state. |
| 299 | */ |
| 300 | return drc->dev ? SPAPR_DR_ENTITY_SENSE_PRESENT |
| 301 | : SPAPR_DR_ENTITY_SENSE_EMPTY; |
| 302 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 303 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 304 | static SpaprDREntitySense logical_entity_sense(SpaprDrc *drc) |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 305 | { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 306 | switch (drc->state) { |
| 307 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 308 | return SPAPR_DR_ENTITY_SENSE_UNUSABLE; |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 309 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
| 310 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: |
| 311 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: |
| 312 | g_assert(drc->dev); |
| 313 | return SPAPR_DR_ENTITY_SENSE_PRESENT; |
| 314 | default: |
| 315 | g_assert_not_reached(); |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 316 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 317 | } |
| 318 | |
Eric Blake | d7bce99 | 2016-01-29 06:48:55 -0700 | [diff] [blame] | 319 | static void prop_get_index(Object *obj, Visitor *v, const char *name, |
| 320 | void *opaque, Error **errp) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 321 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 322 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 323 | uint32_t value = spapr_drc_index(drc); |
Eric Blake | 51e72bc | 2016-01-29 06:48:54 -0700 | [diff] [blame] | 324 | visit_type_uint32(v, name, &value, errp); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 325 | } |
| 326 | |
Eric Blake | d7bce99 | 2016-01-29 06:48:55 -0700 | [diff] [blame] | 327 | static void prop_get_fdt(Object *obj, Visitor *v, const char *name, |
| 328 | void *opaque, Error **errp) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 329 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 330 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
Markus Armbruster | d2f95f4 | 2017-06-26 18:22:59 +0200 | [diff] [blame] | 331 | QNull *null = NULL; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 332 | int fdt_offset_next, fdt_offset, fdt_depth; |
| 333 | void *fdt; |
| 334 | |
| 335 | if (!drc->fdt) { |
Markus Armbruster | d2f95f4 | 2017-06-26 18:22:59 +0200 | [diff] [blame] | 336 | visit_type_null(v, NULL, &null, errp); |
Marc-André Lureau | cb3e7f0 | 2018-04-19 17:01:43 +0200 | [diff] [blame] | 337 | qobject_unref(null); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 338 | return; |
| 339 | } |
| 340 | |
| 341 | fdt = drc->fdt; |
| 342 | fdt_offset = drc->fdt_start_offset; |
| 343 | fdt_depth = 0; |
| 344 | |
| 345 | do { |
| 346 | const char *name = NULL; |
| 347 | const struct fdt_property *prop = NULL; |
| 348 | int prop_len = 0, name_len = 0; |
| 349 | uint32_t tag; |
Greg Kurz | ebd226d | 2020-09-14 14:34:59 +0200 | [diff] [blame] | 350 | bool ok; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 351 | |
| 352 | tag = fdt_next_tag(fdt, fdt_offset, &fdt_offset_next); |
| 353 | switch (tag) { |
| 354 | case FDT_BEGIN_NODE: |
| 355 | fdt_depth++; |
| 356 | name = fdt_get_name(fdt, fdt_offset, &name_len); |
Markus Armbruster | 668f62e | 2020-07-07 18:06:02 +0200 | [diff] [blame] | 357 | if (!visit_start_struct(v, name, NULL, 0, errp)) { |
Markus Armbruster | c75304a | 2015-12-03 17:37:38 +0100 | [diff] [blame] | 358 | return; |
| 359 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 360 | break; |
| 361 | case FDT_END_NODE: |
| 362 | /* shouldn't ever see an FDT_END_NODE before FDT_BEGIN_NODE */ |
| 363 | g_assert(fdt_depth > 0); |
Greg Kurz | ebd226d | 2020-09-14 14:34:59 +0200 | [diff] [blame] | 364 | ok = visit_check_struct(v, errp); |
Eric Blake | 1158bb2 | 2016-06-09 10:48:34 -0600 | [diff] [blame] | 365 | visit_end_struct(v, NULL); |
Greg Kurz | ebd226d | 2020-09-14 14:34:59 +0200 | [diff] [blame] | 366 | if (!ok) { |
Markus Armbruster | c75304a | 2015-12-03 17:37:38 +0100 | [diff] [blame] | 367 | return; |
| 368 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 369 | fdt_depth--; |
| 370 | break; |
| 371 | case FDT_PROP: { |
| 372 | int i; |
| 373 | prop = fdt_get_property_by_offset(fdt, fdt_offset, &prop_len); |
| 374 | name = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); |
Markus Armbruster | 668f62e | 2020-07-07 18:06:02 +0200 | [diff] [blame] | 375 | if (!visit_start_list(v, name, NULL, 0, errp)) { |
Markus Armbruster | c75304a | 2015-12-03 17:37:38 +0100 | [diff] [blame] | 376 | return; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 377 | } |
Markus Armbruster | c75304a | 2015-12-03 17:37:38 +0100 | [diff] [blame] | 378 | for (i = 0; i < prop_len; i++) { |
Markus Armbruster | 62a35aa | 2020-07-07 18:05:46 +0200 | [diff] [blame] | 379 | if (!visit_type_uint8(v, NULL, (uint8_t *)&prop->data[i], |
Markus Armbruster | 668f62e | 2020-07-07 18:06:02 +0200 | [diff] [blame] | 380 | errp)) { |
Markus Armbruster | c75304a | 2015-12-03 17:37:38 +0100 | [diff] [blame] | 381 | return; |
| 382 | } |
| 383 | } |
Greg Kurz | ebd226d | 2020-09-14 14:34:59 +0200 | [diff] [blame] | 384 | ok = visit_check_list(v, errp); |
Eric Blake | 1158bb2 | 2016-06-09 10:48:34 -0600 | [diff] [blame] | 385 | visit_end_list(v, NULL); |
Greg Kurz | ebd226d | 2020-09-14 14:34:59 +0200 | [diff] [blame] | 386 | if (!ok) { |
Markus Armbruster | a4a1c70 | 2017-03-03 13:32:45 +0100 | [diff] [blame] | 387 | return; |
| 388 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 389 | break; |
| 390 | } |
| 391 | default: |
Philippe Mathieu-Daudé | e20c631 | 2018-05-29 14:48:19 -0300 | [diff] [blame] | 392 | error_report("device FDT in unexpected state: %d", tag); |
| 393 | abort(); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 394 | } |
| 395 | fdt_offset = fdt_offset_next; |
| 396 | } while (fdt_depth != 0); |
| 397 | } |
| 398 | |
Greg Kurz | bc370a6 | 2020-12-01 12:37:28 +0100 | [diff] [blame] | 399 | void spapr_drc_attach(SpaprDrc *drc, DeviceState *d) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 400 | { |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 401 | trace_spapr_drc_attach(spapr_drc_index(drc)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 402 | |
Greg Kurz | bc370a6 | 2020-12-01 12:37:28 +0100 | [diff] [blame] | 403 | g_assert(!drc->dev); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 404 | g_assert((drc->state == SPAPR_DRC_STATE_LOGICAL_UNUSABLE) |
| 405 | || (drc->state == SPAPR_DRC_STATE_PHYSICAL_POWERON)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 406 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 407 | drc->dev = d; |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 408 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 409 | object_property_add_link(OBJECT(drc), "device", |
| 410 | object_get_typename(OBJECT(drc->dev)), |
| 411 | (Object **)(&drc->dev), |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 412 | NULL, 0); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 413 | } |
| 414 | |
Daniel Henrique Barboza | a03509c | 2021-02-22 16:45:28 -0300 | [diff] [blame] | 415 | void spapr_drc_unplug_request(SpaprDrc *drc) |
David Gibson | 9c914e5 | 2017-06-08 00:36:23 +1000 | [diff] [blame] | 416 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 417 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 418 | |
Daniel Henrique Barboza | a03509c | 2021-02-22 16:45:28 -0300 | [diff] [blame] | 419 | trace_spapr_drc_unplug_request(spapr_drc_index(drc)); |
David Gibson | 9c914e5 | 2017-06-08 00:36:23 +1000 | [diff] [blame] | 420 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 421 | g_assert(drc->dev); |
| 422 | |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 423 | drc->unplug_requested = true; |
David Gibson | a8dc47f | 2017-07-04 21:07:14 +1000 | [diff] [blame] | 424 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 425 | if (drc->state != drck->empty_state) { |
| 426 | trace_spapr_drc_awaiting_quiesce(spapr_drc_index(drc)); |
David Gibson | 9c914e5 | 2017-06-08 00:36:23 +1000 | [diff] [blame] | 427 | return; |
| 428 | } |
| 429 | |
David Gibson | 9c914e5 | 2017-06-08 00:36:23 +1000 | [diff] [blame] | 430 | spapr_drc_release(drc); |
| 431 | } |
| 432 | |
Greg Kurz | 930ef3b | 2020-12-18 11:33:56 +0100 | [diff] [blame] | 433 | bool spapr_drc_reset(SpaprDrc *drc) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 434 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 435 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
Greg Kurz | 930ef3b | 2020-12-18 11:33:56 +0100 | [diff] [blame] | 436 | bool unplug_completed = false; |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 437 | |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 438 | trace_spapr_drc_reset(spapr_drc_index(drc)); |
David Gibson | b8fdd53 | 2017-06-04 20:26:25 +1000 | [diff] [blame] | 439 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 440 | /* immediately upon reset we can safely assume DRCs whose devices |
David Gibson | 4f9242f | 2017-06-21 15:21:28 +0800 | [diff] [blame] | 441 | * are pending removal can be safely removed. |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 442 | */ |
David Gibson | f1c5235 | 2017-06-20 21:02:41 +0800 | [diff] [blame] | 443 | if (drc->unplug_requested) { |
David Gibson | 4f9242f | 2017-06-21 15:21:28 +0800 | [diff] [blame] | 444 | spapr_drc_release(drc); |
Greg Kurz | 930ef3b | 2020-12-18 11:33:56 +0100 | [diff] [blame] | 445 | unplug_completed = true; |
David Gibson | 4f9242f | 2017-06-21 15:21:28 +0800 | [diff] [blame] | 446 | } |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 447 | |
David Gibson | 4f9242f | 2017-06-21 15:21:28 +0800 | [diff] [blame] | 448 | if (drc->dev) { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 449 | /* A device present at reset is ready to go, same as coldplugged */ |
| 450 | drc->state = drck->ready_state; |
Bharata B Rao | 188bfe1 | 2017-08-17 10:46:42 +0530 | [diff] [blame] | 451 | /* |
| 452 | * Ensure that we are able to send the FDT fragment again |
| 453 | * via configure-connector call if the guest requests. |
| 454 | */ |
| 455 | drc->ccs_offset = drc->fdt_start_offset; |
| 456 | drc->ccs_depth = 0; |
David Gibson | 4f9242f | 2017-06-21 15:21:28 +0800 | [diff] [blame] | 457 | } else { |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 458 | drc->state = drck->empty_state; |
Bharata B Rao | 188bfe1 | 2017-08-17 10:46:42 +0530 | [diff] [blame] | 459 | drc->ccs_offset = -1; |
| 460 | drc->ccs_depth = -1; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 461 | } |
Greg Kurz | 930ef3b | 2020-12-18 11:33:56 +0100 | [diff] [blame] | 462 | |
| 463 | return unplug_completed; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 464 | } |
| 465 | |
Greg Kurz | ab85843 | 2020-02-14 16:01:28 +0100 | [diff] [blame] | 466 | static bool spapr_drc_unplug_requested_needed(void *opaque) |
| 467 | { |
| 468 | return spapr_drc_unplug_requested(opaque); |
| 469 | } |
| 470 | |
| 471 | static const VMStateDescription vmstate_spapr_drc_unplug_requested = { |
| 472 | .name = "spapr_drc/unplug_requested", |
| 473 | .version_id = 1, |
| 474 | .minimum_version_id = 1, |
| 475 | .needed = spapr_drc_unplug_requested_needed, |
| 476 | .fields = (VMStateField []) { |
| 477 | VMSTATE_BOOL(unplug_requested, SpaprDrc), |
| 478 | VMSTATE_END_OF_LIST() |
| 479 | } |
| 480 | }; |
| 481 | |
Greg Kurz | cd725bd | 2020-12-18 11:33:55 +0100 | [diff] [blame] | 482 | static bool spapr_drc_needed(void *opaque) |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 483 | { |
Greg Kurz | cd725bd | 2020-12-18 11:33:55 +0100 | [diff] [blame] | 484 | SpaprDrc *drc = opaque; |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 485 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 486 | |
Greg Kurz | 4b63db1 | 2020-02-14 16:01:22 +0100 | [diff] [blame] | 487 | /* |
| 488 | * If no dev is plugged in there is no need to migrate the DRC state |
| 489 | * nor to reset the DRC at CAS. |
| 490 | */ |
Daniel Henrique Barboza | c618e30 | 2017-08-30 15:21:39 -0300 | [diff] [blame] | 491 | if (!drc->dev) { |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 492 | return false; |
| 493 | } |
| 494 | |
| 495 | /* |
Greg Kurz | 4b63db1 | 2020-02-14 16:01:22 +0100 | [diff] [blame] | 496 | * We need to reset the DRC at CAS or to migrate the DRC state if it's |
| 497 | * not equal to the expected long-term state, which is the same as the |
Greg Kurz | ab85843 | 2020-02-14 16:01:28 +0100 | [diff] [blame] | 498 | * coldplugged initial state, or if an unplug request is pending. |
Greg Kurz | 4b63db1 | 2020-02-14 16:01:22 +0100 | [diff] [blame] | 499 | */ |
Greg Kurz | ab85843 | 2020-02-14 16:01:28 +0100 | [diff] [blame] | 500 | return drc->state != drck->ready_state || |
| 501 | spapr_drc_unplug_requested(drc); |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | static const VMStateDescription vmstate_spapr_drc = { |
| 505 | .name = "spapr_drc", |
| 506 | .version_id = 1, |
| 507 | .minimum_version_id = 1, |
| 508 | .needed = spapr_drc_needed, |
| 509 | .fields = (VMStateField []) { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 510 | VMSTATE_UINT32(state, SpaprDrc), |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 511 | VMSTATE_END_OF_LIST() |
Greg Kurz | ab85843 | 2020-02-14 16:01:28 +0100 | [diff] [blame] | 512 | }, |
| 513 | .subsections = (const VMStateDescription * []) { |
| 514 | &vmstate_spapr_drc_unplug_requested, |
| 515 | NULL |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 516 | } |
| 517 | }; |
| 518 | |
Greg Kurz | 00f46c9 | 2020-12-18 11:33:59 +0100 | [diff] [blame] | 519 | static void drc_realize(DeviceState *d, Error **errp) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 520 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 521 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(d); |
Daniel Henrique Barboza | 37deca7 | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 522 | g_autofree gchar *link_name = g_strdup_printf("%x", spapr_drc_index(drc)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 523 | Object *root_container; |
Markus Armbruster | 7a309cc | 2020-07-14 18:02:00 +0200 | [diff] [blame] | 524 | const char *child_name; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 525 | |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 526 | trace_spapr_drc_realize(spapr_drc_index(drc)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 527 | /* NOTE: we do this as part of realize/unrealize due to the fact |
| 528 | * that the guest will communicate with the DRC via RTAS calls |
| 529 | * referencing the global DRC index. By unlinking the DRC |
| 530 | * from DRC_CONTAINER_PATH/<drc_index> we effectively make it |
| 531 | * inaccessible by the guest, since lookups rely on this path |
| 532 | * existing in the composition tree |
| 533 | */ |
| 534 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 535 | child_name = object_get_canonical_path_component(OBJECT(drc)); |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 536 | trace_spapr_drc_realize_child(spapr_drc_index(drc), child_name); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 537 | object_property_add_alias(root_container, link_name, |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 538 | drc->owner, child_name); |
Marc-André Lureau | 3cad405 | 2019-08-28 16:02:32 +0400 | [diff] [blame] | 539 | vmstate_register(VMSTATE_IF(drc), spapr_drc_index(drc), &vmstate_spapr_drc, |
Daniel Henrique Barboza | a50919d | 2017-05-22 16:35:49 -0300 | [diff] [blame] | 540 | drc); |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 541 | trace_spapr_drc_realize_complete(spapr_drc_index(drc)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 542 | } |
| 543 | |
Greg Kurz | 00f46c9 | 2020-12-18 11:33:59 +0100 | [diff] [blame] | 544 | static void drc_unrealize(DeviceState *d) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 545 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 546 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(d); |
Daniel Henrique Barboza | ef2ece4 | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 547 | g_autofree gchar *name = g_strdup_printf("%x", spapr_drc_index(drc)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 548 | Object *root_container; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 549 | |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 550 | trace_spapr_drc_unrealize(spapr_drc_index(drc)); |
Marc-André Lureau | 3cad405 | 2019-08-28 16:02:32 +0400 | [diff] [blame] | 551 | vmstate_unregister(VMSTATE_IF(drc), &vmstate_spapr_drc, drc); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 552 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); |
Markus Armbruster | df4fe0b | 2020-05-05 17:29:26 +0200 | [diff] [blame] | 553 | object_property_del(root_container, name); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 554 | } |
| 555 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 556 | SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type, |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 557 | uint32_t id) |
| 558 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 559 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(object_new(type)); |
Daniel Henrique Barboza | 7614114 | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 560 | g_autofree char *prop_name = NULL; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 561 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 562 | drc->id = id; |
| 563 | drc->owner = owner; |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 564 | prop_name = g_strdup_printf("dr-connector[%"PRIu32"]", |
| 565 | spapr_drc_index(drc)); |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 566 | object_property_add_child(owner, prop_name, OBJECT(drc)); |
Michael Roth | f3f4103 | 2017-07-25 19:59:56 +0200 | [diff] [blame] | 567 | object_unref(OBJECT(drc)); |
Markus Armbruster | ce189ab | 2020-06-10 07:32:45 +0200 | [diff] [blame] | 568 | qdev_realize(DEVICE(drc), NULL, NULL); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 569 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 570 | return drc; |
| 571 | } |
| 572 | |
| 573 | static void spapr_dr_connector_instance_init(Object *obj) |
| 574 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 575 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
| 576 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 577 | |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 578 | object_property_add_uint32_ptr(obj, "id", &drc->id, OBJ_PROP_FLAG_READ); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 579 | object_property_add(obj, "index", "uint32", prop_get_index, |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 580 | NULL, NULL, NULL); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 581 | object_property_add(obj, "fdt", "struct", prop_get_fdt, |
Markus Armbruster | d262312 | 2020-05-05 17:29:22 +0200 | [diff] [blame] | 582 | NULL, NULL, NULL); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 583 | drc->state = drck->empty_state; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 584 | } |
| 585 | |
| 586 | static void spapr_dr_connector_class_init(ObjectClass *k, void *data) |
| 587 | { |
| 588 | DeviceClass *dk = DEVICE_CLASS(k); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 589 | |
Greg Kurz | 00f46c9 | 2020-12-18 11:33:59 +0100 | [diff] [blame] | 590 | dk->realize = drc_realize; |
| 591 | dk->unrealize = drc_unrealize; |
Markus Armbruster | c401ae8 | 2015-12-03 17:37:40 +0100 | [diff] [blame] | 592 | /* |
Greg Kurz | eaf1ffb | 2020-10-12 13:26:39 +0200 | [diff] [blame] | 593 | * Reason: DR connector needs to be wired to either the machine or to a |
| 594 | * PHB in spapr_dr_connector_new(). |
Markus Armbruster | c401ae8 | 2015-12-03 17:37:40 +0100 | [diff] [blame] | 595 | */ |
Eduardo Habkost | e90f2a8 | 2017-05-03 17:35:44 -0300 | [diff] [blame] | 596 | dk->user_creatable = false; |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 597 | } |
| 598 | |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 599 | static bool drc_physical_needed(void *opaque) |
| 600 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 601 | SpaprDrcPhysical *drcp = (SpaprDrcPhysical *)opaque; |
| 602 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(drcp); |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 603 | |
| 604 | if ((drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_ACTIVE)) |
| 605 | || (!drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_INACTIVE))) { |
| 606 | return false; |
| 607 | } |
| 608 | return true; |
| 609 | } |
| 610 | |
| 611 | static const VMStateDescription vmstate_spapr_drc_physical = { |
| 612 | .name = "spapr_drc/physical", |
| 613 | .version_id = 1, |
| 614 | .minimum_version_id = 1, |
| 615 | .needed = drc_physical_needed, |
| 616 | .fields = (VMStateField []) { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 617 | VMSTATE_UINT32(dr_indicator, SpaprDrcPhysical), |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 618 | VMSTATE_END_OF_LIST() |
| 619 | } |
| 620 | }; |
| 621 | |
| 622 | static void drc_physical_reset(void *opaque) |
| 623 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 624 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(opaque); |
| 625 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(drc); |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 626 | |
| 627 | if (drc->dev) { |
| 628 | drcp->dr_indicator = SPAPR_DR_INDICATOR_ACTIVE; |
| 629 | } else { |
| 630 | drcp->dr_indicator = SPAPR_DR_INDICATOR_INACTIVE; |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | static void realize_physical(DeviceState *d, Error **errp) |
| 635 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 636 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d); |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 637 | Error *local_err = NULL; |
| 638 | |
Greg Kurz | 00f46c9 | 2020-12-18 11:33:59 +0100 | [diff] [blame] | 639 | drc_realize(d, &local_err); |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 640 | if (local_err) { |
| 641 | error_propagate(errp, local_err); |
| 642 | return; |
| 643 | } |
| 644 | |
Marc-André Lureau | 3cad405 | 2019-08-28 16:02:32 +0400 | [diff] [blame] | 645 | vmstate_register(VMSTATE_IF(drcp), |
| 646 | spapr_drc_index(SPAPR_DR_CONNECTOR(drcp)), |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 647 | &vmstate_spapr_drc_physical, drcp); |
| 648 | qemu_register_reset(drc_physical_reset, drcp); |
| 649 | } |
| 650 | |
Markus Armbruster | b69c3c2 | 2020-05-05 17:29:24 +0200 | [diff] [blame] | 651 | static void unrealize_physical(DeviceState *d) |
Greg Kurz | 379ae09 | 2017-07-25 19:59:44 +0200 | [diff] [blame] | 652 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 653 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d); |
Greg Kurz | 379ae09 | 2017-07-25 19:59:44 +0200 | [diff] [blame] | 654 | |
Greg Kurz | 00f46c9 | 2020-12-18 11:33:59 +0100 | [diff] [blame] | 655 | drc_unrealize(d); |
Marc-André Lureau | 3cad405 | 2019-08-28 16:02:32 +0400 | [diff] [blame] | 656 | vmstate_unregister(VMSTATE_IF(drcp), &vmstate_spapr_drc_physical, drcp); |
Greg Kurz | 379ae09 | 2017-07-25 19:59:44 +0200 | [diff] [blame] | 657 | qemu_unregister_reset(drc_physical_reset, drcp); |
| 658 | } |
| 659 | |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 660 | static void spapr_drc_physical_class_init(ObjectClass *k, void *data) |
| 661 | { |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 662 | DeviceClass *dk = DEVICE_CLASS(k); |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 663 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 664 | |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 665 | dk->realize = realize_physical; |
Greg Kurz | 379ae09 | 2017-07-25 19:59:44 +0200 | [diff] [blame] | 666 | dk->unrealize = unrealize_physical; |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 667 | drck->dr_entity_sense = physical_entity_sense; |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 668 | drck->isolate = drc_isolate_physical; |
| 669 | drck->unisolate = drc_unisolate_physical; |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 670 | drck->ready_state = SPAPR_DRC_STATE_PHYSICAL_CONFIGURED; |
| 671 | drck->empty_state = SPAPR_DRC_STATE_PHYSICAL_POWERON; |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 672 | } |
| 673 | |
| 674 | static void spapr_drc_logical_class_init(ObjectClass *k, void *data) |
| 675 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 676 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 677 | |
| 678 | drck->dr_entity_sense = logical_entity_sense; |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 679 | drck->isolate = drc_isolate_logical; |
| 680 | drck->unisolate = drc_unisolate_logical; |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 681 | drck->ready_state = SPAPR_DRC_STATE_LOGICAL_CONFIGURED; |
| 682 | drck->empty_state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE; |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 683 | } |
| 684 | |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 685 | static void spapr_drc_cpu_class_init(ObjectClass *k, void *data) |
| 686 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 687 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 688 | |
| 689 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_CPU; |
David Gibson | 1693ea1 | 2017-06-04 20:26:54 +1000 | [diff] [blame] | 690 | drck->typename = "CPU"; |
David Gibson | 7980833 | 2017-06-07 12:00:11 +1000 | [diff] [blame] | 691 | drck->drc_name_prefix = "CPU "; |
David Gibson | 6b762f2 | 2017-06-16 16:19:20 +0800 | [diff] [blame] | 692 | drck->release = spapr_core_release; |
Greg Kurz | 345b12b | 2019-02-19 18:17:48 +0100 | [diff] [blame] | 693 | drck->dt_populate = spapr_core_dt_populate; |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 694 | } |
| 695 | |
| 696 | static void spapr_drc_pci_class_init(ObjectClass *k, void *data) |
| 697 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 698 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 699 | |
| 700 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PCI; |
David Gibson | 1693ea1 | 2017-06-04 20:26:54 +1000 | [diff] [blame] | 701 | drck->typename = "28"; |
David Gibson | 7980833 | 2017-06-07 12:00:11 +1000 | [diff] [blame] | 702 | drck->drc_name_prefix = "C"; |
David Gibson | 6b762f2 | 2017-06-16 16:19:20 +0800 | [diff] [blame] | 703 | drck->release = spapr_phb_remove_pci_device_cb; |
Greg Kurz | 46fd029 | 2019-02-19 18:17:53 +0100 | [diff] [blame] | 704 | drck->dt_populate = spapr_pci_dt_populate; |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 705 | } |
| 706 | |
| 707 | static void spapr_drc_lmb_class_init(ObjectClass *k, void *data) |
| 708 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 709 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 710 | |
| 711 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_LMB; |
David Gibson | 1693ea1 | 2017-06-04 20:26:54 +1000 | [diff] [blame] | 712 | drck->typename = "MEM"; |
David Gibson | 7980833 | 2017-06-07 12:00:11 +1000 | [diff] [blame] | 713 | drck->drc_name_prefix = "LMB "; |
David Gibson | 6b762f2 | 2017-06-16 16:19:20 +0800 | [diff] [blame] | 714 | drck->release = spapr_lmb_release; |
Greg Kurz | 62d38c9 | 2019-02-19 18:17:43 +0100 | [diff] [blame] | 715 | drck->dt_populate = spapr_lmb_dt_populate; |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 716 | } |
| 717 | |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 718 | static void spapr_drc_phb_class_init(ObjectClass *k, void *data) |
| 719 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 720 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 721 | |
| 722 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB; |
| 723 | drck->typename = "PHB"; |
| 724 | drck->drc_name_prefix = "PHB "; |
Greg Kurz | bb2bdd8 | 2019-02-19 18:18:49 +0100 | [diff] [blame] | 725 | drck->release = spapr_phb_release; |
| 726 | drck->dt_populate = spapr_phb_dt_populate; |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 727 | } |
| 728 | |
Shivaprasad G Bhat | ee3a71e | 2020-02-09 22:56:31 -0600 | [diff] [blame] | 729 | static void spapr_drc_pmem_class_init(ObjectClass *k, void *data) |
| 730 | { |
| 731 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
| 732 | |
| 733 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM; |
| 734 | drck->typename = "PMEM"; |
| 735 | drck->drc_name_prefix = "PMEM "; |
| 736 | drck->release = NULL; |
| 737 | drck->dt_populate = spapr_pmem_dt_populate; |
| 738 | } |
| 739 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 740 | static const TypeInfo spapr_dr_connector_info = { |
| 741 | .name = TYPE_SPAPR_DR_CONNECTOR, |
| 742 | .parent = TYPE_DEVICE, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 743 | .instance_size = sizeof(SpaprDrc), |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 744 | .instance_init = spapr_dr_connector_instance_init, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 745 | .class_size = sizeof(SpaprDrcClass), |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 746 | .class_init = spapr_dr_connector_class_init, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 747 | .abstract = true, |
| 748 | }; |
| 749 | |
| 750 | static const TypeInfo spapr_drc_physical_info = { |
| 751 | .name = TYPE_SPAPR_DRC_PHYSICAL, |
| 752 | .parent = TYPE_SPAPR_DR_CONNECTOR, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 753 | .instance_size = sizeof(SpaprDrcPhysical), |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 754 | .class_init = spapr_drc_physical_class_init, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 755 | .abstract = true, |
| 756 | }; |
| 757 | |
| 758 | static const TypeInfo spapr_drc_logical_info = { |
| 759 | .name = TYPE_SPAPR_DRC_LOGICAL, |
| 760 | .parent = TYPE_SPAPR_DR_CONNECTOR, |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 761 | .class_init = spapr_drc_logical_class_init, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 762 | .abstract = true, |
| 763 | }; |
| 764 | |
| 765 | static const TypeInfo spapr_drc_cpu_info = { |
| 766 | .name = TYPE_SPAPR_DRC_CPU, |
| 767 | .parent = TYPE_SPAPR_DRC_LOGICAL, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 768 | .class_init = spapr_drc_cpu_class_init, |
| 769 | }; |
| 770 | |
| 771 | static const TypeInfo spapr_drc_pci_info = { |
| 772 | .name = TYPE_SPAPR_DRC_PCI, |
| 773 | .parent = TYPE_SPAPR_DRC_PHYSICAL, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 774 | .class_init = spapr_drc_pci_class_init, |
| 775 | }; |
| 776 | |
| 777 | static const TypeInfo spapr_drc_lmb_info = { |
| 778 | .name = TYPE_SPAPR_DRC_LMB, |
| 779 | .parent = TYPE_SPAPR_DRC_LOGICAL, |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 780 | .class_init = spapr_drc_lmb_class_init, |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 781 | }; |
| 782 | |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 783 | static const TypeInfo spapr_drc_phb_info = { |
| 784 | .name = TYPE_SPAPR_DRC_PHB, |
| 785 | .parent = TYPE_SPAPR_DRC_LOGICAL, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 786 | .instance_size = sizeof(SpaprDrc), |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 787 | .class_init = spapr_drc_phb_class_init, |
| 788 | }; |
| 789 | |
Shivaprasad G Bhat | ee3a71e | 2020-02-09 22:56:31 -0600 | [diff] [blame] | 790 | static const TypeInfo spapr_drc_pmem_info = { |
| 791 | .name = TYPE_SPAPR_DRC_PMEM, |
| 792 | .parent = TYPE_SPAPR_DRC_LOGICAL, |
| 793 | .class_init = spapr_drc_pmem_class_init, |
| 794 | }; |
| 795 | |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 796 | /* helper functions for external users */ |
| 797 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 798 | SpaprDrc *spapr_drc_by_index(uint32_t index) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 799 | { |
| 800 | Object *obj; |
Daniel Henrique Barboza | 5436eee | 2022-03-02 06:51:40 +0100 | [diff] [blame] | 801 | g_autofree gchar *name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH, |
| 802 | index); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 803 | obj = object_resolve_path(name, NULL); |
| 804 | |
| 805 | return !obj ? NULL : SPAPR_DR_CONNECTOR(obj); |
| 806 | } |
| 807 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 808 | SpaprDrc *spapr_drc_by_id(const char *type, uint32_t id) |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 809 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 810 | SpaprDrcClass *drck |
David Gibson | fbf5539 | 2017-06-04 20:26:03 +1000 | [diff] [blame] | 811 | = SPAPR_DR_CONNECTOR_CLASS(object_class_by_name(type)); |
| 812 | |
| 813 | return spapr_drc_by_index(drck->typeshift << DRC_INDEX_TYPE_SHIFT |
| 814 | | (id & DRC_INDEX_ID_MASK)); |
Michael Roth | bbf5c87 | 2015-05-07 15:33:43 +1000 | [diff] [blame] | 815 | } |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 816 | |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 817 | /** |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 818 | * spapr_dt_drc |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 819 | * |
| 820 | * @fdt: libfdt device tree |
| 821 | * @path: path in the DT to generate properties |
| 822 | * @owner: parent Object/DeviceState for which to generate DRC |
| 823 | * descriptions for |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 824 | * @drc_type_mask: mask of SpaprDrcType values corresponding |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 825 | * to the types of DRCs to generate entries for |
| 826 | * |
| 827 | * generate OF properties to describe DRC topology/indices to guests |
| 828 | * |
| 829 | * as documented in PAPR+ v2.1, 13.5.2 |
| 830 | */ |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 831 | int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask) |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 832 | { |
| 833 | Object *root_container; |
| 834 | ObjectProperty *prop; |
Daniel P. Berrange | 7746abd | 2015-12-09 12:34:02 +0000 | [diff] [blame] | 835 | ObjectPropertyIterator iter; |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 836 | uint32_t drc_count = 0; |
Daniel Henrique Barboza | 75610ac | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 837 | g_autoptr(GArray) drc_indexes = g_array_new(false, true, |
| 838 | sizeof(uint32_t)); |
| 839 | g_autoptr(GArray) drc_power_domains = g_array_new(false, true, |
| 840 | sizeof(uint32_t)); |
| 841 | g_autoptr(GString) drc_names = g_string_set_size(g_string_new(NULL), |
| 842 | sizeof(uint32_t)); |
| 843 | g_autoptr(GString) drc_types = g_string_set_size(g_string_new(NULL), |
| 844 | sizeof(uint32_t)); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 845 | int ret; |
| 846 | |
Greg Kurz | 776e887 | 2020-12-14 12:19:55 +0100 | [diff] [blame] | 847 | /* |
| 848 | * This should really be only called once per node since it overwrites |
| 849 | * the OF properties if they already exist. |
| 850 | */ |
| 851 | g_assert(!fdt_get_property(fdt, offset, "ibm,drc-indexes", NULL)); |
| 852 | |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 853 | /* the first entry of each properties is a 32-bit integer encoding |
| 854 | * the number of elements in the array. we won't know this until |
| 855 | * we complete the iteration through all the matching DRCs, but |
| 856 | * reserve the space now and set the offsets accordingly so we |
| 857 | * can fill them in later. |
| 858 | */ |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 859 | drc_indexes = g_array_set_size(drc_indexes, 1); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 860 | drc_power_domains = g_array_set_size(drc_power_domains, 1); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 861 | |
| 862 | /* aliases for all DRConnector objects will be rooted in QOM |
| 863 | * composition tree at DRC_CONTAINER_PATH |
| 864 | */ |
| 865 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); |
| 866 | |
Daniel P. Berrange | 7746abd | 2015-12-09 12:34:02 +0000 | [diff] [blame] | 867 | object_property_iter_init(&iter, root_container); |
| 868 | while ((prop = object_property_iter_next(&iter))) { |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 869 | Object *obj; |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 870 | SpaprDrc *drc; |
| 871 | SpaprDrcClass *drck; |
Daniel Henrique Barboza | 75610ac | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 872 | g_autofree char *drc_name = NULL; |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 873 | uint32_t drc_index, drc_power_domain; |
| 874 | |
| 875 | if (!strstart(prop->type, "link<", NULL)) { |
| 876 | continue; |
| 877 | } |
| 878 | |
Markus Armbruster | 552d7f4 | 2020-07-07 18:05:51 +0200 | [diff] [blame] | 879 | obj = object_property_get_link(root_container, prop->name, |
| 880 | &error_abort); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 881 | drc = SPAPR_DR_CONNECTOR(obj); |
| 882 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
| 883 | |
| 884 | if (owner && (drc->owner != owner)) { |
| 885 | continue; |
| 886 | } |
| 887 | |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 888 | if ((spapr_drc_type(drc) & drc_type_mask) == 0) { |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 889 | continue; |
| 890 | } |
| 891 | |
| 892 | drc_count++; |
| 893 | |
| 894 | /* ibm,drc-indexes */ |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 895 | drc_index = cpu_to_be32(spapr_drc_index(drc)); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 896 | g_array_append_val(drc_indexes, drc_index); |
| 897 | |
| 898 | /* ibm,drc-power-domains */ |
| 899 | drc_power_domain = cpu_to_be32(-1); |
| 900 | g_array_append_val(drc_power_domains, drc_power_domain); |
| 901 | |
| 902 | /* ibm,drc-names */ |
Shivaprasad G Bhat | dbd26f2 | 2019-07-17 03:20:01 -0500 | [diff] [blame] | 903 | drc_name = spapr_drc_name(drc); |
| 904 | drc_names = g_string_append(drc_names, drc_name); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 905 | drc_names = g_string_insert_len(drc_names, -1, "\0", 1); |
| 906 | |
| 907 | /* ibm,drc-types */ |
David Gibson | 1693ea1 | 2017-06-04 20:26:54 +1000 | [diff] [blame] | 908 | drc_types = g_string_append(drc_types, drck->typename); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 909 | drc_types = g_string_insert_len(drc_types, -1, "\0", 1); |
| 910 | } |
| 911 | |
| 912 | /* now write the drc count into the space we reserved at the |
| 913 | * beginning of the arrays previously |
| 914 | */ |
| 915 | *(uint32_t *)drc_indexes->data = cpu_to_be32(drc_count); |
| 916 | *(uint32_t *)drc_power_domains->data = cpu_to_be32(drc_count); |
| 917 | *(uint32_t *)drc_names->str = cpu_to_be32(drc_count); |
| 918 | *(uint32_t *)drc_types->str = cpu_to_be32(drc_count); |
| 919 | |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 920 | ret = fdt_setprop(fdt, offset, "ibm,drc-indexes", |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 921 | drc_indexes->data, |
| 922 | drc_indexes->len * sizeof(uint32_t)); |
| 923 | if (ret) { |
Cédric Le Goater | ce9863b | 2016-08-02 19:38:00 +0200 | [diff] [blame] | 924 | error_report("Couldn't create ibm,drc-indexes property"); |
Daniel Henrique Barboza | 75610ac | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 925 | return ret; |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 926 | } |
| 927 | |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 928 | ret = fdt_setprop(fdt, offset, "ibm,drc-power-domains", |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 929 | drc_power_domains->data, |
| 930 | drc_power_domains->len * sizeof(uint32_t)); |
| 931 | if (ret) { |
Cédric Le Goater | ce9863b | 2016-08-02 19:38:00 +0200 | [diff] [blame] | 932 | error_report("Couldn't finalize ibm,drc-power-domains property"); |
Daniel Henrique Barboza | 75610ac | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 933 | return ret; |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 934 | } |
| 935 | |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 936 | ret = fdt_setprop(fdt, offset, "ibm,drc-names", |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 937 | drc_names->str, drc_names->len); |
| 938 | if (ret) { |
Cédric Le Goater | ce9863b | 2016-08-02 19:38:00 +0200 | [diff] [blame] | 939 | error_report("Couldn't finalize ibm,drc-names property"); |
Daniel Henrique Barboza | 75610ac | 2022-03-02 06:51:39 +0100 | [diff] [blame] | 940 | return ret; |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 941 | } |
| 942 | |
David Gibson | 9e7d38e | 2019-04-10 16:11:40 +1000 | [diff] [blame] | 943 | ret = fdt_setprop(fdt, offset, "ibm,drc-types", |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 944 | drc_types->str, drc_types->len); |
| 945 | if (ret) { |
Cédric Le Goater | ce9863b | 2016-08-02 19:38:00 +0200 | [diff] [blame] | 946 | error_report("Couldn't finalize ibm,drc-types property"); |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 947 | } |
| 948 | |
Michael Roth | e4b798b | 2015-05-07 15:33:51 +1000 | [diff] [blame] | 949 | return ret; |
| 950 | } |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 951 | |
Greg Kurz | babb819 | 2020-12-18 11:33:57 +0100 | [diff] [blame] | 952 | void spapr_drc_reset_all(SpaprMachineState *spapr) |
| 953 | { |
| 954 | Object *drc_container; |
| 955 | ObjectProperty *prop; |
| 956 | ObjectPropertyIterator iter; |
| 957 | |
| 958 | drc_container = container_get(object_get_root(), DRC_CONTAINER_PATH); |
| 959 | restart: |
| 960 | object_property_iter_init(&iter, drc_container); |
| 961 | while ((prop = object_property_iter_next(&iter))) { |
| 962 | SpaprDrc *drc; |
| 963 | |
| 964 | if (!strstart(prop->type, "link<", NULL)) { |
| 965 | continue; |
| 966 | } |
| 967 | drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container, |
| 968 | prop->name, |
| 969 | &error_abort)); |
| 970 | |
| 971 | /* |
| 972 | * This will complete any pending plug/unplug requests. |
| 973 | * In case of a unplugged PHB or PCI bridge, this will |
| 974 | * cause some DRCs to be destroyed and thus potentially |
| 975 | * invalidate the iterator. |
| 976 | */ |
| 977 | if (spapr_drc_reset(drc)) { |
| 978 | goto restart; |
| 979 | } |
| 980 | } |
| 981 | } |
| 982 | |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 983 | /* |
| 984 | * RTAS calls |
| 985 | */ |
| 986 | |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 987 | static uint32_t rtas_set_isolation_state(uint32_t idx, uint32_t state) |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 988 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 989 | SpaprDrc *drc = spapr_drc_by_index(idx); |
| 990 | SpaprDrcClass *drck; |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 991 | |
| 992 | if (!drc) { |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 993 | return RTAS_OUT_NO_SUCH_INDICATOR; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 994 | } |
| 995 | |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 996 | trace_spapr_drc_set_isolation_state(spapr_drc_index(drc), state); |
| 997 | |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 998 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | 0dfabd3 | 2017-06-08 00:58:32 +1000 | [diff] [blame] | 999 | |
| 1000 | switch (state) { |
| 1001 | case SPAPR_DR_ISOLATION_STATE_ISOLATED: |
| 1002 | return drck->isolate(drc); |
| 1003 | |
| 1004 | case SPAPR_DR_ISOLATION_STATE_UNISOLATED: |
| 1005 | return drck->unisolate(drc); |
| 1006 | |
| 1007 | default: |
| 1008 | return RTAS_OUT_PARAM_ERROR; |
| 1009 | } |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1010 | } |
| 1011 | |
| 1012 | static uint32_t rtas_set_allocation_state(uint32_t idx, uint32_t state) |
| 1013 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1014 | SpaprDrc *drc = spapr_drc_by_index(idx); |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1015 | |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 1016 | if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_LOGICAL)) { |
| 1017 | return RTAS_OUT_NO_SUCH_INDICATOR; |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1018 | } |
| 1019 | |
David Gibson | 6173673 | 2017-06-08 00:50:19 +1000 | [diff] [blame] | 1020 | trace_spapr_drc_set_allocation_state(spapr_drc_index(drc), state); |
| 1021 | |
| 1022 | switch (state) { |
| 1023 | case SPAPR_DR_ALLOCATION_STATE_USABLE: |
| 1024 | return drc_set_usable(drc); |
| 1025 | |
| 1026 | case SPAPR_DR_ALLOCATION_STATE_UNUSABLE: |
| 1027 | return drc_set_unusable(drc); |
| 1028 | |
| 1029 | default: |
| 1030 | return RTAS_OUT_PARAM_ERROR; |
| 1031 | } |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1032 | } |
| 1033 | |
David Gibson | cd74d27 | 2017-06-06 17:42:26 +1000 | [diff] [blame] | 1034 | static uint32_t rtas_set_dr_indicator(uint32_t idx, uint32_t state) |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1035 | { |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1036 | SpaprDrc *drc = spapr_drc_by_index(idx); |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1037 | |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 1038 | if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_PHYSICAL)) { |
| 1039 | return RTAS_OUT_NO_SUCH_INDICATOR; |
| 1040 | } |
| 1041 | if ((state != SPAPR_DR_INDICATOR_INACTIVE) |
| 1042 | && (state != SPAPR_DR_INDICATOR_ACTIVE) |
| 1043 | && (state != SPAPR_DR_INDICATOR_IDENTIFY) |
| 1044 | && (state != SPAPR_DR_INDICATOR_ACTION)) { |
| 1045 | return RTAS_OUT_PARAM_ERROR; /* bad state parameter */ |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1046 | } |
| 1047 | |
David Gibson | cd74d27 | 2017-06-06 17:42:26 +1000 | [diff] [blame] | 1048 | trace_spapr_drc_set_dr_indicator(idx, state); |
David Gibson | 67fea71 | 2017-06-08 23:55:03 +1000 | [diff] [blame] | 1049 | SPAPR_DRC_PHYSICAL(drc)->dr_indicator = state; |
David Gibson | cd74d27 | 2017-06-06 17:42:26 +1000 | [diff] [blame] | 1050 | return RTAS_OUT_SUCCESS; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1051 | } |
| 1052 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1053 | static void rtas_set_indicator(PowerPCCPU *cpu, SpaprMachineState *spapr, |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1054 | uint32_t token, |
| 1055 | uint32_t nargs, target_ulong args, |
| 1056 | uint32_t nret, target_ulong rets) |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1057 | { |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1058 | uint32_t type, idx, state; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1059 | uint32_t ret = RTAS_OUT_SUCCESS; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1060 | |
| 1061 | if (nargs != 3 || nret != 1) { |
| 1062 | ret = RTAS_OUT_PARAM_ERROR; |
| 1063 | goto out; |
| 1064 | } |
| 1065 | |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1066 | type = rtas_ld(args, 0); |
| 1067 | idx = rtas_ld(args, 1); |
| 1068 | state = rtas_ld(args, 2); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1069 | |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1070 | switch (type) { |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1071 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1072 | ret = rtas_set_isolation_state(idx, state); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1073 | break; |
| 1074 | case RTAS_SENSOR_TYPE_DR: |
David Gibson | cd74d27 | 2017-06-06 17:42:26 +1000 | [diff] [blame] | 1075 | ret = rtas_set_dr_indicator(idx, state); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1076 | break; |
| 1077 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1078 | ret = rtas_set_allocation_state(idx, state); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1079 | break; |
| 1080 | default: |
David Gibson | 7b7258f | 2017-06-06 17:05:53 +1000 | [diff] [blame] | 1081 | ret = RTAS_OUT_NOT_SUPPORTED; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1082 | } |
| 1083 | |
| 1084 | out: |
| 1085 | rtas_st(rets, 0, ret); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1086 | } |
| 1087 | |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1088 | static void rtas_get_sensor_state(PowerPCCPU *cpu, SpaprMachineState *spapr, |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1089 | uint32_t token, uint32_t nargs, |
| 1090 | target_ulong args, uint32_t nret, |
| 1091 | target_ulong rets) |
| 1092 | { |
| 1093 | uint32_t sensor_type; |
| 1094 | uint32_t sensor_index; |
| 1095 | uint32_t sensor_state = 0; |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1096 | SpaprDrc *drc; |
| 1097 | SpaprDrcClass *drck; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1098 | uint32_t ret = RTAS_OUT_SUCCESS; |
| 1099 | |
| 1100 | if (nargs != 2 || nret != 2) { |
| 1101 | ret = RTAS_OUT_PARAM_ERROR; |
| 1102 | goto out; |
| 1103 | } |
| 1104 | |
| 1105 | sensor_type = rtas_ld(args, 0); |
| 1106 | sensor_index = rtas_ld(args, 1); |
| 1107 | |
| 1108 | if (sensor_type != RTAS_SENSOR_TYPE_ENTITY_SENSE) { |
| 1109 | /* currently only DR-related sensors are implemented */ |
| 1110 | trace_spapr_rtas_get_sensor_state_not_supported(sensor_index, |
| 1111 | sensor_type); |
| 1112 | ret = RTAS_OUT_NOT_SUPPORTED; |
| 1113 | goto out; |
| 1114 | } |
| 1115 | |
David Gibson | fbf5539 | 2017-06-04 20:26:03 +1000 | [diff] [blame] | 1116 | drc = spapr_drc_by_index(sensor_index); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1117 | if (!drc) { |
| 1118 | trace_spapr_rtas_get_sensor_state_invalid(sensor_index); |
| 1119 | ret = RTAS_OUT_PARAM_ERROR; |
| 1120 | goto out; |
| 1121 | } |
| 1122 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
David Gibson | f224d35 | 2017-06-07 11:26:52 +1000 | [diff] [blame] | 1123 | sensor_state = drck->dr_entity_sense(drc); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1124 | |
| 1125 | out: |
| 1126 | rtas_st(rets, 0, ret); |
| 1127 | rtas_st(rets, 1, sensor_state); |
| 1128 | } |
| 1129 | |
| 1130 | /* configure-connector work area offsets, int32_t units for field |
| 1131 | * indexes, bytes for field offset/len values. |
| 1132 | * |
| 1133 | * as documented by PAPR+ v2.7, 13.5.3.5 |
| 1134 | */ |
| 1135 | #define CC_IDX_NODE_NAME_OFFSET 2 |
| 1136 | #define CC_IDX_PROP_NAME_OFFSET 2 |
| 1137 | #define CC_IDX_PROP_LEN 3 |
| 1138 | #define CC_IDX_PROP_DATA_OFFSET 4 |
| 1139 | #define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4) |
| 1140 | #define CC_WA_LEN 4096 |
| 1141 | |
| 1142 | static void configure_connector_st(target_ulong addr, target_ulong offset, |
| 1143 | const void *buf, size_t len) |
| 1144 | { |
| 1145 | cpu_physical_memory_write(ppc64_phys_to_real(addr + offset), |
| 1146 | buf, MIN(len, CC_WA_LEN - offset)); |
| 1147 | } |
| 1148 | |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1149 | static void rtas_ibm_configure_connector(PowerPCCPU *cpu, |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1150 | SpaprMachineState *spapr, |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1151 | uint32_t token, uint32_t nargs, |
| 1152 | target_ulong args, uint32_t nret, |
| 1153 | target_ulong rets) |
| 1154 | { |
| 1155 | uint64_t wa_addr; |
| 1156 | uint64_t wa_offset; |
| 1157 | uint32_t drc_index; |
David Gibson | ce2918c | 2019-03-06 15:35:37 +1100 | [diff] [blame] | 1158 | SpaprDrc *drc; |
| 1159 | SpaprDrcClass *drck; |
| 1160 | SpaprDRCCResponse resp = SPAPR_DR_CC_RESPONSE_CONTINUE; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1161 | int rc; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1162 | |
| 1163 | if (nargs != 2 || nret != 1) { |
| 1164 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
| 1165 | return; |
| 1166 | } |
| 1167 | |
| 1168 | wa_addr = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 0); |
| 1169 | |
| 1170 | drc_index = rtas_ld(wa_addr, 0); |
David Gibson | fbf5539 | 2017-06-04 20:26:03 +1000 | [diff] [blame] | 1171 | drc = spapr_drc_by_index(drc_index); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1172 | if (!drc) { |
| 1173 | trace_spapr_rtas_ibm_configure_connector_invalid(drc_index); |
| 1174 | rc = RTAS_OUT_PARAM_ERROR; |
| 1175 | goto out; |
| 1176 | } |
| 1177 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 1178 | if ((drc->state != SPAPR_DRC_STATE_LOGICAL_UNISOLATE) |
Bharata B Rao | 188bfe1 | 2017-08-17 10:46:42 +0530 | [diff] [blame] | 1179 | && (drc->state != SPAPR_DRC_STATE_PHYSICAL_UNISOLATE) |
| 1180 | && (drc->state != SPAPR_DRC_STATE_LOGICAL_CONFIGURED) |
| 1181 | && (drc->state != SPAPR_DRC_STATE_PHYSICAL_CONFIGURED)) { |
| 1182 | /* |
| 1183 | * Need to unisolate the device before configuring |
| 1184 | * or it should already be in configured state to |
| 1185 | * allow configure-connector be called repeatedly. |
| 1186 | */ |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1187 | rc = SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE; |
| 1188 | goto out; |
| 1189 | } |
| 1190 | |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 1191 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
| 1192 | |
Daniel Henrique Barboza | fe1831e | 2021-02-22 16:45:31 -0300 | [diff] [blame] | 1193 | /* |
| 1194 | * This indicates that the kernel is reconfiguring a LMB due to |
Daniel Henrique Barboza | eb7f80f | 2021-03-02 11:10:19 -0300 | [diff] [blame] | 1195 | * a failed hotunplug. Rollback the DIMM unplug process. |
Daniel Henrique Barboza | fe1831e | 2021-02-22 16:45:31 -0300 | [diff] [blame] | 1196 | */ |
| 1197 | if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB && |
| 1198 | drc->unplug_requested) { |
Daniel Henrique Barboza | eb7f80f | 2021-03-02 11:10:19 -0300 | [diff] [blame] | 1199 | spapr_memory_unplug_rollback(spapr, drc->dev); |
Daniel Henrique Barboza | fe1831e | 2021-02-22 16:45:31 -0300 | [diff] [blame] | 1200 | } |
| 1201 | |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 1202 | if (!drc->fdt) { |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 1203 | void *fdt; |
| 1204 | int fdt_size; |
| 1205 | |
| 1206 | fdt = create_device_tree(&fdt_size); |
| 1207 | |
| 1208 | if (drck->dt_populate(drc, spapr, fdt, &drc->fdt_start_offset, |
Markus Armbruster | 9261ef5 | 2020-06-30 11:03:28 +0200 | [diff] [blame] | 1209 | NULL)) { |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 1210 | g_free(fdt); |
Greg Kurz | d9c95c7 | 2019-02-19 18:17:38 +0100 | [diff] [blame] | 1211 | rc = SPAPR_DR_CC_RESPONSE_ERROR; |
| 1212 | goto out; |
| 1213 | } |
| 1214 | |
| 1215 | drc->fdt = fdt; |
| 1216 | drc->ccs_offset = drc->fdt_start_offset; |
| 1217 | drc->ccs_depth = 0; |
| 1218 | } |
| 1219 | |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1220 | do { |
| 1221 | uint32_t tag; |
| 1222 | const char *name; |
| 1223 | const struct fdt_property *prop; |
| 1224 | int fdt_offset_next, prop_len; |
| 1225 | |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 1226 | tag = fdt_next_tag(drc->fdt, drc->ccs_offset, &fdt_offset_next); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1227 | |
| 1228 | switch (tag) { |
| 1229 | case FDT_BEGIN_NODE: |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 1230 | drc->ccs_depth++; |
| 1231 | name = fdt_get_name(drc->fdt, drc->ccs_offset, NULL); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1232 | |
| 1233 | /* provide the name of the next OF node */ |
| 1234 | wa_offset = CC_VAL_DATA_OFFSET; |
| 1235 | rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset); |
| 1236 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
| 1237 | resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD; |
| 1238 | break; |
| 1239 | case FDT_END_NODE: |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 1240 | drc->ccs_depth--; |
| 1241 | if (drc->ccs_depth == 0) { |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 1242 | uint32_t drc_index = spapr_drc_index(drc); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 1243 | |
| 1244 | /* done sending the device tree, move to configured state */ |
David Gibson | 0b55aa9 | 2017-06-02 13:49:20 +1000 | [diff] [blame] | 1245 | trace_spapr_drc_set_configured(drc_index); |
David Gibson | 9d4c0f4 | 2017-06-20 21:57:48 +0800 | [diff] [blame] | 1246 | drc->state = drck->ready_state; |
Bharata B Rao | 188bfe1 | 2017-08-17 10:46:42 +0530 | [diff] [blame] | 1247 | /* |
| 1248 | * Ensure that we are able to send the FDT fragment |
| 1249 | * again via configure-connector call if the guest requests. |
| 1250 | */ |
| 1251 | drc->ccs_offset = drc->fdt_start_offset; |
| 1252 | drc->ccs_depth = 0; |
| 1253 | fdt_offset_next = drc->fdt_start_offset; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1254 | resp = SPAPR_DR_CC_RESPONSE_SUCCESS; |
| 1255 | } else { |
| 1256 | resp = SPAPR_DR_CC_RESPONSE_PREV_PARENT; |
| 1257 | } |
| 1258 | break; |
| 1259 | case FDT_PROP: |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 1260 | prop = fdt_get_property_by_offset(drc->fdt, drc->ccs_offset, |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1261 | &prop_len); |
David Gibson | 88af6ea | 2017-06-01 10:36:24 +1000 | [diff] [blame] | 1262 | name = fdt_string(drc->fdt, fdt32_to_cpu(prop->nameoff)); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1263 | |
| 1264 | /* provide the name of the next OF property */ |
| 1265 | wa_offset = CC_VAL_DATA_OFFSET; |
| 1266 | rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset); |
| 1267 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
| 1268 | |
| 1269 | /* provide the length and value of the OF property. data gets |
| 1270 | * placed immediately after NULL terminator of the OF property's |
| 1271 | * name string |
| 1272 | */ |
| 1273 | wa_offset += strlen(name) + 1, |
| 1274 | rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len); |
| 1275 | rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset); |
| 1276 | configure_connector_st(wa_addr, wa_offset, prop->data, prop_len); |
| 1277 | resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY; |
| 1278 | break; |
| 1279 | case FDT_END: |
| 1280 | resp = SPAPR_DR_CC_RESPONSE_ERROR; |
| 1281 | default: |
| 1282 | /* keep seeking for an actionable tag */ |
| 1283 | break; |
| 1284 | } |
David Gibson | 4445b1d | 2017-06-21 17:12:14 +0800 | [diff] [blame] | 1285 | if (drc->ccs_offset >= 0) { |
| 1286 | drc->ccs_offset = fdt_offset_next; |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1287 | } |
| 1288 | } while (resp == SPAPR_DR_CC_RESPONSE_CONTINUE); |
| 1289 | |
| 1290 | rc = resp; |
| 1291 | out: |
| 1292 | rtas_st(rets, 0, rc); |
| 1293 | } |
| 1294 | |
| 1295 | static void spapr_drc_register_types(void) |
| 1296 | { |
| 1297 | type_register_static(&spapr_dr_connector_info); |
David Gibson | 2d33581 | 2017-06-04 20:25:17 +1000 | [diff] [blame] | 1298 | type_register_static(&spapr_drc_physical_info); |
| 1299 | type_register_static(&spapr_drc_logical_info); |
| 1300 | type_register_static(&spapr_drc_cpu_info); |
| 1301 | type_register_static(&spapr_drc_pci_info); |
| 1302 | type_register_static(&spapr_drc_lmb_info); |
Michael Roth | 962b6c3 | 2019-02-19 18:18:23 +0100 | [diff] [blame] | 1303 | type_register_static(&spapr_drc_phb_info); |
Shivaprasad G Bhat | ee3a71e | 2020-02-09 22:56:31 -0600 | [diff] [blame] | 1304 | type_register_static(&spapr_drc_pmem_info); |
David Gibson | b89b3d3 | 2017-06-01 10:30:00 +1000 | [diff] [blame] | 1305 | |
| 1306 | spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator", |
| 1307 | rtas_set_indicator); |
| 1308 | spapr_rtas_register(RTAS_GET_SENSOR_STATE, "get-sensor-state", |
| 1309 | rtas_get_sensor_state); |
| 1310 | spapr_rtas_register(RTAS_IBM_CONFIGURE_CONNECTOR, "ibm,configure-connector", |
| 1311 | rtas_ibm_configure_connector); |
| 1312 | } |
| 1313 | type_init(spapr_drc_register_types) |