bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 1 | #ifndef EXEC_SPARC_H |
| 2 | #define EXEC_SPARC_H 1 |
| 3 | #include "dyngen-exec.h" |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 4 | #include "config.h" |
bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 5 | |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 6 | #if defined(__sparc__) |
| 7 | struct CPUSPARCState *env; |
| 8 | #else |
bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 9 | register struct CPUSPARCState *env asm(AREG0); |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 10 | #endif |
| 11 | |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 12 | #ifdef TARGET_SPARC64 |
| 13 | #define T0 (env->t0) |
| 14 | #define T1 (env->t1) |
| 15 | #define T2 (env->t2) |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 16 | #define REGWPTR env->regwptr |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 17 | #else |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 18 | #if defined(__sparc__) |
| 19 | register uint32_t T0 asm(AREG3); |
| 20 | register uint32_t T1 asm(AREG2); |
| 21 | #else |
bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 22 | register uint32_t T0 asm(AREG1); |
| 23 | register uint32_t T1 asm(AREG2); |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 24 | #endif |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 25 | |
| 26 | #undef REG_REGWPTR // Broken |
| 27 | #ifdef REG_REGWPTR |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 28 | #if defined(__sparc__) |
| 29 | register uint32_t *REGWPTR asm(AREG4); |
| 30 | #else |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 31 | register uint32_t *REGWPTR asm(AREG3); |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 32 | #endif |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 33 | #define reg_REGWPTR |
| 34 | |
| 35 | #ifdef AREG4 |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 36 | #if defined(__sparc__) |
| 37 | register uint32_t T2 asm(AREG0); |
| 38 | #else |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 39 | register uint32_t T2 asm(AREG4); |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 40 | #endif |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 41 | #define reg_T2 |
| 42 | #else |
| 43 | #define T2 (env->t2) |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 44 | #endif |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 45 | |
| 46 | #else |
| 47 | #define REGWPTR env->regwptr |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 48 | #if defined(__sparc__) |
| 49 | register uint32_t T2 asm(AREG0); |
| 50 | #else |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 51 | register uint32_t T2 asm(AREG3); |
ths | 01d6a89 | 2007-02-02 01:03:34 +0000 | [diff] [blame] | 52 | #endif |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 53 | #define reg_T2 |
| 54 | #endif |
| 55 | #endif |
| 56 | |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 57 | #define FT0 (env->ft0) |
| 58 | #define FT1 (env->ft1) |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 59 | #define DT0 (env->dt0) |
| 60 | #define DT1 (env->dt1) |
bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 61 | |
| 62 | #include "cpu.h" |
| 63 | #include "exec-all.h" |
| 64 | |
| 65 | void cpu_lock(void); |
| 66 | void cpu_unlock(void); |
| 67 | void cpu_loop_exit(void); |
bellard | 658138b | 2004-04-25 17:56:08 +0000 | [diff] [blame] | 68 | void helper_flush(target_ulong addr); |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 69 | void helper_ld_asi(int asi, int size, int sign); |
| 70 | void helper_st_asi(int asi, int size, int sign); |
| 71 | void helper_rett(void); |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 72 | void helper_ldfsr(void); |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 73 | void set_cwp(int new_cwp); |
bellard | a0c4cb4 | 2004-10-10 17:46:24 +0000 | [diff] [blame] | 74 | void do_fitos(void); |
| 75 | void do_fitod(void); |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 76 | void do_fabss(void); |
| 77 | void do_fsqrts(void); |
| 78 | void do_fsqrtd(void); |
| 79 | void do_fcmps(void); |
| 80 | void do_fcmpd(void); |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 81 | #ifdef TARGET_SPARC64 |
| 82 | void do_fabsd(void); |
| 83 | void do_fcmps_fcc1(void); |
| 84 | void do_fcmpd_fcc1(void); |
| 85 | void do_fcmps_fcc2(void); |
| 86 | void do_fcmpd_fcc2(void); |
| 87 | void do_fcmps_fcc3(void); |
| 88 | void do_fcmpd_fcc3(void); |
| 89 | void do_popc(); |
bellard | 8346901 | 2005-07-23 14:27:54 +0000 | [diff] [blame] | 90 | void do_wrpstate(); |
| 91 | void do_done(); |
| 92 | void do_retry(); |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 93 | #endif |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 94 | void do_ldd_kernel(target_ulong addr); |
| 95 | void do_ldd_user(target_ulong addr); |
| 96 | void do_ldd_raw(target_ulong addr); |
bellard | 878d309 | 2005-02-13 19:02:42 +0000 | [diff] [blame] | 97 | void do_interrupt(int intno); |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 98 | void raise_exception(int tt); |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 99 | void memcpy32(target_ulong *dst, const target_ulong *src); |
bellard | ee5bbe3 | 2005-07-04 22:18:23 +0000 | [diff] [blame] | 100 | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev); |
| 101 | void dump_mmu(CPUState *env); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 102 | void helper_debug(); |
bellard | af7bf89 | 2005-01-30 22:39:04 +0000 | [diff] [blame] | 103 | void do_wrpsr(); |
| 104 | void do_rdpsr(); |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 105 | |
| 106 | /* XXX: move that to a generic header */ |
| 107 | #if !defined(CONFIG_USER_ONLY) |
bellard | a9049a0 | 2005-10-30 18:16:26 +0000 | [diff] [blame] | 108 | #include "softmmu_exec.h" |
bellard | e8af50a | 2004-09-30 21:55:55 +0000 | [diff] [blame] | 109 | #endif /* !defined(CONFIG_USER_ONLY) */ |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 110 | |
| 111 | static inline void env_to_regs(void) |
| 112 | { |
bellard | aea3ce4 | 2005-10-30 17:06:11 +0000 | [diff] [blame] | 113 | #if defined(reg_REGWPTR) |
| 114 | REGWPTR = env->regbase + (env->cwp * 16); |
| 115 | env->regwptr = REGWPTR; |
| 116 | #endif |
bellard | 0d1a29f | 2004-10-12 22:01:28 +0000 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | static inline void regs_to_env(void) |
| 120 | { |
| 121 | } |
| 122 | |
bellard | 9d89330 | 2005-02-07 23:10:53 +0000 | [diff] [blame] | 123 | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
| 124 | int is_user, int is_softmmu); |
| 125 | |
bellard | 7a3f194 | 2003-09-30 20:36:07 +0000 | [diff] [blame] | 126 | #endif |