ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU SCI/SCIF serial port emulation |
| 3 | * |
| 4 | * Copyright (c) 2007 Magnus Damm |
| 5 | * |
| 6 | * Based on serial.c - QEMU 16450 UART emulation |
| 7 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 8 | * |
| 9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 10 | * of this software and associated documentation files (the "Software"), to deal |
| 11 | * in the Software without restriction, including without limitation the rights |
| 12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 13 | * copies of the Software, and to permit persons to whom the Software is |
| 14 | * furnished to do so, subject to the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice shall be included in |
| 17 | * all copies or substantial portions of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 25 | * THE SOFTWARE. |
| 26 | */ |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 27 | |
Peter Maydell | 0430891 | 2016-01-26 18:17:30 +0000 | [diff] [blame] | 28 | #include "qemu/osdep.h" |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 29 | #include "hw/sysbus.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 30 | #include "hw/irq.h" |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 31 | #include "hw/qdev-core.h" |
| 32 | #include "hw/qdev-properties.h" |
| 33 | #include "hw/qdev-properties-system.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 34 | #include "hw/sh4/sh.h" |
Marc-André Lureau | 4d43a60 | 2017-01-26 18:26:44 +0400 | [diff] [blame] | 35 | #include "chardev/char-fe.h" |
Marc-André Lureau | 32a6ebe | 2016-10-22 12:52:52 +0300 | [diff] [blame] | 36 | #include "qapi/error.h" |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 37 | #include "qemu/timer.h" |
BALATON Zoltan | 3cf7ce4 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 38 | #include "qemu/log.h" |
BALATON Zoltan | ad52cfc | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 39 | #include "trace.h" |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 40 | |
| 41 | #define SH_SERIAL_FLAG_TEND (1 << 0) |
| 42 | #define SH_SERIAL_FLAG_TDE (1 << 1) |
| 43 | #define SH_SERIAL_FLAG_RDF (1 << 2) |
| 44 | #define SH_SERIAL_FLAG_BRK (1 << 3) |
| 45 | #define SH_SERIAL_FLAG_DR (1 << 4) |
| 46 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 47 | #define SH_RX_FIFO_LENGTH (16) |
| 48 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 49 | OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL) |
| 50 | |
| 51 | struct SHSerialState { |
| 52 | SysBusDevice parent; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 53 | uint8_t smr; |
| 54 | uint8_t brr; |
| 55 | uint8_t scr; |
| 56 | uint8_t dr; /* ftdr / tdr */ |
| 57 | uint8_t sr; /* fsr / ssr */ |
| 58 | uint16_t fcr; |
| 59 | uint8_t sptr; |
| 60 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 61 | uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 62 | uint8_t rx_cnt; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 63 | uint8_t rx_tail; |
| 64 | uint8_t rx_head; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 65 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 66 | uint8_t feat; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 67 | int flags; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 68 | int rtrg; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 69 | |
Marc-André Lureau | 32a6ebe | 2016-10-22 12:52:52 +0300 | [diff] [blame] | 70 | CharBackend chr; |
BALATON Zoltan | 5b344b0 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 71 | QEMUTimer fifo_timeout_timer; |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 72 | uint64_t etu; /* Elementary Time Unit (ns) */ |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 73 | |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 74 | qemu_irq eri; |
| 75 | qemu_irq rxi; |
| 76 | qemu_irq txi; |
| 77 | qemu_irq tei; |
| 78 | qemu_irq bri; |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | typedef struct {} SHSerialStateClass; |
| 82 | |
| 83 | OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 84 | |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 85 | static void sh_serial_clear_fifo(SHSerialState *s) |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 86 | { |
| 87 | memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); |
| 88 | s->rx_cnt = 0; |
| 89 | s->rx_head = 0; |
| 90 | s->rx_tail = 0; |
| 91 | } |
| 92 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 93 | static void sh_serial_write(void *opaque, hwaddr offs, |
Benoît Canet | 9a9d0b8 | 2011-11-17 14:23:02 +0100 | [diff] [blame] | 94 | uint64_t val, unsigned size) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 95 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 96 | SHSerialState *s = opaque; |
BALATON Zoltan | 44ae04f | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 97 | DeviceState *d = DEVICE(s); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 98 | unsigned char ch; |
| 99 | |
BALATON Zoltan | 44ae04f | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 100 | trace_sh_serial_write(d->id, size, offs, val); |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 101 | switch (offs) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 102 | case 0x00: /* SMR */ |
| 103 | s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); |
| 104 | return; |
| 105 | case 0x04: /* BRR */ |
| 106 | s->brr = val; |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 107 | return; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 108 | case 0x08: /* SCR */ |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 109 | /* TODO : For SH7751, SCIF mask should be 0xfb. */ |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 110 | s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 111 | if (!(val & (1 << 5))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 112 | s->flags |= SH_SERIAL_FLAG_TEND; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 113 | } |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 114 | if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 115 | qemu_set_irq(s->txi, val & (1 << 7)); |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 116 | } |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 117 | if (!(val & (1 << 6))) { |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 118 | qemu_set_irq(s->rxi, 0); |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 119 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 120 | return; |
| 121 | case 0x0c: /* FTDR / TDR */ |
Anton Nefedov | 3065070 | 2017-07-06 15:08:52 +0300 | [diff] [blame] | 122 | if (qemu_chr_fe_backend_connected(&s->chr)) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 123 | ch = val; |
BALATON Zoltan | 2213896 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 124 | /* |
| 125 | * XXX this blocks entire thread. Rewrite to use |
| 126 | * qemu_chr_fe_write and background I/O callbacks |
| 127 | */ |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 128 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 129 | } |
| 130 | s->dr = val; |
| 131 | s->flags &= ~SH_SERIAL_FLAG_TDE; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 132 | return; |
| 133 | #if 0 |
| 134 | case 0x14: /* FRDR / RDR */ |
| 135 | ret = 0; |
| 136 | break; |
| 137 | #endif |
| 138 | } |
| 139 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 140 | switch (offs) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 141 | case 0x10: /* FSR */ |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 142 | if (!(val & (1 << 6))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 143 | s->flags &= ~SH_SERIAL_FLAG_TEND; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 144 | } |
| 145 | if (!(val & (1 << 5))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 146 | s->flags &= ~SH_SERIAL_FLAG_TDE; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 147 | } |
| 148 | if (!(val & (1 << 4))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 149 | s->flags &= ~SH_SERIAL_FLAG_BRK; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 150 | } |
| 151 | if (!(val & (1 << 1))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 152 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 153 | } |
| 154 | if (!(val & (1 << 0))) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 155 | s->flags &= ~SH_SERIAL_FLAG_DR; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 156 | } |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 157 | |
| 158 | if (!(val & (1 << 1)) || !(val & (1 << 0))) { |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 159 | if (s->rxi) { |
| 160 | qemu_set_irq(s->rxi, 0); |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 161 | } |
| 162 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 163 | return; |
| 164 | case 0x18: /* FCR */ |
| 165 | s->fcr = val; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 166 | switch ((val >> 6) & 3) { |
| 167 | case 0: |
| 168 | s->rtrg = 1; |
| 169 | break; |
| 170 | case 1: |
| 171 | s->rtrg = 4; |
| 172 | break; |
| 173 | case 2: |
| 174 | s->rtrg = 8; |
| 175 | break; |
| 176 | case 3: |
| 177 | s->rtrg = 14; |
| 178 | break; |
| 179 | } |
| 180 | if (val & (1 << 1)) { |
| 181 | sh_serial_clear_fifo(s); |
| 182 | s->sr &= ~(1 << 1); |
| 183 | } |
| 184 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 185 | return; |
| 186 | case 0x20: /* SPTR */ |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 187 | s->sptr = val & 0xf3; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 188 | return; |
| 189 | case 0x24: /* LSR */ |
| 190 | return; |
| 191 | } |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 192 | } else { |
| 193 | switch (offs) { |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 194 | #if 0 |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 195 | case 0x0c: |
| 196 | ret = s->dr; |
| 197 | break; |
| 198 | case 0x10: |
| 199 | ret = 0; |
| 200 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 201 | #endif |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 202 | case 0x1c: |
| 203 | s->sptr = val & 0x8f; |
| 204 | return; |
| 205 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 206 | } |
BALATON Zoltan | 3cf7ce4 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 207 | qemu_log_mask(LOG_GUEST_ERROR, |
| 208 | "%s: unsupported write to 0x%02" HWADDR_PRIx "\n", |
| 209 | __func__, offs); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 212 | static uint64_t sh_serial_read(void *opaque, hwaddr offs, |
Benoît Canet | 9a9d0b8 | 2011-11-17 14:23:02 +0100 | [diff] [blame] | 213 | unsigned size) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 214 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 215 | SHSerialState *s = opaque; |
BALATON Zoltan | 44ae04f | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 216 | DeviceState *d = DEVICE(s); |
BALATON Zoltan | 3cf7ce4 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 217 | uint32_t ret = UINT32_MAX; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 218 | |
| 219 | #if 0 |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 220 | switch (offs) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 221 | case 0x00: |
| 222 | ret = s->smr; |
| 223 | break; |
| 224 | case 0x04: |
| 225 | ret = s->brr; |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 226 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 227 | case 0x08: |
| 228 | ret = s->scr; |
| 229 | break; |
| 230 | case 0x14: |
| 231 | ret = 0; |
| 232 | break; |
| 233 | } |
| 234 | #endif |
| 235 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 236 | switch (offs) { |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 237 | case 0x00: /* SMR */ |
| 238 | ret = s->smr; |
| 239 | break; |
| 240 | case 0x08: /* SCR */ |
| 241 | ret = s->scr; |
| 242 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 243 | case 0x10: /* FSR */ |
| 244 | ret = 0; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 245 | if (s->flags & SH_SERIAL_FLAG_TEND) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 246 | ret |= (1 << 6); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 247 | } |
| 248 | if (s->flags & SH_SERIAL_FLAG_TDE) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 249 | ret |= (1 << 5); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 250 | } |
| 251 | if (s->flags & SH_SERIAL_FLAG_BRK) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 252 | ret |= (1 << 4); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 253 | } |
| 254 | if (s->flags & SH_SERIAL_FLAG_RDF) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 255 | ret |= (1 << 1); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 256 | } |
| 257 | if (s->flags & SH_SERIAL_FLAG_DR) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 258 | ret |= (1 << 0); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 259 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 260 | |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 261 | if (s->scr & (1 << 5)) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 262 | s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 263 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 264 | |
| 265 | break; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 266 | case 0x14: |
| 267 | if (s->rx_cnt > 0) { |
| 268 | ret = s->rx_fifo[s->rx_tail++]; |
| 269 | s->rx_cnt--; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 270 | if (s->rx_tail == SH_RX_FIFO_LENGTH) { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 271 | s->rx_tail = 0; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 272 | } |
| 273 | if (s->rx_cnt < s->rtrg) { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 274 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 275 | } |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 276 | } |
| 277 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 278 | case 0x18: |
| 279 | ret = s->fcr; |
| 280 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 281 | case 0x1c: |
| 282 | ret = s->rx_cnt; |
| 283 | break; |
| 284 | case 0x20: |
| 285 | ret = s->sptr; |
| 286 | break; |
| 287 | case 0x24: |
| 288 | ret = 0; |
| 289 | break; |
| 290 | } |
BALATON Zoltan | f94bff1 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 291 | } else { |
| 292 | switch (offs) { |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 293 | #if 0 |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 294 | case 0x0c: |
| 295 | ret = s->dr; |
| 296 | break; |
| 297 | case 0x10: |
| 298 | ret = 0; |
| 299 | break; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 300 | case 0x14: |
| 301 | ret = s->rx_fifo[0]; |
| 302 | break; |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 303 | #endif |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 304 | case 0x1c: |
| 305 | ret = s->sptr; |
| 306 | break; |
| 307 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 308 | } |
BALATON Zoltan | 44ae04f | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 309 | trace_sh_serial_read(d->id, size, offs, ret); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 310 | |
BALATON Zoltan | 3cf7ce4 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 311 | if (ret > UINT16_MAX) { |
| 312 | qemu_log_mask(LOG_GUEST_ERROR, |
| 313 | "%s: unsupported read from 0x%02" HWADDR_PRIx "\n", |
| 314 | __func__, offs); |
| 315 | ret = 0; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | return ret; |
| 319 | } |
| 320 | |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 321 | static int sh_serial_can_receive(SHSerialState *s) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 322 | { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 323 | return s->scr & (1 << 4); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 324 | } |
| 325 | |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 326 | static void sh_serial_receive_break(SHSerialState *s) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 327 | { |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 328 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 329 | s->sr |= (1 << 4); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 330 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | static int sh_serial_can_receive1(void *opaque) |
| 334 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 335 | SHSerialState *s = opaque; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 336 | return sh_serial_can_receive(s); |
| 337 | } |
| 338 | |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 339 | static void sh_serial_timeout_int(void *opaque) |
| 340 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 341 | SHSerialState *s = opaque; |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 342 | |
| 343 | s->flags |= SH_SERIAL_FLAG_RDF; |
| 344 | if (s->scr & (1 << 6) && s->rxi) { |
| 345 | qemu_set_irq(s->rxi, 1); |
| 346 | } |
| 347 | } |
| 348 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 349 | static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) |
| 350 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 351 | SHSerialState *s = opaque; |
Aurelien Jarno | b7d2b02 | 2011-01-19 11:38:36 +0100 | [diff] [blame] | 352 | |
| 353 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
| 354 | int i; |
| 355 | for (i = 0; i < size; i++) { |
| 356 | if (s->rx_cnt < SH_RX_FIFO_LENGTH) { |
| 357 | s->rx_fifo[s->rx_head++] = buf[i]; |
| 358 | if (s->rx_head == SH_RX_FIFO_LENGTH) { |
| 359 | s->rx_head = 0; |
| 360 | } |
| 361 | s->rx_cnt++; |
| 362 | if (s->rx_cnt >= s->rtrg) { |
| 363 | s->flags |= SH_SERIAL_FLAG_RDF; |
| 364 | if (s->scr & (1 << 6) && s->rxi) { |
BALATON Zoltan | 5b344b0 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 365 | timer_del(&s->fifo_timeout_timer); |
Aurelien Jarno | b7d2b02 | 2011-01-19 11:38:36 +0100 | [diff] [blame] | 366 | qemu_set_irq(s->rxi, 1); |
| 367 | } |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 368 | } else { |
BALATON Zoltan | 5b344b0 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 369 | timer_mod(&s->fifo_timeout_timer, |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 370 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu); |
Aurelien Jarno | b7d2b02 | 2011-01-19 11:38:36 +0100 | [diff] [blame] | 371 | } |
| 372 | } |
| 373 | } |
| 374 | } else { |
| 375 | s->rx_fifo[0] = buf[0]; |
| 376 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 377 | } |
| 378 | |
Philippe Mathieu-Daudé | 083b266 | 2019-12-18 18:20:09 +0100 | [diff] [blame] | 379 | static void sh_serial_event(void *opaque, QEMUChrEvent event) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 380 | { |
BALATON Zoltan | 2f6df13 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 381 | SHSerialState *s = opaque; |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 382 | if (event == CHR_EVENT_BREAK) { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 383 | sh_serial_receive_break(s); |
BALATON Zoltan | ac3c9e7 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 384 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 385 | } |
| 386 | |
Benoît Canet | 9a9d0b8 | 2011-11-17 14:23:02 +0100 | [diff] [blame] | 387 | static const MemoryRegionOps sh_serial_ops = { |
| 388 | .read = sh_serial_read, |
| 389 | .write = sh_serial_write, |
| 390 | .endianness = DEVICE_NATIVE_ENDIAN, |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 391 | }; |
| 392 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 393 | static void sh_serial_reset(DeviceState *dev) |
BALATON Zoltan | 017f77b | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 394 | { |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 395 | SHSerialState *s = SH_SERIAL(dev); |
| 396 | |
BALATON Zoltan | 017f77b | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 397 | s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |
| 398 | s->rtrg = 1; |
| 399 | |
| 400 | s->smr = 0; |
| 401 | s->brr = 0xff; |
| 402 | s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ |
| 403 | s->sptr = 0; |
| 404 | |
| 405 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
| 406 | s->fcr = 0; |
| 407 | } else { |
| 408 | s->dr = 0xff; |
| 409 | } |
| 410 | |
| 411 | sh_serial_clear_fifo(s); |
| 412 | } |
| 413 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 414 | static void sh_serial_realize(DeviceState *d, Error **errp) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 415 | { |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 416 | SHSerialState *s = SH_SERIAL(d); |
| 417 | MemoryRegion *iomem = g_malloc(sizeof(*iomem)); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 418 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 419 | assert(d->id); |
| 420 | memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28); |
| 421 | sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem); |
| 422 | qdev_init_gpio_out_named(d, &s->eri, "eri", 1); |
| 423 | qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1); |
| 424 | qdev_init_gpio_out_named(d, &s->txi, "txi", 1); |
| 425 | qdev_init_gpio_out_named(d, &s->tei, "tei", 1); |
| 426 | qdev_init_gpio_out_named(d, &s->bri, "bri", 1); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 427 | |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 428 | if (qemu_chr_fe_backend_connected(&s->chr)) { |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 429 | qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, |
| 430 | sh_serial_receive1, |
Anton Nefedov | 81517ba | 2017-07-06 15:08:49 +0300 | [diff] [blame] | 431 | sh_serial_event, NULL, s, NULL, true); |
Hans de Goede | 456d606 | 2013-03-27 20:29:40 +0100 | [diff] [blame] | 432 | } |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 433 | |
BALATON Zoltan | 5b344b0 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 434 | timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL, |
| 435 | sh_serial_timeout_int, s); |
Geert Uytterhoeven | 71bb4ce | 2018-09-05 15:11:25 +0200 | [diff] [blame] | 436 | s->etu = NANOSECONDS_PER_SECOND / 9600; |
BALATON Zoltan | beeb520 | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | static void sh_serial_finalize(Object *obj) |
| 440 | { |
| 441 | SHSerialState *s = SH_SERIAL(obj); |
| 442 | |
| 443 | timer_del(&s->fifo_timeout_timer); |
| 444 | } |
| 445 | |
| 446 | static void sh_serial_init(Object *obj) |
| 447 | { |
| 448 | } |
| 449 | |
| 450 | static Property sh_serial_properties[] = { |
| 451 | DEFINE_PROP_CHR("chardev", SHSerialState, chr), |
| 452 | DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), |
| 453 | DEFINE_PROP_END_OF_LIST() |
| 454 | }; |
| 455 | |
| 456 | static void sh_serial_class_init(ObjectClass *oc, void *data) |
| 457 | { |
| 458 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 459 | |
| 460 | device_class_set_props(dc, sh_serial_properties); |
| 461 | dc->realize = sh_serial_realize; |
| 462 | dc->reset = sh_serial_reset; |
| 463 | /* Reason: part of SuperH CPU/SoC, needs to be wired up */ |
| 464 | dc->user_creatable = false; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 465 | } |