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ths2f062c72007-09-29 19:43:54 +00001/*
2 * QEMU SCI/SCIF serial port emulation
3 *
4 * Copyright (c) 2007 Magnus Damm
5 *
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
Markus Armbruster64552b62019-08-12 07:23:42 +020027
Peter Maydell04308912016-01-26 18:17:30 +000028#include "qemu/osdep.h"
BALATON Zoltanbeeb5202021-10-29 23:02:09 +020029#include "hw/sysbus.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020030#include "hw/irq.h"
BALATON Zoltanbeeb5202021-10-29 23:02:09 +020031#include "hw/qdev-core.h"
32#include "hw/qdev-properties.h"
33#include "hw/qdev-properties-system.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010034#include "hw/sh4/sh.h"
Marc-André Lureau4d43a602017-01-26 18:26:44 +040035#include "chardev/char-fe.h"
Marc-André Lureau32a6ebe2016-10-22 12:52:52 +030036#include "qapi/error.h"
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +020037#include "qemu/timer.h"
BALATON Zoltan3cf7ce42021-10-29 23:02:09 +020038#include "qemu/log.h"
BALATON Zoltanad52cfc2021-10-29 23:02:09 +020039#include "trace.h"
ths2f062c72007-09-29 19:43:54 +000040
41#define SH_SERIAL_FLAG_TEND (1 << 0)
42#define SH_SERIAL_FLAG_TDE (1 << 1)
43#define SH_SERIAL_FLAG_RDF (1 << 2)
44#define SH_SERIAL_FLAG_BRK (1 << 3)
45#define SH_SERIAL_FLAG_DR (1 << 4)
46
aurel3263242a02008-09-15 07:05:18 +000047#define SH_RX_FIFO_LENGTH (16)
48
BALATON Zoltanbeeb5202021-10-29 23:02:09 +020049OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL)
50
51struct SHSerialState {
52 SysBusDevice parent;
ths2f062c72007-09-29 19:43:54 +000053 uint8_t smr;
54 uint8_t brr;
55 uint8_t scr;
56 uint8_t dr; /* ftdr / tdr */
57 uint8_t sr; /* fsr / ssr */
58 uint16_t fcr;
59 uint8_t sptr;
60
aurel3263242a02008-09-15 07:05:18 +000061 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
ths2f062c72007-09-29 19:43:54 +000062 uint8_t rx_cnt;
aurel3263242a02008-09-15 07:05:18 +000063 uint8_t rx_tail;
64 uint8_t rx_head;
ths2f062c72007-09-29 19:43:54 +000065
BALATON Zoltanbeeb5202021-10-29 23:02:09 +020066 uint8_t feat;
ths2f062c72007-09-29 19:43:54 +000067 int flags;
aurel3263242a02008-09-15 07:05:18 +000068 int rtrg;
ths2f062c72007-09-29 19:43:54 +000069
Marc-André Lureau32a6ebe2016-10-22 12:52:52 +030070 CharBackend chr;
BALATON Zoltan5b344b02021-10-29 23:02:09 +020071 QEMUTimer fifo_timeout_timer;
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +020072 uint64_t etu; /* Elementary Time Unit (ns) */
aurel32bf5b7422008-05-09 18:46:04 +000073
aurel324e7ed2d2008-11-21 21:06:51 +000074 qemu_irq eri;
75 qemu_irq rxi;
76 qemu_irq txi;
77 qemu_irq tei;
78 qemu_irq bri;
BALATON Zoltanbeeb5202021-10-29 23:02:09 +020079};
80
81typedef struct {} SHSerialStateClass;
82
83OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE)
ths2f062c72007-09-29 19:43:54 +000084
BALATON Zoltan2f6df132021-10-29 23:02:09 +020085static void sh_serial_clear_fifo(SHSerialState *s)
aurel3263242a02008-09-15 07:05:18 +000086{
87 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
88 s->rx_cnt = 0;
89 s->rx_head = 0;
90 s->rx_tail = 0;
91}
92
Avi Kivitya8170e52012-10-23 12:30:10 +020093static void sh_serial_write(void *opaque, hwaddr offs,
Benoît Canet9a9d0b82011-11-17 14:23:02 +010094 uint64_t val, unsigned size)
ths2f062c72007-09-29 19:43:54 +000095{
BALATON Zoltan2f6df132021-10-29 23:02:09 +020096 SHSerialState *s = opaque;
BALATON Zoltan44ae04f2021-10-29 23:02:09 +020097 DeviceState *d = DEVICE(s);
ths2f062c72007-09-29 19:43:54 +000098 unsigned char ch;
99
BALATON Zoltan44ae04f2021-10-29 23:02:09 +0200100 trace_sh_serial_write(d->id, size, offs, val);
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200101 switch (offs) {
ths2f062c72007-09-29 19:43:54 +0000102 case 0x00: /* SMR */
103 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
104 return;
105 case 0x04: /* BRR */
106 s->brr = val;
Paolo Bonzini7d374352018-12-13 23:37:37 +0100107 return;
ths2f062c72007-09-29 19:43:54 +0000108 case 0x08: /* SCR */
aurel3263242a02008-09-15 07:05:18 +0000109 /* TODO : For SH7751, SCIF mask should be 0xfb. */
aurel32bf5b7422008-05-09 18:46:04 +0000110 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200111 if (!(val & (1 << 5))) {
ths2f062c72007-09-29 19:43:54 +0000112 s->flags |= SH_SERIAL_FLAG_TEND;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200113 }
aurel32bf5b7422008-05-09 18:46:04 +0000114 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
Paolo Bonzini7d374352018-12-13 23:37:37 +0100115 qemu_set_irq(s->txi, val & (1 << 7));
aurel32bf5b7422008-05-09 18:46:04 +0000116 }
aurel324e7ed2d2008-11-21 21:06:51 +0000117 if (!(val & (1 << 6))) {
Paolo Bonzini7d374352018-12-13 23:37:37 +0100118 qemu_set_irq(s->rxi, 0);
aurel3263242a02008-09-15 07:05:18 +0000119 }
ths2f062c72007-09-29 19:43:54 +0000120 return;
121 case 0x0c: /* FTDR / TDR */
Anton Nefedov30650702017-07-06 15:08:52 +0300122 if (qemu_chr_fe_backend_connected(&s->chr)) {
ths2f062c72007-09-29 19:43:54 +0000123 ch = val;
BALATON Zoltan22138962021-10-29 23:02:09 +0200124 /*
125 * XXX this blocks entire thread. Rewrite to use
126 * qemu_chr_fe_write and background I/O callbacks
127 */
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300128 qemu_chr_fe_write_all(&s->chr, &ch, 1);
Paolo Bonzini7d374352018-12-13 23:37:37 +0100129 }
130 s->dr = val;
131 s->flags &= ~SH_SERIAL_FLAG_TDE;
ths2f062c72007-09-29 19:43:54 +0000132 return;
133#if 0
134 case 0x14: /* FRDR / RDR */
135 ret = 0;
136 break;
137#endif
138 }
139 if (s->feat & SH_SERIAL_FEAT_SCIF) {
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200140 switch (offs) {
ths2f062c72007-09-29 19:43:54 +0000141 case 0x10: /* FSR */
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200142 if (!(val & (1 << 6))) {
ths2f062c72007-09-29 19:43:54 +0000143 s->flags &= ~SH_SERIAL_FLAG_TEND;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200144 }
145 if (!(val & (1 << 5))) {
ths2f062c72007-09-29 19:43:54 +0000146 s->flags &= ~SH_SERIAL_FLAG_TDE;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200147 }
148 if (!(val & (1 << 4))) {
ths2f062c72007-09-29 19:43:54 +0000149 s->flags &= ~SH_SERIAL_FLAG_BRK;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200150 }
151 if (!(val & (1 << 1))) {
ths2f062c72007-09-29 19:43:54 +0000152 s->flags &= ~SH_SERIAL_FLAG_RDF;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200153 }
154 if (!(val & (1 << 0))) {
ths2f062c72007-09-29 19:43:54 +0000155 s->flags &= ~SH_SERIAL_FLAG_DR;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200156 }
aurel3263242a02008-09-15 07:05:18 +0000157
158 if (!(val & (1 << 1)) || !(val & (1 << 0))) {
aurel324e7ed2d2008-11-21 21:06:51 +0000159 if (s->rxi) {
160 qemu_set_irq(s->rxi, 0);
aurel3263242a02008-09-15 07:05:18 +0000161 }
162 }
ths2f062c72007-09-29 19:43:54 +0000163 return;
164 case 0x18: /* FCR */
165 s->fcr = val;
aurel3263242a02008-09-15 07:05:18 +0000166 switch ((val >> 6) & 3) {
167 case 0:
168 s->rtrg = 1;
169 break;
170 case 1:
171 s->rtrg = 4;
172 break;
173 case 2:
174 s->rtrg = 8;
175 break;
176 case 3:
177 s->rtrg = 14;
178 break;
179 }
180 if (val & (1 << 1)) {
181 sh_serial_clear_fifo(s);
182 s->sr &= ~(1 << 1);
183 }
184
ths2f062c72007-09-29 19:43:54 +0000185 return;
186 case 0x20: /* SPTR */
aurel3263242a02008-09-15 07:05:18 +0000187 s->sptr = val & 0xf3;
ths2f062c72007-09-29 19:43:54 +0000188 return;
189 case 0x24: /* LSR */
190 return;
191 }
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200192 } else {
193 switch (offs) {
aurel32d1f193b2008-12-07 22:46:49 +0000194#if 0
ths2f062c72007-09-29 19:43:54 +0000195 case 0x0c:
196 ret = s->dr;
197 break;
198 case 0x10:
199 ret = 0;
200 break;
ths2f062c72007-09-29 19:43:54 +0000201#endif
aurel32d1f193b2008-12-07 22:46:49 +0000202 case 0x1c:
203 s->sptr = val & 0x8f;
204 return;
205 }
ths2f062c72007-09-29 19:43:54 +0000206 }
BALATON Zoltan3cf7ce42021-10-29 23:02:09 +0200207 qemu_log_mask(LOG_GUEST_ERROR,
208 "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
209 __func__, offs);
ths2f062c72007-09-29 19:43:54 +0000210}
211
Avi Kivitya8170e52012-10-23 12:30:10 +0200212static uint64_t sh_serial_read(void *opaque, hwaddr offs,
Benoît Canet9a9d0b82011-11-17 14:23:02 +0100213 unsigned size)
ths2f062c72007-09-29 19:43:54 +0000214{
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200215 SHSerialState *s = opaque;
BALATON Zoltan44ae04f2021-10-29 23:02:09 +0200216 DeviceState *d = DEVICE(s);
BALATON Zoltan3cf7ce42021-10-29 23:02:09 +0200217 uint32_t ret = UINT32_MAX;
ths2f062c72007-09-29 19:43:54 +0000218
219#if 0
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200220 switch (offs) {
ths2f062c72007-09-29 19:43:54 +0000221 case 0x00:
222 ret = s->smr;
223 break;
224 case 0x04:
225 ret = s->brr;
Paolo Bonzini7d374352018-12-13 23:37:37 +0100226 break;
ths2f062c72007-09-29 19:43:54 +0000227 case 0x08:
228 ret = s->scr;
229 break;
230 case 0x14:
231 ret = 0;
232 break;
233 }
234#endif
235 if (s->feat & SH_SERIAL_FEAT_SCIF) {
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200236 switch (offs) {
aurel32bf5b7422008-05-09 18:46:04 +0000237 case 0x00: /* SMR */
238 ret = s->smr;
239 break;
240 case 0x08: /* SCR */
241 ret = s->scr;
242 break;
ths2f062c72007-09-29 19:43:54 +0000243 case 0x10: /* FSR */
244 ret = 0;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200245 if (s->flags & SH_SERIAL_FLAG_TEND) {
ths2f062c72007-09-29 19:43:54 +0000246 ret |= (1 << 6);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200247 }
248 if (s->flags & SH_SERIAL_FLAG_TDE) {
ths2f062c72007-09-29 19:43:54 +0000249 ret |= (1 << 5);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200250 }
251 if (s->flags & SH_SERIAL_FLAG_BRK) {
ths2f062c72007-09-29 19:43:54 +0000252 ret |= (1 << 4);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200253 }
254 if (s->flags & SH_SERIAL_FLAG_RDF) {
ths2f062c72007-09-29 19:43:54 +0000255 ret |= (1 << 1);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200256 }
257 if (s->flags & SH_SERIAL_FLAG_DR) {
ths2f062c72007-09-29 19:43:54 +0000258 ret |= (1 << 0);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200259 }
ths2f062c72007-09-29 19:43:54 +0000260
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200261 if (s->scr & (1 << 5)) {
ths2f062c72007-09-29 19:43:54 +0000262 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200263 }
ths2f062c72007-09-29 19:43:54 +0000264
265 break;
aurel3263242a02008-09-15 07:05:18 +0000266 case 0x14:
267 if (s->rx_cnt > 0) {
268 ret = s->rx_fifo[s->rx_tail++];
269 s->rx_cnt--;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200270 if (s->rx_tail == SH_RX_FIFO_LENGTH) {
aurel3263242a02008-09-15 07:05:18 +0000271 s->rx_tail = 0;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200272 }
273 if (s->rx_cnt < s->rtrg) {
aurel3263242a02008-09-15 07:05:18 +0000274 s->flags &= ~SH_SERIAL_FLAG_RDF;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200275 }
aurel3263242a02008-09-15 07:05:18 +0000276 }
277 break;
ths2f062c72007-09-29 19:43:54 +0000278 case 0x18:
279 ret = s->fcr;
280 break;
ths2f062c72007-09-29 19:43:54 +0000281 case 0x1c:
282 ret = s->rx_cnt;
283 break;
284 case 0x20:
285 ret = s->sptr;
286 break;
287 case 0x24:
288 ret = 0;
289 break;
290 }
BALATON Zoltanf94bff12021-10-29 23:02:09 +0200291 } else {
292 switch (offs) {
aurel32d1f193b2008-12-07 22:46:49 +0000293#if 0
ths2f062c72007-09-29 19:43:54 +0000294 case 0x0c:
295 ret = s->dr;
296 break;
297 case 0x10:
298 ret = 0;
299 break;
aurel3263242a02008-09-15 07:05:18 +0000300 case 0x14:
301 ret = s->rx_fifo[0];
302 break;
aurel32d1f193b2008-12-07 22:46:49 +0000303#endif
ths2f062c72007-09-29 19:43:54 +0000304 case 0x1c:
305 ret = s->sptr;
306 break;
307 }
ths2f062c72007-09-29 19:43:54 +0000308 }
BALATON Zoltan44ae04f2021-10-29 23:02:09 +0200309 trace_sh_serial_read(d->id, size, offs, ret);
ths2f062c72007-09-29 19:43:54 +0000310
BALATON Zoltan3cf7ce42021-10-29 23:02:09 +0200311 if (ret > UINT16_MAX) {
312 qemu_log_mask(LOG_GUEST_ERROR,
313 "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
314 __func__, offs);
315 ret = 0;
ths2f062c72007-09-29 19:43:54 +0000316 }
317
318 return ret;
319}
320
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200321static int sh_serial_can_receive(SHSerialState *s)
ths2f062c72007-09-29 19:43:54 +0000322{
aurel3263242a02008-09-15 07:05:18 +0000323 return s->scr & (1 << 4);
ths2f062c72007-09-29 19:43:54 +0000324}
325
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200326static void sh_serial_receive_break(SHSerialState *s)
ths2f062c72007-09-29 19:43:54 +0000327{
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200328 if (s->feat & SH_SERIAL_FEAT_SCIF) {
aurel3263242a02008-09-15 07:05:18 +0000329 s->sr |= (1 << 4);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200330 }
ths2f062c72007-09-29 19:43:54 +0000331}
332
333static int sh_serial_can_receive1(void *opaque)
334{
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200335 SHSerialState *s = opaque;
ths2f062c72007-09-29 19:43:54 +0000336 return sh_serial_can_receive(s);
337}
338
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +0200339static void sh_serial_timeout_int(void *opaque)
340{
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200341 SHSerialState *s = opaque;
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +0200342
343 s->flags |= SH_SERIAL_FLAG_RDF;
344 if (s->scr & (1 << 6) && s->rxi) {
345 qemu_set_irq(s->rxi, 1);
346 }
347}
348
ths2f062c72007-09-29 19:43:54 +0000349static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
350{
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200351 SHSerialState *s = opaque;
Aurelien Jarnob7d2b022011-01-19 11:38:36 +0100352
353 if (s->feat & SH_SERIAL_FEAT_SCIF) {
354 int i;
355 for (i = 0; i < size; i++) {
356 if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
357 s->rx_fifo[s->rx_head++] = buf[i];
358 if (s->rx_head == SH_RX_FIFO_LENGTH) {
359 s->rx_head = 0;
360 }
361 s->rx_cnt++;
362 if (s->rx_cnt >= s->rtrg) {
363 s->flags |= SH_SERIAL_FLAG_RDF;
364 if (s->scr & (1 << 6) && s->rxi) {
BALATON Zoltan5b344b02021-10-29 23:02:09 +0200365 timer_del(&s->fifo_timeout_timer);
Aurelien Jarnob7d2b022011-01-19 11:38:36 +0100366 qemu_set_irq(s->rxi, 1);
367 }
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +0200368 } else {
BALATON Zoltan5b344b02021-10-29 23:02:09 +0200369 timer_mod(&s->fifo_timeout_timer,
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +0200370 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
Aurelien Jarnob7d2b022011-01-19 11:38:36 +0100371 }
372 }
373 }
374 } else {
375 s->rx_fifo[0] = buf[0];
376 }
ths2f062c72007-09-29 19:43:54 +0000377}
378
Philippe Mathieu-Daudé083b2662019-12-18 18:20:09 +0100379static void sh_serial_event(void *opaque, QEMUChrEvent event)
ths2f062c72007-09-29 19:43:54 +0000380{
BALATON Zoltan2f6df132021-10-29 23:02:09 +0200381 SHSerialState *s = opaque;
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200382 if (event == CHR_EVENT_BREAK) {
ths2f062c72007-09-29 19:43:54 +0000383 sh_serial_receive_break(s);
BALATON Zoltanac3c9e72021-10-29 23:02:09 +0200384 }
ths2f062c72007-09-29 19:43:54 +0000385}
386
Benoît Canet9a9d0b82011-11-17 14:23:02 +0100387static const MemoryRegionOps sh_serial_ops = {
388 .read = sh_serial_read,
389 .write = sh_serial_write,
390 .endianness = DEVICE_NATIVE_ENDIAN,
ths2f062c72007-09-29 19:43:54 +0000391};
392
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200393static void sh_serial_reset(DeviceState *dev)
BALATON Zoltan017f77b2021-10-29 23:02:09 +0200394{
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200395 SHSerialState *s = SH_SERIAL(dev);
396
BALATON Zoltan017f77b2021-10-29 23:02:09 +0200397 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
398 s->rtrg = 1;
399
400 s->smr = 0;
401 s->brr = 0xff;
402 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
403 s->sptr = 0;
404
405 if (s->feat & SH_SERIAL_FEAT_SCIF) {
406 s->fcr = 0;
407 } else {
408 s->dr = 0xff;
409 }
410
411 sh_serial_clear_fifo(s);
412}
413
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200414static void sh_serial_realize(DeviceState *d, Error **errp)
ths2f062c72007-09-29 19:43:54 +0000415{
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200416 SHSerialState *s = SH_SERIAL(d);
417 MemoryRegion *iomem = g_malloc(sizeof(*iomem));
ths2f062c72007-09-29 19:43:54 +0000418
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200419 assert(d->id);
420 memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28);
421 sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem);
422 qdev_init_gpio_out_named(d, &s->eri, "eri", 1);
423 qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1);
424 qdev_init_gpio_out_named(d, &s->txi, "txi", 1);
425 qdev_init_gpio_out_named(d, &s->tei, "tei", 1);
426 qdev_init_gpio_out_named(d, &s->bri, "bri", 1);
ths2f062c72007-09-29 19:43:54 +0000427
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200428 if (qemu_chr_fe_backend_connected(&s->chr)) {
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300429 qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
430 sh_serial_receive1,
Anton Nefedov81517ba2017-07-06 15:08:49 +0300431 sh_serial_event, NULL, s, NULL, true);
Hans de Goede456d6062013-03-27 20:29:40 +0100432 }
aurel32bf5b7422008-05-09 18:46:04 +0000433
BALATON Zoltan5b344b02021-10-29 23:02:09 +0200434 timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL,
435 sh_serial_timeout_int, s);
Geert Uytterhoeven71bb4ce2018-09-05 15:11:25 +0200436 s->etu = NANOSECONDS_PER_SECOND / 9600;
BALATON Zoltanbeeb5202021-10-29 23:02:09 +0200437}
438
439static void sh_serial_finalize(Object *obj)
440{
441 SHSerialState *s = SH_SERIAL(obj);
442
443 timer_del(&s->fifo_timeout_timer);
444}
445
446static void sh_serial_init(Object *obj)
447{
448}
449
450static Property sh_serial_properties[] = {
451 DEFINE_PROP_CHR("chardev", SHSerialState, chr),
452 DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),
453 DEFINE_PROP_END_OF_LIST()
454};
455
456static void sh_serial_class_init(ObjectClass *oc, void *data)
457{
458 DeviceClass *dc = DEVICE_CLASS(oc);
459
460 device_class_set_props(dc, sh_serial_properties);
461 dc->realize = sh_serial_realize;
462 dc->reset = sh_serial_reset;
463 /* Reason: part of SuperH CPU/SoC, needs to be wired up */
464 dc->user_creatable = false;
ths2f062c72007-09-29 19:43:54 +0000465}