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bellard6af0bf92005-07-02 14:58:51 +00001#if !defined (__QEMU_MIPS_DEFS_H__)
2#define __QEMU_MIPS_DEFS_H__
3
bellard6af0bf92005-07-02 14:58:51 +00004/* If we want to use host float regs... */
5//#define USE_HOST_FLOAT_REGS
6
thse9c71dd2007-12-25 20:46:56 +00007/* Real pages are variable size... */
bellard6af0bf92005-07-02 14:58:51 +00008#define TARGET_PAGE_BITS 12
ths814b9a42006-12-06 17:42:40 +00009#define MIPS_TLB_MAX 128
bellard6af0bf92005-07-02 14:58:51 +000010
thsd26bc212007-11-08 18:05:37 +000011#if defined(TARGET_MIPS64)
thsc570fd12006-12-21 01:19:56 +000012#define TARGET_LONG_BITS 64
Aurelien Jarno30724e72010-03-13 01:39:17 +010013#define TARGET_PHYS_ADDR_SPACE_BITS 36
14#define TARGET_VIRT_ADDR_SPACE_BITS 42
thsc570fd12006-12-21 01:19:56 +000015#else
16#define TARGET_LONG_BITS 32
Aurelien Jarno30724e72010-03-13 01:39:17 +010017#define TARGET_PHYS_ADDR_SPACE_BITS 36
18#define TARGET_VIRT_ADDR_SPACE_BITS 32
thsc570fd12006-12-21 01:19:56 +000019#endif
20
thse189e742007-09-24 12:48:00 +000021/* Masks used to mark instructions to indicate which ISA level they
22 were introduced in. */
23#define ISA_MIPS1 0x00000001
24#define ISA_MIPS2 0x00000002
25#define ISA_MIPS3 0x00000004
26#define ISA_MIPS4 0x00000008
27#define ISA_MIPS5 0x00000010
28#define ISA_MIPS32 0x00000020
29#define ISA_MIPS32R2 0x00000040
30#define ISA_MIPS64 0x00000080
31#define ISA_MIPS64R2 0x00000100
32
thse9c71dd2007-12-25 20:46:56 +000033/* MIPS ASEs. */
thse189e742007-09-24 12:48:00 +000034#define ASE_MIPS16 0x00001000
35#define ASE_MIPS3D 0x00002000
36#define ASE_MDMX 0x00004000
37#define ASE_DSP 0x00008000
38#define ASE_DSPR2 0x00010000
ths7385ac02007-10-23 17:04:27 +000039#define ASE_MT 0x00020000
40#define ASE_SMARTMIPS 0x00040000
Nathan Froyd3c824102010-06-08 13:29:59 -070041#define ASE_MICROMIPS 0x00080000
thse189e742007-09-24 12:48:00 +000042
thse9c71dd2007-12-25 20:46:56 +000043/* Chip specific instructions. */
Huacai Chen5bc6fba2010-06-29 10:50:27 +080044#define INSN_LOONGSON2E 0x20000000
45#define INSN_LOONGSON2F 0x40000000
thse9c71dd2007-12-25 20:46:56 +000046#define INSN_VR54XX 0x80000000
thse189e742007-09-24 12:48:00 +000047
thse9c71dd2007-12-25 20:46:56 +000048/* MIPS CPU defines. */
thse189e742007-09-24 12:48:00 +000049#define CPU_MIPS1 (ISA_MIPS1)
50#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
51#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
52#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
thse9c71dd2007-12-25 20:46:56 +000053#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
Huacai Chen5bc6fba2010-06-29 10:50:27 +080054#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
55#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
thse9c71dd2007-12-25 20:46:56 +000056
thse189e742007-09-24 12:48:00 +000057#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
58
thse9c71dd2007-12-25 20:46:56 +000059/* MIPS Technologies "Release 1" */
thse189e742007-09-24 12:48:00 +000060#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
61#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
62
thse9c71dd2007-12-25 20:46:56 +000063/* MIPS Technologies "Release 2" */
thse189e742007-09-24 12:48:00 +000064#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
65#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
66
ths19221bd2007-04-19 16:35:09 +000067/* Strictly follow the architecture standard:
68 - Disallow "special" instruction handling for PMON/SPIM.
69 Note that we still maintain Count/Compare to match the host clock. */
thsb48cfdf2007-04-11 02:24:14 +000070//#define MIPS_STRICT_STANDARD 1
71
bellard6af0bf92005-07-02 14:58:51 +000072#endif /* !defined (__QEMU_MIPS_DEFS_H__) */