blob: 396c5627bc08c539c79a52d22b1bb704318d8caa [file] [log] [blame]
pbrook0ff596d2007-05-23 00:03:59 +00001#ifndef QEMU_I2C_H
2#define QEMU_I2C_H
3
4/* The QEMU I2C implementation only supports simple transfers that complete
5 immediately. It does not support slave devices that need to be able to
6 defer their response (eg. CPU slave interfaces where the data is supplied
7 by the device driver in response to an interrupt). */
8
9enum i2c_event {
10 I2C_START_RECV,
11 I2C_START_SEND,
12 I2C_FINISH,
thsaa1f17c2007-07-11 22:48:58 +000013 I2C_NACK /* Masker NACKed a receive byte. */
pbrook0ff596d2007-05-23 00:03:59 +000014};
15
pbrook0ff596d2007-05-23 00:03:59 +000016/* Master to slave. */
17typedef int (*i2c_send_cb)(i2c_slave *s, uint8_t data);
18/* Slave to master. */
19typedef int (*i2c_recv_cb)(i2c_slave *s);
20/* Notify the slave of a bus state change. */
21typedef void (*i2c_event_cb)(i2c_slave *s, enum i2c_event event);
22
23struct i2c_slave
24{
25 /* Callbacks to be set by the device. */
26 i2c_event_cb event;
27 i2c_recv_cb recv;
28 i2c_send_cb send;
29
30 /* Remaining fields for internal use by the I2C code. */
31 int address;
32 void *next;
pbrookc701b352008-07-01 23:16:53 +000033 i2c_bus *bus;
pbrook0ff596d2007-05-23 00:03:59 +000034};
35
pbrook0ff596d2007-05-23 00:03:59 +000036i2c_bus *i2c_init_bus(void);
37i2c_slave *i2c_slave_init(i2c_bus *bus, int address, int size);
38void i2c_set_slave_address(i2c_slave *dev, int address);
39int i2c_bus_busy(i2c_bus *bus);
40int i2c_start_transfer(i2c_bus *bus, int address, int recv);
41void i2c_end_transfer(i2c_bus *bus);
42void i2c_nack(i2c_bus *bus);
43int i2c_send(i2c_bus *bus, uint8_t data);
44int i2c_recv(i2c_bus *bus);
balrogaa941b92007-05-24 18:50:09 +000045void i2c_slave_save(QEMUFile *f, i2c_slave *dev);
46void i2c_slave_load(QEMUFile *f, i2c_slave *dev);
pbrook0ff596d2007-05-23 00:03:59 +000047
pbrook87ecb682007-11-17 17:14:51 +000048/* max111x.c */
49struct max111x_s;
50uint32_t max111x_read(void *opaque);
51void max111x_write(void *opaque, uint32_t value);
52struct max111x_s *max1110_init(qemu_irq cb);
53struct max111x_s *max1111_init(qemu_irq cb);
54void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
55
balrogadb86c32007-05-23 22:04:23 +000056/* max7310.c */
57i2c_slave *max7310_init(i2c_bus *bus);
58void max7310_reset(i2c_slave *i2c);
59qemu_irq *max7310_gpio_in_get(i2c_slave *i2c);
60void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler);
61
62/* wm8750.c */
63i2c_slave *wm8750_init(i2c_bus *bus, AudioState *audio);
64void wm8750_reset(i2c_slave *i2c);
65void wm8750_data_req_set(i2c_slave *i2c,
66 void (*data_req)(void *, int, int), void *opaque);
67void wm8750_dac_dat(void *opaque, uint32_t sample);
68uint32_t wm8750_adc_dat(void *opaque);
balrog662caa62008-04-26 12:00:18 +000069void *wm8750_dac_buffer(void *opaque, int samples);
70void wm8750_dac_commit(void *opaque);
balrogb0f74c82008-11-12 17:36:08 +000071void wm8750_set_bclk_in(void *opaque, int new_hz);
balrogadb86c32007-05-23 22:04:23 +000072
pbrook87ecb682007-11-17 17:14:51 +000073/* ssd0303.c */
aliguori3023f332009-01-16 19:04:14 +000074void ssd0303_init(i2c_bus *bus, int address);
pbrook87ecb682007-11-17 17:14:51 +000075
balrog7e7c5e42008-04-14 21:57:44 +000076/* twl92230.c */
77i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq);
78qemu_irq *twl92230_gpio_in_get(i2c_slave *i2c);
79void twl92230_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler);
80
81/* tmp105.c */
82struct i2c_slave *tmp105_init(i2c_bus *bus, qemu_irq alarm);
83void tmp105_reset(i2c_slave *i2c);
84void tmp105_set(i2c_slave *i2c, int temp);
85
balrog1d4e5472008-05-09 22:16:11 +000086/* lm832x.c */
87struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq);
88void lm832x_key_event(struct i2c_slave *i2c, int key, int state);
89
pbrook0ff596d2007-05-23 00:03:59 +000090#endif