blob: 674377a19e083df360d1d16c2fea8286f2cdf4b2 [file] [log] [blame]
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +11001/*
2 * PowerPC ISAV3 BookS emulation generic mmu definitions for qemu.
3 *
4 * Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
Chetan Pant6bd039c2020-10-19 06:11:26 +00009 * version 2.1 of the License, or (at your option) any later version.
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110010 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
Markus Armbruster58ea30f2019-03-15 15:51:20 +010020#ifndef PPC_MMU_BOOK3S_V3_H
21#define PPC_MMU_BOOK3S_V3_H
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110022
Benjamin Herrenschmidt3367c622019-02-15 18:00:28 +010023#include "mmu-hash64.h"
Bruno Larsen (billionai)a97c4d32021-07-06 12:03:15 -030024#include "mmu-books.h"
Benjamin Herrenschmidt3367c622019-02-15 18:00:28 +010025
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110026#ifndef CONFIG_USER_ONLY
27
Cédric Le Goater4a7518e2018-04-24 13:30:42 +020028/*
29 * Partition table definitions
30 */
31#define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
32#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
33
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110034/* Partition Table Entry Fields */
Benjamin Herrenschmidt79825f42019-02-15 18:00:27 +010035#define PATE0_HR 0x8000000000000000
36
37/*
38 * WARNING: This field doesn't actually exist in the final version of
39 * the architecture and is unused by hardware. However, qemu uses it
40 * as an indication of a radix guest in the pseudo-PATB entry that it
41 * maintains for SPAPR guests and in the migration stream, so we need
42 * to keep it around
43 */
44#define PATE1_GR 0x8000000000000000
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110045
Suraj Jitindar Singhd5fee0b2017-05-02 16:37:17 +100046/* Process Table Entry */
47struct prtb_entry {
48 uint64_t prtbe0, prtbe1;
49};
50
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110051#ifdef TARGET_PPC64
52
Leandro Luporie7beaea2022-07-12 16:37:41 -030053/*
54 * tlbie[l] helper flags
55 *
56 * RIC, PRS, R and local are passed as flags in the last argument.
57 */
58#define TLBIE_F_RIC_SHIFT 0
59#define TLBIE_F_PRS_SHIFT 2
60#define TLBIE_F_R_SHIFT 3
61#define TLBIE_F_LOCAL_SHIFT 4
62
63#define TLBIE_F_RIC_MASK (3 << TLBIE_F_RIC_SHIFT)
64#define TLBIE_F_PRS (1 << TLBIE_F_PRS_SHIFT)
65#define TLBIE_F_R (1 << TLBIE_F_R_SHIFT)
66#define TLBIE_F_LOCAL (1 << TLBIE_F_LOCAL_SHIFT)
67
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110068static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
69{
70 return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
71}
72
Benjamin Herrenschmidt3367c622019-02-15 18:00:28 +010073bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
74 ppc_v3_pate_t *entry);
75
Benjamin Herrenschmidt38c784a2019-02-15 18:00:19 +010076/*
77 * The LPCR:HR bit is a shortcut that avoids having to
78 * dig out the partition table in the fast path. This is
79 * also how the HW uses it.
80 */
81static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110082{
Benjamin Herrenschmidt38c784a2019-02-15 18:00:19 +010083 return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +110084}
85
Benjamin Herrenschmidt3367c622019-02-15 18:00:28 +010086static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
87{
88 uint64_t base;
89
90 if (cpu->vhyp) {
91 return 0;
92 }
93 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
94 ppc_v3_pate_t pate;
95
96 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
97 return 0;
98 }
99 base = pate.dw0;
100 } else {
101 base = cpu->env.spr[SPR_SDR1];
102 }
103 return base & SDR_64_HTABORG;
104}
105
106static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
107{
108 uint64_t base;
109
110 if (cpu->vhyp) {
111 PPCVirtualHypervisorClass *vhc =
112 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
113 return vhc->hpt_mask(cpu->vhyp);
114 }
115 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
116 ppc_v3_pate_t pate;
117
118 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
119 return 0;
120 }
121 base = pate.dw0;
122 } else {
123 base = cpu->env.spr[SPR_SDR1];
124 }
125 return (1ULL << ((base & SDR_64_HTABSIZE) + 18 - 7)) - 1;
126}
127
Suraj Jitindar Singhb2899492017-03-01 17:54:38 +1100128#endif /* TARGET_PPC64 */
129
130#endif /* CONFIG_USER_ONLY */
131
Markus Armbruster58ea30f2019-03-15 15:51:20 +0100132#endif /* PPC_MMU_BOOK3S_V3_H */