balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Andrzej Zaborowski |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 24 | |
| 25 | #ifndef NDEBUG |
| 26 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 27 | "%r0", |
| 28 | "%r1", |
| 29 | "%r2", |
| 30 | "%r3", |
| 31 | "%r4", |
| 32 | "%r5", |
| 33 | "%r6", |
| 34 | "%r7", |
| 35 | "%r8", |
| 36 | "%r9", |
| 37 | "%r10", |
| 38 | "%r11", |
| 39 | "%r12", |
| 40 | "%r13", |
| 41 | "%r14", |
| 42 | }; |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 43 | #endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 44 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 45 | static const int tcg_target_reg_alloc_order[] = { |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 46 | TCG_REG_R0, |
| 47 | TCG_REG_R1, |
| 48 | TCG_REG_R2, |
| 49 | TCG_REG_R3, |
| 50 | TCG_REG_R4, |
| 51 | TCG_REG_R5, |
| 52 | TCG_REG_R6, |
| 53 | TCG_REG_R7, |
| 54 | TCG_REG_R8, |
| 55 | TCG_REG_R9, |
| 56 | TCG_REG_R10, |
| 57 | TCG_REG_R11, |
| 58 | TCG_REG_R12, |
| 59 | TCG_REG_R13, |
| 60 | TCG_REG_R14, |
| 61 | }; |
| 62 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 63 | static const int tcg_target_call_iarg_regs[4] = { |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 64 | TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 |
| 65 | }; |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 66 | static const int tcg_target_call_oarg_regs[2] = { |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 67 | TCG_REG_R0, TCG_REG_R1 |
| 68 | }; |
| 69 | |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 70 | static void patch_reloc(uint8_t *code_ptr, int type, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 71 | tcg_target_long value, tcg_target_long addend) |
| 72 | { |
| 73 | switch (type) { |
| 74 | case R_ARM_ABS32: |
| 75 | *(uint32_t *) code_ptr = value; |
| 76 | break; |
| 77 | |
| 78 | case R_ARM_CALL: |
| 79 | case R_ARM_JUMP24: |
| 80 | default: |
| 81 | tcg_abort(); |
| 82 | |
| 83 | case R_ARM_PC24: |
balrog | eae6ce5 | 2008-05-24 22:56:51 +0000 | [diff] [blame] | 84 | *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) | |
balrog | e936243 | 2008-05-23 18:50:44 +0000 | [diff] [blame] | 85 | (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 86 | break; |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | /* maximum number of register used for input function arguments */ |
| 91 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
| 92 | { |
| 93 | return 4; |
| 94 | } |
| 95 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 96 | /* parse target specific constraints */ |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 97 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 98 | { |
| 99 | const char *ct_str; |
| 100 | |
| 101 | ct_str = *pct_str; |
| 102 | switch (ct_str[0]) { |
| 103 | case 'r': |
| 104 | #ifndef CONFIG_SOFTMMU |
| 105 | case 'd': |
| 106 | case 'D': |
| 107 | case 'x': |
| 108 | case 'X': |
| 109 | #endif |
| 110 | ct->ct |= TCG_CT_REG; |
| 111 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 112 | break; |
| 113 | |
| 114 | #ifdef CONFIG_SOFTMMU |
balrog | d0660ed | 2008-05-24 23:12:19 +0000 | [diff] [blame] | 115 | /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */ |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 116 | case 'x': |
| 117 | ct->ct |= TCG_CT_REG; |
| 118 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 119 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
| 120 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 121 | break; |
| 122 | |
balrog | d0660ed | 2008-05-24 23:12:19 +0000 | [diff] [blame] | 123 | /* qemu_ld64 data_reg */ |
| 124 | case 'd': |
| 125 | ct->ct |= TCG_CT_REG; |
| 126 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 127 | /* r1 is still needed to load data_reg2, so don't use it. */ |
| 128 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
| 129 | break; |
| 130 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 131 | /* qemu_ld/st64 data_reg2 */ |
| 132 | case 'D': |
| 133 | ct->ct |= TCG_CT_REG; |
| 134 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 135 | /* r0, r1 and optionally r2 will be overwritten by the address |
| 136 | * and the low word of data, so don't use these. */ |
| 137 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
| 138 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
| 139 | # if TARGET_LONG_BITS == 64 |
| 140 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); |
| 141 | # endif |
| 142 | break; |
| 143 | |
| 144 | # if TARGET_LONG_BITS == 64 |
| 145 | /* qemu_ld/st addr_reg2 */ |
| 146 | case 'X': |
| 147 | ct->ct |= TCG_CT_REG; |
| 148 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 149 | /* r0 will be overwritten by the low word of base, so don't use it. */ |
| 150 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 151 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 152 | break; |
| 153 | # endif |
| 154 | #endif |
| 155 | |
| 156 | case '1': |
| 157 | ct->ct |= TCG_CT_REG; |
| 158 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 159 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
| 160 | break; |
| 161 | |
| 162 | case '2': |
| 163 | ct->ct |= TCG_CT_REG; |
| 164 | tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); |
| 165 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); |
| 166 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); |
| 167 | break; |
| 168 | |
| 169 | default: |
| 170 | return -1; |
| 171 | } |
| 172 | ct_str++; |
| 173 | *pct_str = ct_str; |
| 174 | |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | /* Test if a constant matches the constraint. |
| 179 | * TODO: define constraints for: |
| 180 | * |
| 181 | * ldr/str offset: between -0xfff and 0xfff |
| 182 | * ldrh/strh offset: between -0xff and 0xff |
| 183 | * mov operand2: values represented with x << (2 * y), x < 0x100 |
| 184 | * add, sub, eor...: ditto |
| 185 | */ |
| 186 | static inline int tcg_target_const_match(tcg_target_long val, |
| 187 | const TCGArgConstraint *arg_ct) |
| 188 | { |
| 189 | int ct; |
| 190 | ct = arg_ct->ct; |
| 191 | if (ct & TCG_CT_CONST) |
| 192 | return 1; |
| 193 | else |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | enum arm_data_opc_e { |
| 198 | ARITH_AND = 0x0, |
| 199 | ARITH_EOR = 0x1, |
| 200 | ARITH_SUB = 0x2, |
| 201 | ARITH_RSB = 0x3, |
| 202 | ARITH_ADD = 0x4, |
| 203 | ARITH_ADC = 0x5, |
| 204 | ARITH_SBC = 0x6, |
| 205 | ARITH_RSC = 0x7, |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 206 | ARITH_TST = 0x8, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 207 | ARITH_CMP = 0xa, |
| 208 | ARITH_CMN = 0xb, |
| 209 | ARITH_ORR = 0xc, |
| 210 | ARITH_MOV = 0xd, |
| 211 | ARITH_BIC = 0xe, |
| 212 | ARITH_MVN = 0xf, |
| 213 | }; |
| 214 | |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 215 | #define TO_CPSR(opc) \ |
| 216 | ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20) |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 217 | |
| 218 | #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) |
| 219 | #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) |
| 220 | #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) |
| 221 | #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) |
| 222 | #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) |
| 223 | #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) |
| 224 | #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) |
| 225 | #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) |
| 226 | |
| 227 | enum arm_cond_code_e { |
| 228 | COND_EQ = 0x0, |
| 229 | COND_NE = 0x1, |
| 230 | COND_CS = 0x2, /* Unsigned greater or equal */ |
| 231 | COND_CC = 0x3, /* Unsigned less than */ |
| 232 | COND_MI = 0x4, /* Negative */ |
| 233 | COND_PL = 0x5, /* Zero or greater */ |
| 234 | COND_VS = 0x6, /* Overflow */ |
| 235 | COND_VC = 0x7, /* No overflow */ |
| 236 | COND_HI = 0x8, /* Unsigned greater than */ |
| 237 | COND_LS = 0x9, /* Unsigned less or equal */ |
| 238 | COND_GE = 0xa, |
| 239 | COND_LT = 0xb, |
| 240 | COND_GT = 0xc, |
| 241 | COND_LE = 0xd, |
| 242 | COND_AL = 0xe, |
| 243 | }; |
| 244 | |
| 245 | static const uint8_t tcg_cond_to_arm_cond[10] = { |
| 246 | [TCG_COND_EQ] = COND_EQ, |
| 247 | [TCG_COND_NE] = COND_NE, |
| 248 | [TCG_COND_LT] = COND_LT, |
| 249 | [TCG_COND_GE] = COND_GE, |
| 250 | [TCG_COND_LE] = COND_LE, |
| 251 | [TCG_COND_GT] = COND_GT, |
| 252 | /* unsigned */ |
| 253 | [TCG_COND_LTU] = COND_CC, |
| 254 | [TCG_COND_GEU] = COND_CS, |
| 255 | [TCG_COND_LEU] = COND_LS, |
| 256 | [TCG_COND_GTU] = COND_HI, |
| 257 | }; |
| 258 | |
| 259 | static inline void tcg_out_bx(TCGContext *s, int cond, int rn) |
| 260 | { |
| 261 | tcg_out32(s, (cond << 28) | 0x012fff10 | rn); |
| 262 | } |
| 263 | |
| 264 | static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) |
| 265 | { |
| 266 | tcg_out32(s, (cond << 28) | 0x0a000000 | |
| 267 | (((offset - 8) >> 2) & 0x00ffffff)); |
| 268 | } |
| 269 | |
balrog | e936243 | 2008-05-23 18:50:44 +0000 | [diff] [blame] | 270 | static inline void tcg_out_b_noaddr(TCGContext *s, int cond) |
| 271 | { |
| 272 | #ifdef WORDS_BIGENDIAN |
| 273 | tcg_out8(s, (cond << 4) | 0x0a); |
| 274 | s->code_ptr += 3; |
| 275 | #else |
| 276 | s->code_ptr += 3; |
| 277 | tcg_out8(s, (cond << 4) | 0x0a); |
| 278 | #endif |
| 279 | } |
| 280 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 281 | static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) |
| 282 | { |
| 283 | tcg_out32(s, (cond << 28) | 0x0b000000 | |
| 284 | (((offset - 8) >> 2) & 0x00ffffff)); |
| 285 | } |
| 286 | |
| 287 | static inline void tcg_out_dat_reg(TCGContext *s, |
| 288 | int cond, int opc, int rd, int rn, int rm, int shift) |
| 289 | { |
| 290 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) | |
| 291 | (rn << 16) | (rd << 12) | shift | rm); |
| 292 | } |
| 293 | |
| 294 | static inline void tcg_out_dat_reg2(TCGContext *s, |
| 295 | int cond, int opc0, int opc1, int rd0, int rd1, |
| 296 | int rn0, int rn1, int rm0, int rm1, int shift) |
| 297 | { |
| 298 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) | |
| 299 | (rn0 << 16) | (rd0 << 12) | shift | rm0); |
| 300 | tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) | |
| 301 | (rn1 << 16) | (rd1 << 12) | shift | rm1); |
| 302 | } |
| 303 | |
| 304 | static inline void tcg_out_dat_imm(TCGContext *s, |
| 305 | int cond, int opc, int rd, int rn, int im) |
| 306 | { |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 307 | tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 308 | (rn << 16) | (rd << 12) | im); |
| 309 | } |
| 310 | |
| 311 | static inline void tcg_out_movi32(TCGContext *s, |
| 312 | int cond, int rd, int32_t arg) |
| 313 | { |
| 314 | int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8); |
| 315 | |
| 316 | /* TODO: This is very suboptimal, we can easily have a constant |
| 317 | * pool somewhere after all the instructions. */ |
| 318 | |
| 319 | if (arg < 0 && arg > -0x100) |
| 320 | return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff); |
| 321 | |
| 322 | if (offset < 0x100 && offset > -0x100) |
| 323 | return offset >= 0 ? |
| 324 | tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) : |
| 325 | tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset); |
| 326 | |
| 327 | tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff); |
| 328 | if (arg & 0x0000ff00) |
| 329 | tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd, |
| 330 | ((arg >> 8) & 0xff) | 0xc00); |
| 331 | if (arg & 0x00ff0000) |
| 332 | tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd, |
| 333 | ((arg >> 16) & 0xff) | 0x800); |
| 334 | if (arg & 0xff000000) |
| 335 | tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd, |
| 336 | ((arg >> 24) & 0xff) | 0x400); |
| 337 | } |
| 338 | |
| 339 | static inline void tcg_out_mul32(TCGContext *s, |
| 340 | int cond, int rd, int rs, int rm) |
| 341 | { |
| 342 | if (rd != rm) |
| 343 | tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) | |
| 344 | (rs << 8) | 0x90 | rm); |
| 345 | else if (rd != rs) |
| 346 | tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) | |
| 347 | (rm << 8) | 0x90 | rs); |
| 348 | else { |
| 349 | tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) | |
| 350 | (rs << 8) | 0x90 | rm); |
| 351 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 352 | rd, 0, 8, SHIFT_IMM_LSL(0)); |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | static inline void tcg_out_umull32(TCGContext *s, |
| 357 | int cond, int rd0, int rd1, int rs, int rm) |
| 358 | { |
| 359 | if (rd0 != rm && rd1 != rm) |
| 360 | tcg_out32(s, (cond << 28) | 0x800090 | |
| 361 | (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm); |
| 362 | else if (rd0 != rs && rd1 != rs) |
| 363 | tcg_out32(s, (cond << 28) | 0x800090 | |
| 364 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs); |
| 365 | else { |
| 366 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 367 | TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0)); |
| 368 | tcg_out32(s, (cond << 28) | 0x800098 | |
| 369 | (rd1 << 16) | (rd0 << 12) | (rs << 8)); |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | static inline void tcg_out_smull32(TCGContext *s, |
| 374 | int cond, int rd0, int rd1, int rs, int rm) |
| 375 | { |
| 376 | if (rd0 != rm && rd1 != rm) |
| 377 | tcg_out32(s, (cond << 28) | 0xc00090 | |
| 378 | (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm); |
| 379 | else if (rd0 != rs && rd1 != rs) |
| 380 | tcg_out32(s, (cond << 28) | 0xc00090 | |
| 381 | (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs); |
| 382 | else { |
| 383 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 384 | TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0)); |
| 385 | tcg_out32(s, (cond << 28) | 0xc00098 | |
| 386 | (rd1 << 16) | (rd0 << 12) | (rs << 8)); |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | static inline void tcg_out_ld32_12(TCGContext *s, int cond, |
| 391 | int rd, int rn, tcg_target_long im) |
| 392 | { |
| 393 | if (im >= 0) |
| 394 | tcg_out32(s, (cond << 28) | 0x05900000 | |
| 395 | (rn << 16) | (rd << 12) | (im & 0xfff)); |
| 396 | else |
| 397 | tcg_out32(s, (cond << 28) | 0x05100000 | |
| 398 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); |
| 399 | } |
| 400 | |
| 401 | static inline void tcg_out_st32_12(TCGContext *s, int cond, |
| 402 | int rd, int rn, tcg_target_long im) |
| 403 | { |
| 404 | if (im >= 0) |
| 405 | tcg_out32(s, (cond << 28) | 0x05800000 | |
| 406 | (rn << 16) | (rd << 12) | (im & 0xfff)); |
| 407 | else |
| 408 | tcg_out32(s, (cond << 28) | 0x05000000 | |
| 409 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); |
| 410 | } |
| 411 | |
| 412 | static inline void tcg_out_ld32_r(TCGContext *s, int cond, |
| 413 | int rd, int rn, int rm) |
| 414 | { |
| 415 | tcg_out32(s, (cond << 28) | 0x07900000 | |
| 416 | (rn << 16) | (rd << 12) | rm); |
| 417 | } |
| 418 | |
| 419 | static inline void tcg_out_st32_r(TCGContext *s, int cond, |
| 420 | int rd, int rn, int rm) |
| 421 | { |
| 422 | tcg_out32(s, (cond << 28) | 0x07800000 | |
| 423 | (rn << 16) | (rd << 12) | rm); |
| 424 | } |
| 425 | |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 426 | /* Register pre-increment with base writeback. */ |
| 427 | static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, |
| 428 | int rd, int rn, int rm) |
| 429 | { |
| 430 | tcg_out32(s, (cond << 28) | 0x07b00000 | |
| 431 | (rn << 16) | (rd << 12) | rm); |
| 432 | } |
| 433 | |
| 434 | static inline void tcg_out_st32_rwb(TCGContext *s, int cond, |
| 435 | int rd, int rn, int rm) |
| 436 | { |
| 437 | tcg_out32(s, (cond << 28) | 0x07a00000 | |
| 438 | (rn << 16) | (rd << 12) | rm); |
| 439 | } |
| 440 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 441 | static inline void tcg_out_ld16u_8(TCGContext *s, int cond, |
| 442 | int rd, int rn, tcg_target_long im) |
| 443 | { |
| 444 | if (im >= 0) |
| 445 | tcg_out32(s, (cond << 28) | 0x01d000b0 | |
| 446 | (rn << 16) | (rd << 12) | |
| 447 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 448 | else |
| 449 | tcg_out32(s, (cond << 28) | 0x015000b0 | |
| 450 | (rn << 16) | (rd << 12) | |
| 451 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 452 | } |
| 453 | |
| 454 | static inline void tcg_out_st16u_8(TCGContext *s, int cond, |
| 455 | int rd, int rn, tcg_target_long im) |
| 456 | { |
| 457 | if (im >= 0) |
| 458 | tcg_out32(s, (cond << 28) | 0x01c000b0 | |
| 459 | (rn << 16) | (rd << 12) | |
| 460 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 461 | else |
| 462 | tcg_out32(s, (cond << 28) | 0x014000b0 | |
| 463 | (rn << 16) | (rd << 12) | |
| 464 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 465 | } |
| 466 | |
| 467 | static inline void tcg_out_ld16u_r(TCGContext *s, int cond, |
| 468 | int rd, int rn, int rm) |
| 469 | { |
| 470 | tcg_out32(s, (cond << 28) | 0x019000b0 | |
| 471 | (rn << 16) | (rd << 12) | rm); |
| 472 | } |
| 473 | |
| 474 | static inline void tcg_out_st16u_r(TCGContext *s, int cond, |
| 475 | int rd, int rn, int rm) |
| 476 | { |
| 477 | tcg_out32(s, (cond << 28) | 0x018000b0 | |
| 478 | (rn << 16) | (rd << 12) | rm); |
| 479 | } |
| 480 | |
| 481 | static inline void tcg_out_ld16s_8(TCGContext *s, int cond, |
| 482 | int rd, int rn, tcg_target_long im) |
| 483 | { |
| 484 | if (im >= 0) |
| 485 | tcg_out32(s, (cond << 28) | 0x01d000f0 | |
| 486 | (rn << 16) | (rd << 12) | |
| 487 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 488 | else |
| 489 | tcg_out32(s, (cond << 28) | 0x015000f0 | |
| 490 | (rn << 16) | (rd << 12) | |
| 491 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 492 | } |
| 493 | |
| 494 | static inline void tcg_out_st16s_8(TCGContext *s, int cond, |
| 495 | int rd, int rn, tcg_target_long im) |
| 496 | { |
| 497 | if (im >= 0) |
| 498 | tcg_out32(s, (cond << 28) | 0x01c000f0 | |
| 499 | (rn << 16) | (rd << 12) | |
| 500 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 501 | else |
| 502 | tcg_out32(s, (cond << 28) | 0x014000f0 | |
| 503 | (rn << 16) | (rd << 12) | |
| 504 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 505 | } |
| 506 | |
| 507 | static inline void tcg_out_ld16s_r(TCGContext *s, int cond, |
| 508 | int rd, int rn, int rm) |
| 509 | { |
| 510 | tcg_out32(s, (cond << 28) | 0x019000f0 | |
| 511 | (rn << 16) | (rd << 12) | rm); |
| 512 | } |
| 513 | |
| 514 | static inline void tcg_out_st16s_r(TCGContext *s, int cond, |
| 515 | int rd, int rn, int rm) |
| 516 | { |
| 517 | tcg_out32(s, (cond << 28) | 0x018000f0 | |
| 518 | (rn << 16) | (rd << 12) | rm); |
| 519 | } |
| 520 | |
| 521 | static inline void tcg_out_ld8_12(TCGContext *s, int cond, |
| 522 | int rd, int rn, tcg_target_long im) |
| 523 | { |
| 524 | if (im >= 0) |
| 525 | tcg_out32(s, (cond << 28) | 0x05d00000 | |
| 526 | (rn << 16) | (rd << 12) | (im & 0xfff)); |
| 527 | else |
| 528 | tcg_out32(s, (cond << 28) | 0x05500000 | |
| 529 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); |
| 530 | } |
| 531 | |
| 532 | static inline void tcg_out_st8_12(TCGContext *s, int cond, |
| 533 | int rd, int rn, tcg_target_long im) |
| 534 | { |
| 535 | if (im >= 0) |
| 536 | tcg_out32(s, (cond << 28) | 0x05c00000 | |
| 537 | (rn << 16) | (rd << 12) | (im & 0xfff)); |
| 538 | else |
| 539 | tcg_out32(s, (cond << 28) | 0x05400000 | |
| 540 | (rn << 16) | (rd << 12) | ((-im) & 0xfff)); |
| 541 | } |
| 542 | |
| 543 | static inline void tcg_out_ld8_r(TCGContext *s, int cond, |
| 544 | int rd, int rn, int rm) |
| 545 | { |
| 546 | tcg_out32(s, (cond << 28) | 0x07d00000 | |
| 547 | (rn << 16) | (rd << 12) | rm); |
| 548 | } |
| 549 | |
| 550 | static inline void tcg_out_st8_r(TCGContext *s, int cond, |
| 551 | int rd, int rn, int rm) |
| 552 | { |
| 553 | tcg_out32(s, (cond << 28) | 0x07c00000 | |
| 554 | (rn << 16) | (rd << 12) | rm); |
| 555 | } |
| 556 | |
| 557 | static inline void tcg_out_ld8s_8(TCGContext *s, int cond, |
| 558 | int rd, int rn, tcg_target_long im) |
| 559 | { |
| 560 | if (im >= 0) |
| 561 | tcg_out32(s, (cond << 28) | 0x01d000d0 | |
| 562 | (rn << 16) | (rd << 12) | |
| 563 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 564 | else |
| 565 | tcg_out32(s, (cond << 28) | 0x015000d0 | |
| 566 | (rn << 16) | (rd << 12) | |
| 567 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 568 | } |
| 569 | |
| 570 | static inline void tcg_out_st8s_8(TCGContext *s, int cond, |
| 571 | int rd, int rn, tcg_target_long im) |
| 572 | { |
| 573 | if (im >= 0) |
| 574 | tcg_out32(s, (cond << 28) | 0x01c000d0 | |
| 575 | (rn << 16) | (rd << 12) | |
| 576 | ((im & 0xf0) << 4) | (im & 0xf)); |
| 577 | else |
| 578 | tcg_out32(s, (cond << 28) | 0x014000d0 | |
| 579 | (rn << 16) | (rd << 12) | |
| 580 | (((-im) & 0xf0) << 4) | ((-im) & 0xf)); |
| 581 | } |
| 582 | |
| 583 | static inline void tcg_out_ld8s_r(TCGContext *s, int cond, |
| 584 | int rd, int rn, int rm) |
| 585 | { |
balrog | 204c167 | 2008-05-20 11:28:35 +0000 | [diff] [blame] | 586 | tcg_out32(s, (cond << 28) | 0x019000d0 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 587 | (rn << 16) | (rd << 12) | rm); |
| 588 | } |
| 589 | |
| 590 | static inline void tcg_out_st8s_r(TCGContext *s, int cond, |
| 591 | int rd, int rn, int rm) |
| 592 | { |
balrog | 204c167 | 2008-05-20 11:28:35 +0000 | [diff] [blame] | 593 | tcg_out32(s, (cond << 28) | 0x018000d0 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 594 | (rn << 16) | (rd << 12) | rm); |
| 595 | } |
| 596 | |
| 597 | static inline void tcg_out_ld32u(TCGContext *s, int cond, |
| 598 | int rd, int rn, int32_t offset) |
| 599 | { |
| 600 | if (offset > 0xfff || offset < -0xfff) { |
| 601 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 602 | tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8); |
| 603 | } else |
| 604 | tcg_out_ld32_12(s, cond, rd, rn, offset); |
| 605 | } |
| 606 | |
| 607 | static inline void tcg_out_st32(TCGContext *s, int cond, |
| 608 | int rd, int rn, int32_t offset) |
| 609 | { |
| 610 | if (offset > 0xfff || offset < -0xfff) { |
| 611 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 612 | tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8); |
| 613 | } else |
| 614 | tcg_out_st32_12(s, cond, rd, rn, offset); |
| 615 | } |
| 616 | |
| 617 | static inline void tcg_out_ld16u(TCGContext *s, int cond, |
| 618 | int rd, int rn, int32_t offset) |
| 619 | { |
| 620 | if (offset > 0xff || offset < -0xff) { |
| 621 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 622 | tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8); |
| 623 | } else |
| 624 | tcg_out_ld16u_8(s, cond, rd, rn, offset); |
| 625 | } |
| 626 | |
| 627 | static inline void tcg_out_ld16s(TCGContext *s, int cond, |
| 628 | int rd, int rn, int32_t offset) |
| 629 | { |
| 630 | if (offset > 0xff || offset < -0xff) { |
| 631 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 632 | tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8); |
| 633 | } else |
| 634 | tcg_out_ld16s_8(s, cond, rd, rn, offset); |
| 635 | } |
| 636 | |
| 637 | static inline void tcg_out_st16u(TCGContext *s, int cond, |
| 638 | int rd, int rn, int32_t offset) |
| 639 | { |
| 640 | if (offset > 0xff || offset < -0xff) { |
| 641 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 642 | tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8); |
| 643 | } else |
| 644 | tcg_out_st16u_8(s, cond, rd, rn, offset); |
| 645 | } |
| 646 | |
| 647 | static inline void tcg_out_ld8u(TCGContext *s, int cond, |
| 648 | int rd, int rn, int32_t offset) |
| 649 | { |
| 650 | if (offset > 0xfff || offset < -0xfff) { |
| 651 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 652 | tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8); |
| 653 | } else |
| 654 | tcg_out_ld8_12(s, cond, rd, rn, offset); |
| 655 | } |
| 656 | |
| 657 | static inline void tcg_out_ld8s(TCGContext *s, int cond, |
| 658 | int rd, int rn, int32_t offset) |
| 659 | { |
| 660 | if (offset > 0xff || offset < -0xff) { |
| 661 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 662 | tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8); |
| 663 | } else |
| 664 | tcg_out_ld8s_8(s, cond, rd, rn, offset); |
| 665 | } |
| 666 | |
| 667 | static inline void tcg_out_st8u(TCGContext *s, int cond, |
| 668 | int rd, int rn, int32_t offset) |
| 669 | { |
| 670 | if (offset > 0xfff || offset < -0xfff) { |
| 671 | tcg_out_movi32(s, cond, TCG_REG_R8, offset); |
| 672 | tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8); |
| 673 | } else |
| 674 | tcg_out_st8_12(s, cond, rd, rn, offset); |
| 675 | } |
| 676 | |
| 677 | static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr) |
| 678 | { |
| 679 | int32_t val; |
| 680 | |
| 681 | val = addr - (tcg_target_long) s->code_ptr; |
| 682 | if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd) |
| 683 | tcg_out_b(s, cond, val); |
| 684 | else { |
| 685 | #if 1 |
| 686 | tcg_abort(); |
| 687 | #else |
| 688 | if (cond == COND_AL) { |
| 689 | tcg_out_ld32_12(s, COND_AL, 15, 15, -4); |
| 690 | tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */ |
| 691 | } else { |
| 692 | tcg_out_movi32(s, cond, TCG_REG_R8, val - 8); |
| 693 | tcg_out_dat_reg(s, cond, ARITH_ADD, |
| 694 | 15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0)); |
| 695 | } |
| 696 | #endif |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr) |
| 701 | { |
| 702 | int32_t val; |
| 703 | |
| 704 | #ifdef SAVE_LR |
| 705 | tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0)); |
| 706 | #endif |
| 707 | |
| 708 | val = addr - (tcg_target_long) s->code_ptr; |
| 709 | if (val < 0x01fffffd && val > -0x01fffffd) |
| 710 | tcg_out_bl(s, cond, val); |
| 711 | else { |
| 712 | #if 1 |
| 713 | tcg_abort(); |
| 714 | #else |
| 715 | if (cond == COND_AL) { |
| 716 | tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4); |
| 717 | tcg_out_ld32_12(s, COND_AL, 15, 15, -4); |
| 718 | tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */ |
| 719 | } else { |
| 720 | tcg_out_movi32(s, cond, TCG_REG_R9, addr); |
| 721 | tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15); |
| 722 | tcg_out_bx(s, cond, TCG_REG_R9); |
| 723 | } |
| 724 | #endif |
| 725 | } |
| 726 | |
| 727 | #ifdef SAVE_LR |
| 728 | tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0)); |
| 729 | #endif |
| 730 | } |
| 731 | |
| 732 | static inline void tcg_out_callr(TCGContext *s, int cond, int arg) |
| 733 | { |
| 734 | #ifdef SAVE_LR |
| 735 | tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0)); |
| 736 | #endif |
| 737 | /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */ |
| 738 | tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0)); |
| 739 | tcg_out_bx(s, cond, arg); |
| 740 | #ifdef SAVE_LR |
| 741 | tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0)); |
| 742 | #endif |
| 743 | } |
| 744 | |
| 745 | static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index) |
| 746 | { |
| 747 | TCGLabel *l = &s->labels[label_index]; |
| 748 | |
| 749 | if (l->has_value) |
| 750 | tcg_out_goto(s, cond, l->u.value); |
| 751 | else if (cond == COND_AL) { |
| 752 | tcg_out_ld32_12(s, COND_AL, 15, 15, -4); |
| 753 | tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337); |
| 754 | s->code_ptr += 4; |
| 755 | } else { |
| 756 | /* Probably this should be preferred even for COND_AL... */ |
| 757 | tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337); |
balrog | e936243 | 2008-05-23 18:50:44 +0000 | [diff] [blame] | 758 | tcg_out_b_noaddr(s, cond); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 759 | } |
| 760 | } |
| 761 | |
| 762 | static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args, |
| 763 | void *helper_div, void *helper_rem, int shift) |
| 764 | { |
| 765 | int div_reg = args[0]; |
| 766 | int rem_reg = args[1]; |
| 767 | |
| 768 | /* stmdb sp!, { r0 - r3, ip, lr } */ |
| 769 | /* (Note that we need an even number of registers as per EABI) */ |
| 770 | tcg_out32(s, (cond << 28) | 0x092d500f); |
| 771 | |
| 772 | tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0)); |
| 773 | tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0)); |
| 774 | tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0)); |
| 775 | tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift); |
| 776 | |
| 777 | tcg_out_call(s, cond, (uint32_t) helper_div); |
| 778 | tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0)); |
| 779 | |
| 780 | /* ldmia sp, { r0 - r3, fp, lr } */ |
| 781 | tcg_out32(s, (cond << 28) | 0x089d500f); |
| 782 | |
| 783 | tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0)); |
| 784 | tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0)); |
| 785 | tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0)); |
| 786 | tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift); |
| 787 | |
| 788 | tcg_out_call(s, cond, (uint32_t) helper_rem); |
| 789 | |
| 790 | tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0)); |
| 791 | tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0)); |
| 792 | |
| 793 | /* ldr r0, [sp], #4 */ |
| 794 | if (rem_reg != 0 && div_reg != 0) |
| 795 | tcg_out32(s, (cond << 28) | 0x04bd0004); |
| 796 | /* ldr r1, [sp], #4 */ |
| 797 | if (rem_reg != 1 && div_reg != 1) |
| 798 | tcg_out32(s, (cond << 28) | 0x04bd1004); |
| 799 | /* ldr r2, [sp], #4 */ |
| 800 | if (rem_reg != 2 && div_reg != 2) |
| 801 | tcg_out32(s, (cond << 28) | 0x04bd2004); |
| 802 | /* ldr r3, [sp], #4 */ |
| 803 | if (rem_reg != 3 && div_reg != 3) |
| 804 | tcg_out32(s, (cond << 28) | 0x04bd3004); |
| 805 | /* ldr ip, [sp], #4 */ |
| 806 | if (rem_reg != 12 && div_reg != 12) |
| 807 | tcg_out32(s, (cond << 28) | 0x04bdc004); |
| 808 | /* ldr lr, [sp], #4 */ |
| 809 | if (rem_reg != 14 && div_reg != 14) |
| 810 | tcg_out32(s, (cond << 28) | 0x04bde004); |
| 811 | } |
| 812 | |
| 813 | #ifdef CONFIG_SOFTMMU |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 814 | |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 815 | #include "../../softmmu_defs.h" |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 816 | |
| 817 | static void *qemu_ld_helpers[4] = { |
| 818 | __ldb_mmu, |
| 819 | __ldw_mmu, |
| 820 | __ldl_mmu, |
| 821 | __ldq_mmu, |
| 822 | }; |
| 823 | |
| 824 | static void *qemu_st_helpers[4] = { |
| 825 | __stb_mmu, |
| 826 | __stw_mmu, |
| 827 | __stl_mmu, |
| 828 | __stq_mmu, |
| 829 | }; |
| 830 | #endif |
| 831 | |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 832 | #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) |
| 833 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 834 | static inline void tcg_out_qemu_ld(TCGContext *s, int cond, |
| 835 | const TCGArg *args, int opc) |
| 836 | { |
| 837 | int addr_reg, data_reg, data_reg2; |
| 838 | #ifdef CONFIG_SOFTMMU |
| 839 | int mem_index, s_bits; |
| 840 | # if TARGET_LONG_BITS == 64 |
| 841 | int addr_reg2; |
| 842 | # endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 843 | uint32_t *label_ptr; |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 844 | #endif |
| 845 | |
| 846 | data_reg = *args++; |
| 847 | if (opc == 3) |
| 848 | data_reg2 = *args++; |
| 849 | else |
| 850 | data_reg2 = 0; /* surpress warning */ |
| 851 | addr_reg = *args++; |
| 852 | #if TARGET_LONG_BITS == 64 |
| 853 | addr_reg2 = *args++; |
| 854 | #endif |
| 855 | #ifdef CONFIG_SOFTMMU |
| 856 | mem_index = *args; |
| 857 | s_bits = opc & 3; |
| 858 | |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 859 | /* Should generate something like the following: |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 860 | * shr r8, addr_reg, #TARGET_PAGE_BITS |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 861 | * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 862 | * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 863 | */ |
| 864 | # if CPU_TLB_BITS > 8 |
| 865 | # error |
| 866 | # endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 867 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 868 | 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 869 | tcg_out_dat_imm(s, COND_AL, ARITH_AND, |
| 870 | 0, 8, CPU_TLB_SIZE - 1); |
| 871 | tcg_out_dat_reg(s, COND_AL, ARITH_ADD, |
| 872 | 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 873 | /* In the |
| 874 | * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))] |
| 875 | * below, the offset is likely to exceed 12 bits if mem_index != 0 and |
| 876 | * not exceed otherwise, so use an |
| 877 | * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table) |
| 878 | * before. |
| 879 | */ |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 880 | if (mem_index) |
| 881 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0, |
| 882 | (mem_index << (TLB_SHIFT & 1)) | |
| 883 | ((16 - (TLB_SHIFT >> 1)) << 8)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 884 | tcg_out_ld32_12(s, COND_AL, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 885 | offsetof(CPUState, tlb_table[0][0].addr_read)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 886 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, |
| 887 | 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 888 | /* Check alignment. */ |
| 889 | if (s_bits) |
| 890 | tcg_out_dat_imm(s, COND_EQ, ARITH_TST, |
| 891 | 0, addr_reg, (1 << s_bits) - 1); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 892 | # if TARGET_LONG_BITS == 64 |
| 893 | /* XXX: possibly we could use a block data load or writeback in |
| 894 | * the first access. */ |
| 895 | tcg_out_ld32_12(s, COND_EQ, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 896 | offsetof(CPUState, tlb_table[0][0].addr_read) + 4); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 897 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, |
| 898 | 0, 1, addr_reg2, SHIFT_IMM_LSL(0)); |
| 899 | # endif |
| 900 | tcg_out_ld32_12(s, COND_EQ, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 901 | offsetof(CPUState, tlb_table[0][0].addend)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 902 | |
| 903 | switch (opc) { |
| 904 | case 0: |
| 905 | tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 906 | break; |
| 907 | case 0 | 4: |
| 908 | tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 909 | break; |
| 910 | case 1: |
| 911 | tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 912 | break; |
| 913 | case 1 | 4: |
| 914 | tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 915 | break; |
| 916 | case 2: |
| 917 | default: |
| 918 | tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 919 | break; |
| 920 | case 3: |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 921 | tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 922 | tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4); |
| 923 | break; |
| 924 | } |
| 925 | |
| 926 | label_ptr = (void *) s->code_ptr; |
| 927 | tcg_out_b(s, COND_EQ, 8); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 928 | |
| 929 | # ifdef SAVE_LR |
| 930 | tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0)); |
| 931 | # endif |
| 932 | |
| 933 | /* TODO: move this code to where the constants pool will be */ |
| 934 | if (addr_reg) |
| 935 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 936 | 0, 0, addr_reg, SHIFT_IMM_LSL(0)); |
| 937 | # if TARGET_LONG_BITS == 32 |
| 938 | tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index); |
| 939 | # else |
| 940 | if (addr_reg2 != 1) |
| 941 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 942 | 1, 0, addr_reg2, SHIFT_IMM_LSL(0)); |
| 943 | tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); |
| 944 | # endif |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 945 | tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] - |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 946 | (tcg_target_long) s->code_ptr); |
| 947 | |
| 948 | switch (opc) { |
| 949 | case 0 | 4: |
| 950 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 951 | 0, 0, 0, SHIFT_IMM_LSL(24)); |
| 952 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 953 | data_reg, 0, 0, SHIFT_IMM_ASR(24)); |
| 954 | break; |
| 955 | case 1 | 4: |
| 956 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 957 | 0, 0, 0, SHIFT_IMM_LSL(16)); |
| 958 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 959 | data_reg, 0, 0, SHIFT_IMM_ASR(16)); |
| 960 | break; |
| 961 | case 0: |
| 962 | case 1: |
| 963 | case 2: |
| 964 | default: |
| 965 | if (data_reg) |
| 966 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 967 | data_reg, 0, 0, SHIFT_IMM_LSL(0)); |
| 968 | break; |
| 969 | case 3: |
balrog | d0660ed | 2008-05-24 23:12:19 +0000 | [diff] [blame] | 970 | if (data_reg != 0) |
| 971 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 972 | data_reg, 0, 0, SHIFT_IMM_LSL(0)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 973 | if (data_reg2 != 1) |
| 974 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 975 | data_reg2, 0, 1, SHIFT_IMM_LSL(0)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 976 | break; |
| 977 | } |
| 978 | |
| 979 | # ifdef SAVE_LR |
| 980 | tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0)); |
| 981 | # endif |
| 982 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 983 | *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2; |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 984 | #else |
| 985 | switch (opc) { |
| 986 | case 0: |
| 987 | tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0); |
| 988 | break; |
| 989 | case 0 | 4: |
| 990 | tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0); |
| 991 | break; |
| 992 | case 1: |
| 993 | tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0); |
| 994 | break; |
| 995 | case 1 | 4: |
| 996 | tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0); |
| 997 | break; |
| 998 | case 2: |
| 999 | default: |
| 1000 | tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); |
| 1001 | break; |
| 1002 | case 3: |
balrog | eae6ce5 | 2008-05-24 22:56:51 +0000 | [diff] [blame] | 1003 | /* TODO: use block load - |
| 1004 | * check that data_reg2 > data_reg or the other way */ |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1005 | tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); |
| 1006 | tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4); |
| 1007 | break; |
| 1008 | } |
| 1009 | #endif |
| 1010 | } |
| 1011 | |
| 1012 | static inline void tcg_out_qemu_st(TCGContext *s, int cond, |
| 1013 | const TCGArg *args, int opc) |
| 1014 | { |
| 1015 | int addr_reg, data_reg, data_reg2; |
| 1016 | #ifdef CONFIG_SOFTMMU |
| 1017 | int mem_index, s_bits; |
| 1018 | # if TARGET_LONG_BITS == 64 |
| 1019 | int addr_reg2; |
| 1020 | # endif |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1021 | uint32_t *label_ptr; |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1022 | #endif |
| 1023 | |
| 1024 | data_reg = *args++; |
| 1025 | if (opc == 3) |
| 1026 | data_reg2 = *args++; |
| 1027 | else |
| 1028 | data_reg2 = 0; /* surpress warning */ |
| 1029 | addr_reg = *args++; |
| 1030 | #if TARGET_LONG_BITS == 64 |
| 1031 | addr_reg2 = *args++; |
| 1032 | #endif |
| 1033 | #ifdef CONFIG_SOFTMMU |
| 1034 | mem_index = *args; |
| 1035 | s_bits = opc & 3; |
| 1036 | |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1037 | /* Should generate something like the following: |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1038 | * shr r8, addr_reg, #TARGET_PAGE_BITS |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1039 | * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1040 | * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1041 | */ |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1042 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1043 | 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1044 | tcg_out_dat_imm(s, COND_AL, ARITH_AND, |
| 1045 | 0, 8, CPU_TLB_SIZE - 1); |
| 1046 | tcg_out_dat_reg(s, COND_AL, ARITH_ADD, |
| 1047 | 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1048 | /* In the |
| 1049 | * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))] |
| 1050 | * below, the offset is likely to exceed 12 bits if mem_index != 0 and |
| 1051 | * not exceed otherwise, so use an |
| 1052 | * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table) |
| 1053 | * before. |
| 1054 | */ |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 1055 | if (mem_index) |
| 1056 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0, |
| 1057 | (mem_index << (TLB_SHIFT & 1)) | |
| 1058 | ((16 - (TLB_SHIFT >> 1)) << 8)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1059 | tcg_out_ld32_12(s, COND_AL, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 1060 | offsetof(CPUState, tlb_table[0][0].addr_write)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1061 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, |
| 1062 | 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1063 | /* Check alignment. */ |
| 1064 | if (s_bits) |
| 1065 | tcg_out_dat_imm(s, COND_EQ, ARITH_TST, |
| 1066 | 0, addr_reg, (1 << s_bits) - 1); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1067 | # if TARGET_LONG_BITS == 64 |
| 1068 | /* XXX: possibly we could use a block data load or writeback in |
| 1069 | * the first access. */ |
| 1070 | tcg_out_ld32_12(s, COND_EQ, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 1071 | offsetof(CPUState, tlb_table[0][0].addr_write) |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1072 | + 4); |
| 1073 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, |
| 1074 | 0, 1, addr_reg2, SHIFT_IMM_LSL(0)); |
| 1075 | # endif |
| 1076 | tcg_out_ld32_12(s, COND_EQ, 1, 0, |
balrog | 225b437 | 2008-05-23 12:55:11 +0000 | [diff] [blame] | 1077 | offsetof(CPUState, tlb_table[0][0].addend)); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1078 | |
| 1079 | switch (opc) { |
| 1080 | case 0: |
| 1081 | tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 1082 | break; |
| 1083 | case 0 | 4: |
| 1084 | tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 1085 | break; |
| 1086 | case 1: |
| 1087 | tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 1088 | break; |
| 1089 | case 1 | 4: |
| 1090 | tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 1091 | break; |
| 1092 | case 2: |
| 1093 | default: |
| 1094 | tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1); |
| 1095 | break; |
| 1096 | case 3: |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1097 | tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1098 | tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4); |
| 1099 | break; |
| 1100 | } |
| 1101 | |
| 1102 | label_ptr = (void *) s->code_ptr; |
| 1103 | tcg_out_b(s, COND_EQ, 8); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1104 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1105 | /* TODO: move this code to where the constants pool will be */ |
| 1106 | if (addr_reg) |
| 1107 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1108 | 0, 0, addr_reg, SHIFT_IMM_LSL(0)); |
| 1109 | # if TARGET_LONG_BITS == 32 |
| 1110 | switch (opc) { |
| 1111 | case 0: |
| 1112 | tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff); |
| 1113 | tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); |
| 1114 | break; |
| 1115 | case 1: |
| 1116 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1117 | 1, 0, data_reg, SHIFT_IMM_LSL(16)); |
| 1118 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1119 | 1, 0, 1, SHIFT_IMM_LSR(16)); |
| 1120 | tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); |
| 1121 | break; |
| 1122 | case 2: |
| 1123 | if (data_reg != 1) |
| 1124 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1125 | 1, 0, data_reg, SHIFT_IMM_LSL(0)); |
| 1126 | tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index); |
| 1127 | break; |
| 1128 | case 3: |
| 1129 | if (data_reg != 1) |
| 1130 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1131 | 1, 0, data_reg, SHIFT_IMM_LSL(0)); |
| 1132 | if (data_reg2 != 2) |
| 1133 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1134 | 2, 0, data_reg2, SHIFT_IMM_LSL(0)); |
| 1135 | tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); |
| 1136 | break; |
| 1137 | } |
| 1138 | # else |
| 1139 | if (addr_reg2 != 1) |
| 1140 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1141 | 1, 0, addr_reg2, SHIFT_IMM_LSL(0)); |
| 1142 | switch (opc) { |
| 1143 | case 0: |
| 1144 | tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff); |
| 1145 | tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); |
| 1146 | break; |
| 1147 | case 1: |
| 1148 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1149 | 2, 0, data_reg, SHIFT_IMM_LSL(16)); |
| 1150 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1151 | 2, 0, 2, SHIFT_IMM_LSR(16)); |
| 1152 | tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); |
| 1153 | break; |
| 1154 | case 2: |
| 1155 | if (data_reg != 2) |
| 1156 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1157 | 2, 0, data_reg, SHIFT_IMM_LSL(0)); |
| 1158 | tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); |
| 1159 | break; |
| 1160 | case 3: |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1161 | tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index); |
| 1162 | tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */ |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1163 | if (data_reg != 2) |
| 1164 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1165 | 2, 0, data_reg, SHIFT_IMM_LSL(0)); |
| 1166 | if (data_reg2 != 3) |
| 1167 | tcg_out_dat_reg(s, cond, ARITH_MOV, |
| 1168 | 3, 0, data_reg2, SHIFT_IMM_LSL(0)); |
| 1169 | break; |
| 1170 | } |
| 1171 | # endif |
| 1172 | |
balrog | 91a3c1b | 2008-05-23 18:51:15 +0000 | [diff] [blame] | 1173 | # ifdef SAVE_LR |
| 1174 | tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0)); |
| 1175 | # endif |
| 1176 | |
balrog | 204c167 | 2008-05-20 11:28:35 +0000 | [diff] [blame] | 1177 | tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] - |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1178 | (tcg_target_long) s->code_ptr); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1179 | # if TARGET_LONG_BITS == 64 |
| 1180 | if (opc == 3) |
| 1181 | tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10); |
| 1182 | # endif |
| 1183 | |
| 1184 | # ifdef SAVE_LR |
| 1185 | tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0)); |
| 1186 | # endif |
| 1187 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1188 | *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2; |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1189 | #else |
| 1190 | switch (opc) { |
| 1191 | case 0: |
| 1192 | tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0); |
| 1193 | break; |
| 1194 | case 0 | 4: |
balrog | 204c167 | 2008-05-20 11:28:35 +0000 | [diff] [blame] | 1195 | tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0); |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1196 | break; |
| 1197 | case 1: |
| 1198 | tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0); |
| 1199 | break; |
| 1200 | case 1 | 4: |
| 1201 | tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0); |
| 1202 | break; |
| 1203 | case 2: |
| 1204 | default: |
| 1205 | tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0); |
| 1206 | break; |
| 1207 | case 3: |
balrog | eae6ce5 | 2008-05-24 22:56:51 +0000 | [diff] [blame] | 1208 | /* TODO: use block store - |
| 1209 | * check that data_reg2 > data_reg or the other way */ |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1210 | tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0); |
| 1211 | tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4); |
| 1212 | break; |
| 1213 | } |
| 1214 | #endif |
| 1215 | } |
| 1216 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1217 | static uint8_t *tb_ret_addr; |
| 1218 | |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 1219 | static inline void tcg_out_op(TCGContext *s, int opc, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1220 | const TCGArg *args, const int *const_args) |
| 1221 | { |
| 1222 | int c; |
| 1223 | |
| 1224 | switch (opc) { |
| 1225 | case INDEX_op_exit_tb: |
| 1226 | #ifdef SAVE_LR |
| 1227 | if (args[0] >> 8) |
| 1228 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0); |
| 1229 | else |
| 1230 | tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]); |
| 1231 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0)); |
| 1232 | if (args[0] >> 8) |
| 1233 | tcg_out32(s, args[0]); |
| 1234 | #else |
| 1235 | if (args[0] >> 8) |
| 1236 | tcg_out_ld32_12(s, COND_AL, 0, 15, 0); |
| 1237 | else |
| 1238 | tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]); |
| 1239 | tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr); |
| 1240 | if (args[0] >> 8) |
| 1241 | tcg_out32(s, args[0]); |
| 1242 | #endif |
| 1243 | break; |
| 1244 | case INDEX_op_goto_tb: |
| 1245 | if (s->tb_jmp_offset) { |
| 1246 | /* Direct jump method */ |
| 1247 | #if 1 |
| 1248 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
| 1249 | tcg_out_b(s, COND_AL, 8); |
| 1250 | #else |
| 1251 | tcg_out_ld32_12(s, COND_AL, 15, 15, -4); |
| 1252 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
| 1253 | tcg_out32(s, 0); |
| 1254 | #endif |
| 1255 | } else { |
| 1256 | /* Indirect jump method */ |
| 1257 | #if 1 |
| 1258 | c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8); |
| 1259 | if (c > 0xfff || c < -0xfff) { |
| 1260 | tcg_out_movi32(s, COND_AL, TCG_REG_R0, |
| 1261 | (tcg_target_long) (s->tb_next + args[0])); |
| 1262 | tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0); |
| 1263 | } else |
| 1264 | tcg_out_ld32_12(s, COND_AL, 15, 15, c); |
| 1265 | #else |
| 1266 | tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0); |
| 1267 | tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0); |
| 1268 | tcg_out32(s, (tcg_target_long) (s->tb_next + args[0])); |
| 1269 | #endif |
| 1270 | } |
| 1271 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; |
| 1272 | break; |
| 1273 | case INDEX_op_call: |
| 1274 | if (const_args[0]) |
| 1275 | tcg_out_call(s, COND_AL, args[0]); |
| 1276 | else |
| 1277 | tcg_out_callr(s, COND_AL, args[0]); |
| 1278 | break; |
| 1279 | case INDEX_op_jmp: |
| 1280 | if (const_args[0]) |
| 1281 | tcg_out_goto(s, COND_AL, args[0]); |
| 1282 | else |
| 1283 | tcg_out_bx(s, COND_AL, args[0]); |
| 1284 | break; |
| 1285 | case INDEX_op_br: |
| 1286 | tcg_out_goto_label(s, COND_AL, args[0]); |
| 1287 | break; |
| 1288 | |
| 1289 | case INDEX_op_ld8u_i32: |
| 1290 | tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]); |
| 1291 | break; |
| 1292 | case INDEX_op_ld8s_i32: |
| 1293 | tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]); |
| 1294 | break; |
| 1295 | case INDEX_op_ld16u_i32: |
| 1296 | tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]); |
| 1297 | break; |
| 1298 | case INDEX_op_ld16s_i32: |
| 1299 | tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]); |
| 1300 | break; |
| 1301 | case INDEX_op_ld_i32: |
| 1302 | tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]); |
| 1303 | break; |
| 1304 | case INDEX_op_st8_i32: |
| 1305 | tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]); |
| 1306 | break; |
| 1307 | case INDEX_op_st16_i32: |
| 1308 | tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]); |
| 1309 | break; |
| 1310 | case INDEX_op_st_i32: |
| 1311 | tcg_out_st32(s, COND_AL, args[0], args[1], args[2]); |
| 1312 | break; |
| 1313 | |
| 1314 | case INDEX_op_mov_i32: |
| 1315 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
| 1316 | args[0], 0, args[1], SHIFT_IMM_LSL(0)); |
| 1317 | break; |
| 1318 | case INDEX_op_movi_i32: |
| 1319 | tcg_out_movi32(s, COND_AL, args[0], args[1]); |
| 1320 | break; |
| 1321 | case INDEX_op_add_i32: |
| 1322 | c = ARITH_ADD; |
| 1323 | goto gen_arith; |
| 1324 | case INDEX_op_sub_i32: |
| 1325 | c = ARITH_SUB; |
| 1326 | goto gen_arith; |
| 1327 | case INDEX_op_and_i32: |
| 1328 | c = ARITH_AND; |
| 1329 | goto gen_arith; |
| 1330 | case INDEX_op_or_i32: |
| 1331 | c = ARITH_ORR; |
| 1332 | goto gen_arith; |
| 1333 | case INDEX_op_xor_i32: |
| 1334 | c = ARITH_EOR; |
| 1335 | /* Fall through. */ |
| 1336 | gen_arith: |
| 1337 | tcg_out_dat_reg(s, COND_AL, c, |
| 1338 | args[0], args[1], args[2], SHIFT_IMM_LSL(0)); |
| 1339 | break; |
| 1340 | case INDEX_op_add2_i32: |
| 1341 | tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC, |
| 1342 | args[0], args[1], args[2], args[3], |
| 1343 | args[4], args[5], SHIFT_IMM_LSL(0)); |
| 1344 | break; |
| 1345 | case INDEX_op_sub2_i32: |
| 1346 | tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC, |
| 1347 | args[0], args[1], args[2], args[3], |
| 1348 | args[4], args[5], SHIFT_IMM_LSL(0)); |
| 1349 | break; |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 1350 | case INDEX_op_neg_i32: |
| 1351 | tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0); |
| 1352 | break; |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1353 | case INDEX_op_mul_i32: |
| 1354 | tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]); |
| 1355 | break; |
| 1356 | case INDEX_op_mulu2_i32: |
| 1357 | tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]); |
| 1358 | break; |
| 1359 | case INDEX_op_div2_i32: |
| 1360 | tcg_out_div_helper(s, COND_AL, args, |
| 1361 | tcg_helper_div_i64, tcg_helper_rem_i64, |
| 1362 | SHIFT_IMM_ASR(31)); |
| 1363 | break; |
| 1364 | case INDEX_op_divu2_i32: |
| 1365 | tcg_out_div_helper(s, COND_AL, args, |
| 1366 | tcg_helper_divu_i64, tcg_helper_remu_i64, |
| 1367 | SHIFT_IMM_LSR(31)); |
| 1368 | break; |
| 1369 | /* XXX: Perhaps args[2] & 0x1f is wrong */ |
| 1370 | case INDEX_op_shl_i32: |
| 1371 | c = const_args[2] ? |
| 1372 | SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]); |
| 1373 | goto gen_shift32; |
| 1374 | case INDEX_op_shr_i32: |
| 1375 | c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) : |
| 1376 | SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]); |
| 1377 | goto gen_shift32; |
| 1378 | case INDEX_op_sar_i32: |
| 1379 | c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) : |
| 1380 | SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]); |
| 1381 | /* Fall through. */ |
| 1382 | gen_shift32: |
| 1383 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c); |
| 1384 | break; |
| 1385 | |
| 1386 | case INDEX_op_brcond_i32: |
| 1387 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, |
| 1388 | args[0], args[1], SHIFT_IMM_LSL(0)); |
| 1389 | tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]); |
| 1390 | break; |
| 1391 | case INDEX_op_brcond2_i32: |
| 1392 | /* The resulting conditions are: |
| 1393 | * TCG_COND_EQ --> a0 == a2 && a1 == a3, |
| 1394 | * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3, |
| 1395 | * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3, |
| 1396 | * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3), |
| 1397 | * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), |
| 1398 | * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, |
| 1399 | */ |
| 1400 | tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, |
| 1401 | args[1], args[3], SHIFT_IMM_LSL(0)); |
| 1402 | tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, |
| 1403 | args[0], args[2], SHIFT_IMM_LSL(0)); |
| 1404 | tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]); |
| 1405 | break; |
| 1406 | |
| 1407 | case INDEX_op_qemu_ld8u: |
| 1408 | tcg_out_qemu_ld(s, COND_AL, args, 0); |
| 1409 | break; |
| 1410 | case INDEX_op_qemu_ld8s: |
| 1411 | tcg_out_qemu_ld(s, COND_AL, args, 0 | 4); |
| 1412 | break; |
| 1413 | case INDEX_op_qemu_ld16u: |
| 1414 | tcg_out_qemu_ld(s, COND_AL, args, 1); |
| 1415 | break; |
| 1416 | case INDEX_op_qemu_ld16s: |
| 1417 | tcg_out_qemu_ld(s, COND_AL, args, 1 | 4); |
| 1418 | break; |
| 1419 | case INDEX_op_qemu_ld32u: |
| 1420 | tcg_out_qemu_ld(s, COND_AL, args, 2); |
| 1421 | break; |
| 1422 | case INDEX_op_qemu_ld64: |
| 1423 | tcg_out_qemu_ld(s, COND_AL, args, 3); |
| 1424 | break; |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 1425 | |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1426 | case INDEX_op_qemu_st8: |
| 1427 | tcg_out_qemu_st(s, COND_AL, args, 0); |
| 1428 | break; |
| 1429 | case INDEX_op_qemu_st16: |
| 1430 | tcg_out_qemu_st(s, COND_AL, args, 1); |
| 1431 | break; |
| 1432 | case INDEX_op_qemu_st32: |
| 1433 | tcg_out_qemu_st(s, COND_AL, args, 2); |
| 1434 | break; |
| 1435 | case INDEX_op_qemu_st64: |
| 1436 | tcg_out_qemu_st(s, COND_AL, args, 3); |
| 1437 | break; |
| 1438 | |
| 1439 | case INDEX_op_ext8s_i32: |
| 1440 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
| 1441 | args[0], 0, args[1], SHIFT_IMM_LSL(24)); |
| 1442 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
| 1443 | args[0], 0, args[0], SHIFT_IMM_ASR(24)); |
| 1444 | break; |
| 1445 | case INDEX_op_ext16s_i32: |
| 1446 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
| 1447 | args[0], 0, args[1], SHIFT_IMM_LSL(16)); |
| 1448 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, |
| 1449 | args[0], 0, args[0], SHIFT_IMM_ASR(16)); |
| 1450 | break; |
| 1451 | |
| 1452 | default: |
| 1453 | tcg_abort(); |
| 1454 | } |
| 1455 | } |
| 1456 | |
| 1457 | static const TCGTargetOpDef arm_op_defs[] = { |
| 1458 | { INDEX_op_exit_tb, { } }, |
| 1459 | { INDEX_op_goto_tb, { } }, |
| 1460 | { INDEX_op_call, { "ri" } }, |
| 1461 | { INDEX_op_jmp, { "ri" } }, |
| 1462 | { INDEX_op_br, { } }, |
| 1463 | |
| 1464 | { INDEX_op_mov_i32, { "r", "r" } }, |
| 1465 | { INDEX_op_movi_i32, { "r" } }, |
| 1466 | |
| 1467 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
| 1468 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
| 1469 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
| 1470 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
| 1471 | { INDEX_op_ld_i32, { "r", "r" } }, |
| 1472 | { INDEX_op_st8_i32, { "r", "r" } }, |
| 1473 | { INDEX_op_st16_i32, { "r", "r" } }, |
| 1474 | { INDEX_op_st_i32, { "r", "r" } }, |
| 1475 | |
| 1476 | /* TODO: "r", "r", "ri" */ |
| 1477 | { INDEX_op_add_i32, { "r", "r", "r" } }, |
| 1478 | { INDEX_op_sub_i32, { "r", "r", "r" } }, |
| 1479 | { INDEX_op_mul_i32, { "r", "r", "r" } }, |
| 1480 | { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, |
| 1481 | { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } }, |
| 1482 | { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } }, |
| 1483 | { INDEX_op_and_i32, { "r", "r", "r" } }, |
| 1484 | { INDEX_op_or_i32, { "r", "r", "r" } }, |
| 1485 | { INDEX_op_xor_i32, { "r", "r", "r" } }, |
balrog | 650bbb3 | 2008-05-20 11:26:40 +0000 | [diff] [blame] | 1486 | { INDEX_op_neg_i32, { "r", "r" } }, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1487 | |
| 1488 | { INDEX_op_shl_i32, { "r", "r", "ri" } }, |
| 1489 | { INDEX_op_shr_i32, { "r", "r", "ri" } }, |
| 1490 | { INDEX_op_sar_i32, { "r", "r", "ri" } }, |
| 1491 | |
| 1492 | { INDEX_op_brcond_i32, { "r", "r" } }, |
| 1493 | |
| 1494 | /* TODO: "r", "r", "r", "r", "ri", "ri" */ |
| 1495 | { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } }, |
| 1496 | { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } }, |
| 1497 | { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } }, |
| 1498 | |
| 1499 | { INDEX_op_qemu_ld8u, { "r", "x", "X" } }, |
| 1500 | { INDEX_op_qemu_ld8s, { "r", "x", "X" } }, |
| 1501 | { INDEX_op_qemu_ld16u, { "r", "x", "X" } }, |
| 1502 | { INDEX_op_qemu_ld16s, { "r", "x", "X" } }, |
| 1503 | { INDEX_op_qemu_ld32u, { "r", "x", "X" } }, |
balrog | d0660ed | 2008-05-24 23:12:19 +0000 | [diff] [blame] | 1504 | { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } }, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1505 | |
pbrook | 3979144 | 2008-05-24 20:07:07 +0000 | [diff] [blame] | 1506 | { INDEX_op_qemu_st8, { "x", "x", "X" } }, |
| 1507 | { INDEX_op_qemu_st16, { "x", "x", "X" } }, |
| 1508 | { INDEX_op_qemu_st32, { "x", "x", "X" } }, |
| 1509 | { INDEX_op_qemu_st64, { "x", "D", "x", "X" } }, |
balrog | 811d4cf | 2008-05-19 23:59:38 +0000 | [diff] [blame] | 1510 | |
| 1511 | { INDEX_op_ext8s_i32, { "r", "r" } }, |
| 1512 | { INDEX_op_ext16s_i32, { "r", "r" } }, |
| 1513 | |
| 1514 | { -1 }, |
| 1515 | }; |
| 1516 | |
| 1517 | void tcg_target_init(TCGContext *s) |
| 1518 | { |
| 1519 | /* fail safe */ |
| 1520 | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
| 1521 | tcg_abort(); |
| 1522 | |
| 1523 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, |
| 1524 | ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8)); |
| 1525 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
| 1526 | ((2 << TCG_REG_R3) - 1) | |
| 1527 | (1 << TCG_REG_R12) | (1 << TCG_REG_R14)); |
| 1528 | |
| 1529 | tcg_regset_clear(s->reserved_regs); |
| 1530 | #ifdef SAVE_LR |
| 1531 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14); |
| 1532 | #endif |
| 1533 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); |
| 1534 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8); |
| 1535 | |
| 1536 | tcg_add_target_add_op_defs(arm_op_defs); |
| 1537 | } |
| 1538 | |
| 1539 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg, |
| 1540 | int arg1, tcg_target_long arg2) |
| 1541 | { |
| 1542 | tcg_out_ld32u(s, COND_AL, arg, arg1, arg2); |
| 1543 | } |
| 1544 | |
| 1545 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
| 1546 | int arg1, tcg_target_long arg2) |
| 1547 | { |
| 1548 | tcg_out_st32(s, COND_AL, arg, arg1, arg2); |
| 1549 | } |
| 1550 | |
| 1551 | void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
| 1552 | { |
| 1553 | if (val > 0) |
| 1554 | if (val < 0x100) |
| 1555 | tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val); |
| 1556 | else |
| 1557 | tcg_abort(); |
| 1558 | else if (val < 0) { |
| 1559 | if (val > -0x100) |
| 1560 | tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val); |
| 1561 | else |
| 1562 | tcg_abort(); |
| 1563 | } |
| 1564 | } |
| 1565 | |
| 1566 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
| 1567 | { |
| 1568 | tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0)); |
| 1569 | } |
| 1570 | |
| 1571 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
| 1572 | int ret, tcg_target_long arg) |
| 1573 | { |
| 1574 | tcg_out_movi32(s, COND_AL, ret, arg); |
| 1575 | } |
| 1576 | |
| 1577 | void tcg_target_qemu_prologue(TCGContext *s) |
| 1578 | { |
| 1579 | /* stmdb sp!, { r9 - r11, lr } */ |
| 1580 | tcg_out32(s, (COND_AL << 28) | 0x092d4e00); |
| 1581 | |
| 1582 | tcg_out_bx(s, COND_AL, TCG_REG_R0); |
| 1583 | tb_ret_addr = s->code_ptr; |
| 1584 | |
| 1585 | /* ldmia sp!, { r9 - r11, pc } */ |
| 1586 | tcg_out32(s, (COND_AL << 28) | 0x08bd8e00); |
| 1587 | } |