Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU model of the Milkymist System Controller. |
| 3 | * |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 4 | * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc> |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | * |
| 20 | * Specification available at: |
| 21 | * http://www.milkymist.org/socdoc/sysctl.pdf |
| 22 | */ |
| 23 | |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 24 | #include "hw/hw.h" |
| 25 | #include "hw/sysbus.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 26 | #include "sysemu/sysemu.h" |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 27 | #include "trace.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 28 | #include "qemu/timer.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 29 | #include "hw/ptimer.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 30 | #include "qemu/error-report.h" |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 31 | |
| 32 | enum { |
| 33 | CTRL_ENABLE = (1<<0), |
| 34 | CTRL_AUTORESTART = (1<<1), |
| 35 | }; |
| 36 | |
| 37 | enum { |
| 38 | ICAP_READY = (1<<0), |
| 39 | }; |
| 40 | |
| 41 | enum { |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 42 | R_GPIO_IN = 0, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 43 | R_GPIO_OUT, |
| 44 | R_GPIO_INTEN, |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 45 | R_TIMER0_CONTROL = 4, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 46 | R_TIMER0_COMPARE, |
| 47 | R_TIMER0_COUNTER, |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 48 | R_TIMER1_CONTROL = 8, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 49 | R_TIMER1_COMPARE, |
| 50 | R_TIMER1_COUNTER, |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 51 | R_ICAP = 16, |
| 52 | R_DBG_SCRATCHPAD = 20, |
| 53 | R_DBG_WRITE_LOCK, |
| 54 | R_CLK_FREQUENCY = 29, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 55 | R_CAPABILITIES, |
| 56 | R_SYSTEM_ID, |
| 57 | R_MAX |
| 58 | }; |
| 59 | |
Andreas Färber | b564b13 | 2013-07-27 15:06:42 +0200 | [diff] [blame] | 60 | #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl" |
| 61 | #define MILKYMIST_SYSCTL(obj) \ |
| 62 | OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL) |
| 63 | |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 64 | struct MilkymistSysctlState { |
Andreas Färber | b564b13 | 2013-07-27 15:06:42 +0200 | [diff] [blame] | 65 | SysBusDevice parent_obj; |
| 66 | |
Michael Walle | dfa87cc | 2011-08-31 16:48:43 +0200 | [diff] [blame] | 67 | MemoryRegion regs_region; |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 68 | |
| 69 | QEMUBH *bh0; |
| 70 | QEMUBH *bh1; |
| 71 | ptimer_state *ptimer0; |
| 72 | ptimer_state *ptimer1; |
| 73 | |
| 74 | uint32_t freq_hz; |
| 75 | uint32_t capabilities; |
| 76 | uint32_t systemid; |
| 77 | uint32_t strappings; |
| 78 | |
| 79 | uint32_t regs[R_MAX]; |
| 80 | |
| 81 | qemu_irq gpio_irq; |
| 82 | qemu_irq timer0_irq; |
| 83 | qemu_irq timer1_irq; |
| 84 | }; |
| 85 | typedef struct MilkymistSysctlState MilkymistSysctlState; |
| 86 | |
| 87 | static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value) |
| 88 | { |
| 89 | trace_milkymist_sysctl_icap_write(value); |
| 90 | switch (value & 0xffff) { |
| 91 | case 0x000e: |
| 92 | qemu_system_shutdown_request(); |
| 93 | break; |
| 94 | } |
| 95 | } |
| 96 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 97 | static uint64_t sysctl_read(void *opaque, hwaddr addr, |
Michael Walle | dfa87cc | 2011-08-31 16:48:43 +0200 | [diff] [blame] | 98 | unsigned size) |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 99 | { |
| 100 | MilkymistSysctlState *s = opaque; |
| 101 | uint32_t r = 0; |
| 102 | |
| 103 | addr >>= 2; |
| 104 | switch (addr) { |
| 105 | case R_TIMER0_COUNTER: |
| 106 | r = (uint32_t)ptimer_get_count(s->ptimer0); |
| 107 | /* milkymist timer counts up */ |
| 108 | r = s->regs[R_TIMER0_COMPARE] - r; |
| 109 | break; |
| 110 | case R_TIMER1_COUNTER: |
| 111 | r = (uint32_t)ptimer_get_count(s->ptimer1); |
| 112 | /* milkymist timer counts up */ |
| 113 | r = s->regs[R_TIMER1_COMPARE] - r; |
| 114 | break; |
| 115 | case R_GPIO_IN: |
| 116 | case R_GPIO_OUT: |
| 117 | case R_GPIO_INTEN: |
| 118 | case R_TIMER0_CONTROL: |
| 119 | case R_TIMER0_COMPARE: |
| 120 | case R_TIMER1_CONTROL: |
| 121 | case R_TIMER1_COMPARE: |
| 122 | case R_ICAP: |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 123 | case R_DBG_SCRATCHPAD: |
| 124 | case R_DBG_WRITE_LOCK: |
| 125 | case R_CLK_FREQUENCY: |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 126 | case R_CAPABILITIES: |
| 127 | case R_SYSTEM_ID: |
| 128 | r = s->regs[addr]; |
| 129 | break; |
| 130 | |
| 131 | default: |
Markus Armbruster | dd3d677 | 2011-06-22 14:03:56 +0200 | [diff] [blame] | 132 | error_report("milkymist_sysctl: read access to unknown register 0x" |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 133 | TARGET_FMT_plx, addr << 2); |
| 134 | break; |
| 135 | } |
| 136 | |
| 137 | trace_milkymist_sysctl_memory_read(addr << 2, r); |
| 138 | |
| 139 | return r; |
| 140 | } |
| 141 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 142 | static void sysctl_write(void *opaque, hwaddr addr, uint64_t value, |
Michael Walle | dfa87cc | 2011-08-31 16:48:43 +0200 | [diff] [blame] | 143 | unsigned size) |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 144 | { |
| 145 | MilkymistSysctlState *s = opaque; |
| 146 | |
| 147 | trace_milkymist_sysctl_memory_write(addr, value); |
| 148 | |
| 149 | addr >>= 2; |
| 150 | switch (addr) { |
| 151 | case R_GPIO_OUT: |
| 152 | case R_GPIO_INTEN: |
| 153 | case R_TIMER0_COUNTER: |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 154 | case R_TIMER1_COUNTER: |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 155 | case R_DBG_SCRATCHPAD: |
Michael Walle | f3172a0 | 2011-04-13 00:29:35 +0200 | [diff] [blame] | 156 | s->regs[addr] = value; |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 157 | break; |
| 158 | case R_TIMER0_COMPARE: |
| 159 | ptimer_set_limit(s->ptimer0, value, 0); |
| 160 | s->regs[addr] = value; |
| 161 | break; |
| 162 | case R_TIMER1_COMPARE: |
| 163 | ptimer_set_limit(s->ptimer1, value, 0); |
| 164 | s->regs[addr] = value; |
| 165 | break; |
| 166 | case R_TIMER0_CONTROL: |
| 167 | s->regs[addr] = value; |
| 168 | if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) { |
Michael Walle | f3172a0 | 2011-04-13 00:29:35 +0200 | [diff] [blame] | 169 | trace_milkymist_sysctl_start_timer0(); |
| 170 | ptimer_set_count(s->ptimer0, |
| 171 | s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 172 | ptimer_run(s->ptimer0, 0); |
| 173 | } else { |
Michael Walle | f3172a0 | 2011-04-13 00:29:35 +0200 | [diff] [blame] | 174 | trace_milkymist_sysctl_stop_timer0(); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 175 | ptimer_stop(s->ptimer0); |
| 176 | } |
| 177 | break; |
| 178 | case R_TIMER1_CONTROL: |
| 179 | s->regs[addr] = value; |
| 180 | if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) { |
| 181 | trace_milkymist_sysctl_start_timer1(); |
Michael Walle | f3172a0 | 2011-04-13 00:29:35 +0200 | [diff] [blame] | 182 | ptimer_set_count(s->ptimer1, |
| 183 | s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 184 | ptimer_run(s->ptimer1, 0); |
| 185 | } else { |
| 186 | trace_milkymist_sysctl_stop_timer1(); |
| 187 | ptimer_stop(s->ptimer1); |
| 188 | } |
| 189 | break; |
| 190 | case R_ICAP: |
| 191 | sysctl_icap_write(s, value); |
| 192 | break; |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 193 | case R_DBG_WRITE_LOCK: |
| 194 | s->regs[addr] = 1; |
| 195 | break; |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 196 | case R_SYSTEM_ID: |
| 197 | qemu_system_reset_request(); |
| 198 | break; |
| 199 | |
| 200 | case R_GPIO_IN: |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 201 | case R_CLK_FREQUENCY: |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 202 | case R_CAPABILITIES: |
| 203 | error_report("milkymist_sysctl: write to read-only register 0x" |
| 204 | TARGET_FMT_plx, addr << 2); |
| 205 | break; |
| 206 | |
| 207 | default: |
Markus Armbruster | dd3d677 | 2011-06-22 14:03:56 +0200 | [diff] [blame] | 208 | error_report("milkymist_sysctl: write access to unknown register 0x" |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 209 | TARGET_FMT_plx, addr << 2); |
| 210 | break; |
| 211 | } |
| 212 | } |
| 213 | |
Michael Walle | dfa87cc | 2011-08-31 16:48:43 +0200 | [diff] [blame] | 214 | static const MemoryRegionOps sysctl_mmio_ops = { |
| 215 | .read = sysctl_read, |
| 216 | .write = sysctl_write, |
| 217 | .valid = { |
| 218 | .min_access_size = 4, |
| 219 | .max_access_size = 4, |
| 220 | }, |
| 221 | .endianness = DEVICE_NATIVE_ENDIAN, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | static void timer0_hit(void *opaque) |
| 225 | { |
| 226 | MilkymistSysctlState *s = opaque; |
| 227 | |
| 228 | if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) { |
| 229 | s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE; |
| 230 | trace_milkymist_sysctl_stop_timer0(); |
| 231 | ptimer_stop(s->ptimer0); |
| 232 | } |
| 233 | |
| 234 | trace_milkymist_sysctl_pulse_irq_timer0(); |
| 235 | qemu_irq_pulse(s->timer0_irq); |
| 236 | } |
| 237 | |
| 238 | static void timer1_hit(void *opaque) |
| 239 | { |
| 240 | MilkymistSysctlState *s = opaque; |
| 241 | |
| 242 | if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) { |
| 243 | s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE; |
| 244 | trace_milkymist_sysctl_stop_timer1(); |
| 245 | ptimer_stop(s->ptimer1); |
| 246 | } |
| 247 | |
| 248 | trace_milkymist_sysctl_pulse_irq_timer1(); |
| 249 | qemu_irq_pulse(s->timer1_irq); |
| 250 | } |
| 251 | |
| 252 | static void milkymist_sysctl_reset(DeviceState *d) |
| 253 | { |
Andreas Färber | b564b13 | 2013-07-27 15:06:42 +0200 | [diff] [blame] | 254 | MilkymistSysctlState *s = MILKYMIST_SYSCTL(d); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 255 | int i; |
| 256 | |
| 257 | for (i = 0; i < R_MAX; i++) { |
| 258 | s->regs[i] = 0; |
| 259 | } |
| 260 | |
| 261 | ptimer_stop(s->ptimer0); |
| 262 | ptimer_stop(s->ptimer1); |
| 263 | |
| 264 | /* defaults */ |
| 265 | s->regs[R_ICAP] = ICAP_READY; |
| 266 | s->regs[R_SYSTEM_ID] = s->systemid; |
Michael Walle | 060544d | 2012-03-31 19:54:09 +0200 | [diff] [blame] | 267 | s->regs[R_CLK_FREQUENCY] = s->freq_hz; |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 268 | s->regs[R_CAPABILITIES] = s->capabilities; |
| 269 | s->regs[R_GPIO_IN] = s->strappings; |
| 270 | } |
| 271 | |
| 272 | static int milkymist_sysctl_init(SysBusDevice *dev) |
| 273 | { |
Andreas Färber | b564b13 | 2013-07-27 15:06:42 +0200 | [diff] [blame] | 274 | MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 275 | |
| 276 | sysbus_init_irq(dev, &s->gpio_irq); |
| 277 | sysbus_init_irq(dev, &s->timer0_irq); |
| 278 | sysbus_init_irq(dev, &s->timer1_irq); |
| 279 | |
| 280 | s->bh0 = qemu_bh_new(timer0_hit, s); |
| 281 | s->bh1 = qemu_bh_new(timer1_hit, s); |
| 282 | s->ptimer0 = ptimer_init(s->bh0); |
| 283 | s->ptimer1 = ptimer_init(s->bh1); |
| 284 | ptimer_set_freq(s->ptimer0, s->freq_hz); |
| 285 | ptimer_set_freq(s->ptimer1, s->freq_hz); |
| 286 | |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 287 | memory_region_init_io(&s->regs_region, OBJECT(s), &sysctl_mmio_ops, s, |
Michael Walle | dfa87cc | 2011-08-31 16:48:43 +0200 | [diff] [blame] | 288 | "milkymist-sysctl", R_MAX * 4); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 289 | sysbus_init_mmio(dev, &s->regs_region); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | static const VMStateDescription vmstate_milkymist_sysctl = { |
| 295 | .name = "milkymist-sysctl", |
| 296 | .version_id = 1, |
| 297 | .minimum_version_id = 1, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 298 | .fields = (VMStateField[]) { |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 299 | VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX), |
| 300 | VMSTATE_PTIMER(ptimer0, MilkymistSysctlState), |
| 301 | VMSTATE_PTIMER(ptimer1, MilkymistSysctlState), |
| 302 | VMSTATE_END_OF_LIST() |
| 303 | } |
| 304 | }; |
| 305 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 306 | static Property milkymist_sysctl_properties[] = { |
| 307 | DEFINE_PROP_UINT32("frequency", MilkymistSysctlState, |
| 308 | freq_hz, 80000000), |
| 309 | DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState, |
| 310 | capabilities, 0x00000000), |
| 311 | DEFINE_PROP_UINT32("systemid", MilkymistSysctlState, |
| 312 | systemid, 0x10014d31), |
| 313 | DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState, |
| 314 | strappings, 0x00000001), |
| 315 | DEFINE_PROP_END_OF_LIST(), |
| 316 | }; |
| 317 | |
| 318 | static void milkymist_sysctl_class_init(ObjectClass *klass, void *data) |
| 319 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 320 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 321 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 322 | |
| 323 | k->init = milkymist_sysctl_init; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 324 | dc->reset = milkymist_sysctl_reset; |
| 325 | dc->vmsd = &vmstate_milkymist_sysctl; |
| 326 | dc->props = milkymist_sysctl_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 327 | } |
| 328 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 329 | static const TypeInfo milkymist_sysctl_info = { |
Andreas Färber | b564b13 | 2013-07-27 15:06:42 +0200 | [diff] [blame] | 330 | .name = TYPE_MILKYMIST_SYSCTL, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 331 | .parent = TYPE_SYS_BUS_DEVICE, |
| 332 | .instance_size = sizeof(MilkymistSysctlState), |
| 333 | .class_init = milkymist_sysctl_class_init, |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 334 | }; |
| 335 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 336 | static void milkymist_sysctl_register_types(void) |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 337 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 338 | type_register_static(&milkymist_sysctl_info); |
Michael Walle | 9683242 | 2011-03-07 23:32:38 +0100 | [diff] [blame] | 339 | } |
| 340 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 341 | type_init(milkymist_sysctl_register_types) |