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Michael Walleea7924d2011-02-17 23:45:10 +01001/*
2 * QEMU model of the LatticeMico32 timer block.
3 *
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32timer.pdf
22 */
23
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010024#include "hw/hw.h"
25#include "hw/sysbus.h"
Michael Walleea7924d2011-02-17 23:45:10 +010026#include "trace.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010027#include "qemu/timer.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010028#include "hw/ptimer.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010029#include "qemu/error-report.h"
Alex Bligh6a1751b2013-08-21 16:02:47 +010030#include "qemu/main-loop.h"
Michael Walleea7924d2011-02-17 23:45:10 +010031
32#define DEFAULT_FREQUENCY (50*1000000)
33
34enum {
35 R_SR = 0,
36 R_CR,
37 R_PERIOD,
38 R_SNAPSHOT,
39 R_MAX
40};
41
42enum {
43 SR_TO = (1 << 0),
44 SR_RUN = (1 << 1),
45};
46
47enum {
48 CR_ITO = (1 << 0),
49 CR_CONT = (1 << 1),
50 CR_START = (1 << 2),
51 CR_STOP = (1 << 3),
52};
53
Andreas Färberfe54d852013-07-27 14:54:54 +020054#define TYPE_LM32_TIMER "lm32-timer"
55#define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
56
Michael Walleea7924d2011-02-17 23:45:10 +010057struct LM32TimerState {
Andreas Färberfe54d852013-07-27 14:54:54 +020058 SysBusDevice parent_obj;
59
Avi Kivityd09510b2011-11-20 11:44:25 +020060 MemoryRegion iomem;
Michael Walleea7924d2011-02-17 23:45:10 +010061
62 QEMUBH *bh;
63 ptimer_state *ptimer;
64
65 qemu_irq irq;
66 uint32_t freq_hz;
67
68 uint32_t regs[R_MAX];
69};
70typedef struct LM32TimerState LM32TimerState;
71
72static void timer_update_irq(LM32TimerState *s)
73{
74 int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
75
76 trace_lm32_timer_irq_state(state);
77 qemu_set_irq(s->irq, state);
78}
79
Avi Kivitya8170e52012-10-23 12:30:10 +020080static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
Michael Walleea7924d2011-02-17 23:45:10 +010081{
82 LM32TimerState *s = opaque;
83 uint32_t r = 0;
84
85 addr >>= 2;
86 switch (addr) {
87 case R_SR:
88 case R_CR:
89 case R_PERIOD:
90 r = s->regs[addr];
91 break;
92 case R_SNAPSHOT:
93 r = (uint32_t)ptimer_get_count(s->ptimer);
94 break;
95 default:
Markus Armbrusterdd3d6772011-06-22 14:03:56 +020096 error_report("lm32_timer: read access to unknown register 0x"
Michael Walleea7924d2011-02-17 23:45:10 +010097 TARGET_FMT_plx, addr << 2);
98 break;
99 }
100
101 trace_lm32_timer_memory_read(addr << 2, r);
102 return r;
103}
104
Avi Kivitya8170e52012-10-23 12:30:10 +0200105static void timer_write(void *opaque, hwaddr addr,
Avi Kivityd09510b2011-11-20 11:44:25 +0200106 uint64_t value, unsigned size)
Michael Walleea7924d2011-02-17 23:45:10 +0100107{
108 LM32TimerState *s = opaque;
109
110 trace_lm32_timer_memory_write(addr, value);
111
112 addr >>= 2;
113 switch (addr) {
114 case R_SR:
115 s->regs[R_SR] &= ~SR_TO;
116 break;
117 case R_CR:
118 s->regs[R_CR] = value;
119 if (s->regs[R_CR] & CR_START) {
120 ptimer_run(s->ptimer, 1);
121 }
122 if (s->regs[R_CR] & CR_STOP) {
123 ptimer_stop(s->ptimer);
124 }
125 break;
126 case R_PERIOD:
127 s->regs[R_PERIOD] = value;
128 ptimer_set_count(s->ptimer, value);
129 break;
130 case R_SNAPSHOT:
131 error_report("lm32_timer: write access to read only register 0x"
132 TARGET_FMT_plx, addr << 2);
133 break;
134 default:
Markus Armbrusterdd3d6772011-06-22 14:03:56 +0200135 error_report("lm32_timer: write access to unknown register 0x"
Michael Walleea7924d2011-02-17 23:45:10 +0100136 TARGET_FMT_plx, addr << 2);
137 break;
138 }
139 timer_update_irq(s);
140}
141
Avi Kivityd09510b2011-11-20 11:44:25 +0200142static const MemoryRegionOps timer_ops = {
143 .read = timer_read,
144 .write = timer_write,
145 .endianness = DEVICE_NATIVE_ENDIAN,
146 .valid = {
147 .min_access_size = 4,
148 .max_access_size = 4,
149 },
Michael Walleea7924d2011-02-17 23:45:10 +0100150};
151
152static void timer_hit(void *opaque)
153{
154 LM32TimerState *s = opaque;
155
156 trace_lm32_timer_hit();
157
158 s->regs[R_SR] |= SR_TO;
159
160 if (s->regs[R_CR] & CR_CONT) {
161 ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
162 ptimer_run(s->ptimer, 1);
163 }
164 timer_update_irq(s);
165}
166
167static void timer_reset(DeviceState *d)
168{
Andreas Färberfe54d852013-07-27 14:54:54 +0200169 LM32TimerState *s = LM32_TIMER(d);
Michael Walleea7924d2011-02-17 23:45:10 +0100170 int i;
171
172 for (i = 0; i < R_MAX; i++) {
173 s->regs[i] = 0;
174 }
175 ptimer_stop(s->ptimer);
176}
177
178static int lm32_timer_init(SysBusDevice *dev)
179{
Andreas Färberfe54d852013-07-27 14:54:54 +0200180 LM32TimerState *s = LM32_TIMER(dev);
Michael Walleea7924d2011-02-17 23:45:10 +0100181
182 sysbus_init_irq(dev, &s->irq);
183
184 s->bh = qemu_bh_new(timer_hit, s);
185 s->ptimer = ptimer_init(s->bh);
186 ptimer_set_freq(s->ptimer, s->freq_hz);
187
Paolo Bonzini853dca12013-06-06 21:25:08 -0400188 memory_region_init_io(&s->iomem, OBJECT(s), &timer_ops, s,
189 "timer", R_MAX * 4);
Avi Kivity750ecd42011-11-27 11:38:10 +0200190 sysbus_init_mmio(dev, &s->iomem);
Michael Walleea7924d2011-02-17 23:45:10 +0100191
192 return 0;
193}
194
195static const VMStateDescription vmstate_lm32_timer = {
196 .name = "lm32-timer",
197 .version_id = 1,
198 .minimum_version_id = 1,
Juan Quintela35d08452014-04-16 16:01:33 +0200199 .fields = (VMStateField[]) {
Michael Walleea7924d2011-02-17 23:45:10 +0100200 VMSTATE_PTIMER(ptimer, LM32TimerState),
201 VMSTATE_UINT32(freq_hz, LM32TimerState),
202 VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
203 VMSTATE_END_OF_LIST()
204 }
205};
206
Anthony Liguori999e12b2012-01-24 13:12:29 -0600207static Property lm32_timer_properties[] = {
208 DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
209 DEFINE_PROP_END_OF_LIST(),
210};
211
212static void lm32_timer_class_init(ObjectClass *klass, void *data)
213{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600214 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600215 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
216
217 k->init = lm32_timer_init;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600218 dc->reset = timer_reset;
219 dc->vmsd = &vmstate_lm32_timer;
220 dc->props = lm32_timer_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600221}
222
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100223static const TypeInfo lm32_timer_info = {
Andreas Färberfe54d852013-07-27 14:54:54 +0200224 .name = TYPE_LM32_TIMER,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600225 .parent = TYPE_SYS_BUS_DEVICE,
226 .instance_size = sizeof(LM32TimerState),
227 .class_init = lm32_timer_class_init,
Michael Walleea7924d2011-02-17 23:45:10 +0100228};
229
Andreas Färber83f7d432012-02-09 15:20:55 +0100230static void lm32_timer_register_types(void)
Michael Walleea7924d2011-02-17 23:45:10 +0100231{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600232 type_register_static(&lm32_timer_info);
Michael Walleea7924d2011-02-17 23:45:10 +0100233}
234
Andreas Färber83f7d432012-02-09 15:20:55 +0100235type_init(lm32_timer_register_types)