Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TriCore emulation for qemu: main CPU struct. |
| 3 | * |
| 4 | * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
Thomas Huth | 02754ac | 2019-01-23 15:08:55 +0100 | [diff] [blame] | 9 | * version 2.1 of the License, or (at your option) any later version. |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
Markus Armbruster | 07f5a25 | 2016-06-29 11:05:55 +0200 | [diff] [blame] | 19 | |
| 20 | #ifndef TRICORE_CPU_H |
| 21 | #define TRICORE_CPU_H |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 22 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 23 | #include "qemu-common.h" |
Paolo Bonzini | fc111b1 | 2016-03-15 13:49:25 +0100 | [diff] [blame] | 24 | #include "cpu-qom.h" |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 25 | #include "exec/cpu-defs.h" |
Richard Henderson | 74433bf | 2019-03-22 11:51:19 -0700 | [diff] [blame^] | 26 | #include "tricore-defs.h" |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 27 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 28 | #define CPUArchState struct CPUTriCoreState |
| 29 | |
| 30 | struct CPUTriCoreState; |
| 31 | |
| 32 | struct tricore_boot_info; |
| 33 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 34 | typedef struct tricore_def_t tricore_def_t; |
| 35 | |
| 36 | typedef struct CPUTriCoreState CPUTriCoreState; |
| 37 | struct CPUTriCoreState { |
| 38 | /* GPR Register */ |
| 39 | uint32_t gpr_a[16]; |
| 40 | uint32_t gpr_d[16]; |
| 41 | /* CSFR Register */ |
| 42 | uint32_t PCXI; |
| 43 | /* Frequently accessed PSW_USB bits are stored separately for efficiency. |
| 44 | This contains all the other bits. Use psw_{read,write} to access |
| 45 | the whole PSW. */ |
| 46 | uint32_t PSW; |
| 47 | |
| 48 | /* PSW flag cache for faster execution |
| 49 | */ |
| 50 | uint32_t PSW_USB_C; |
| 51 | uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ |
| 52 | uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ |
| 53 | uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ |
| 54 | uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ |
| 55 | |
| 56 | uint32_t PC; |
| 57 | uint32_t SYSCON; |
| 58 | uint32_t CPU_ID; |
David Brenken | 04e6241 | 2018-03-01 16:56:17 +0100 | [diff] [blame] | 59 | uint32_t CORE_ID; |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 60 | uint32_t BIV; |
| 61 | uint32_t BTV; |
| 62 | uint32_t ISP; |
| 63 | uint32_t ICR; |
| 64 | uint32_t FCX; |
| 65 | uint32_t LCX; |
| 66 | uint32_t COMPAT; |
| 67 | |
| 68 | /* Mem Protection Register */ |
| 69 | uint32_t DPR0_0L; |
| 70 | uint32_t DPR0_0U; |
| 71 | uint32_t DPR0_1L; |
| 72 | uint32_t DPR0_1U; |
| 73 | uint32_t DPR0_2L; |
| 74 | uint32_t DPR0_2U; |
| 75 | uint32_t DPR0_3L; |
| 76 | uint32_t DPR0_3U; |
| 77 | |
| 78 | uint32_t DPR1_0L; |
| 79 | uint32_t DPR1_0U; |
| 80 | uint32_t DPR1_1L; |
| 81 | uint32_t DPR1_1U; |
| 82 | uint32_t DPR1_2L; |
| 83 | uint32_t DPR1_2U; |
| 84 | uint32_t DPR1_3L; |
| 85 | uint32_t DPR1_3U; |
| 86 | |
| 87 | uint32_t DPR2_0L; |
| 88 | uint32_t DPR2_0U; |
| 89 | uint32_t DPR2_1L; |
| 90 | uint32_t DPR2_1U; |
| 91 | uint32_t DPR2_2L; |
| 92 | uint32_t DPR2_2U; |
| 93 | uint32_t DPR2_3L; |
| 94 | uint32_t DPR2_3U; |
| 95 | |
| 96 | uint32_t DPR3_0L; |
| 97 | uint32_t DPR3_0U; |
| 98 | uint32_t DPR3_1L; |
| 99 | uint32_t DPR3_1U; |
| 100 | uint32_t DPR3_2L; |
| 101 | uint32_t DPR3_2U; |
| 102 | uint32_t DPR3_3L; |
| 103 | uint32_t DPR3_3U; |
| 104 | |
| 105 | uint32_t CPR0_0L; |
| 106 | uint32_t CPR0_0U; |
| 107 | uint32_t CPR0_1L; |
| 108 | uint32_t CPR0_1U; |
| 109 | uint32_t CPR0_2L; |
| 110 | uint32_t CPR0_2U; |
| 111 | uint32_t CPR0_3L; |
| 112 | uint32_t CPR0_3U; |
| 113 | |
| 114 | uint32_t CPR1_0L; |
| 115 | uint32_t CPR1_0U; |
| 116 | uint32_t CPR1_1L; |
| 117 | uint32_t CPR1_1U; |
| 118 | uint32_t CPR1_2L; |
| 119 | uint32_t CPR1_2U; |
| 120 | uint32_t CPR1_3L; |
| 121 | uint32_t CPR1_3U; |
| 122 | |
| 123 | uint32_t CPR2_0L; |
| 124 | uint32_t CPR2_0U; |
| 125 | uint32_t CPR2_1L; |
| 126 | uint32_t CPR2_1U; |
| 127 | uint32_t CPR2_2L; |
| 128 | uint32_t CPR2_2U; |
| 129 | uint32_t CPR2_3L; |
| 130 | uint32_t CPR2_3U; |
| 131 | |
| 132 | uint32_t CPR3_0L; |
| 133 | uint32_t CPR3_0U; |
| 134 | uint32_t CPR3_1L; |
| 135 | uint32_t CPR3_1U; |
| 136 | uint32_t CPR3_2L; |
| 137 | uint32_t CPR3_2U; |
| 138 | uint32_t CPR3_3L; |
| 139 | uint32_t CPR3_3U; |
| 140 | |
| 141 | uint32_t DPM0; |
| 142 | uint32_t DPM1; |
| 143 | uint32_t DPM2; |
| 144 | uint32_t DPM3; |
| 145 | |
| 146 | uint32_t CPM0; |
| 147 | uint32_t CPM1; |
| 148 | uint32_t CPM2; |
| 149 | uint32_t CPM3; |
| 150 | |
| 151 | /* Memory Management Registers */ |
| 152 | uint32_t MMU_CON; |
| 153 | uint32_t MMU_ASI; |
| 154 | uint32_t MMU_TVA; |
| 155 | uint32_t MMU_TPA; |
| 156 | uint32_t MMU_TPX; |
| 157 | uint32_t MMU_TFA; |
| 158 | /* {1.3.1 only */ |
| 159 | uint32_t BMACON; |
| 160 | uint32_t SMACON; |
| 161 | uint32_t DIEAR; |
| 162 | uint32_t DIETR; |
| 163 | uint32_t CCDIER; |
| 164 | uint32_t MIECON; |
| 165 | uint32_t PIEAR; |
| 166 | uint32_t PIETR; |
| 167 | uint32_t CCPIER; |
| 168 | /*} */ |
| 169 | /* Debug Registers */ |
| 170 | uint32_t DBGSR; |
| 171 | uint32_t EXEVT; |
| 172 | uint32_t CREVT; |
| 173 | uint32_t SWEVT; |
| 174 | uint32_t TR0EVT; |
| 175 | uint32_t TR1EVT; |
| 176 | uint32_t DMS; |
| 177 | uint32_t DCX; |
| 178 | uint32_t DBGTCR; |
| 179 | uint32_t CCTRL; |
| 180 | uint32_t CCNT; |
| 181 | uint32_t ICNT; |
| 182 | uint32_t M1CNT; |
| 183 | uint32_t M2CNT; |
| 184 | uint32_t M3CNT; |
| 185 | /* Floating Point Registers */ |
Bastian Koppelmann | 996a729 | 2016-03-11 16:03:11 +0100 | [diff] [blame] | 186 | float_status fp_status; |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 187 | /* QEMU */ |
| 188 | int error_code; |
| 189 | uint32_t hflags; /* CPU State */ |
| 190 | |
| 191 | CPU_COMMON |
| 192 | |
| 193 | /* Internal CPU feature flags. */ |
| 194 | uint64_t features; |
| 195 | |
| 196 | const tricore_def_t *cpu_model; |
| 197 | void *irq[8]; |
| 198 | struct QEMUTimer *timer; /* Internal timer */ |
| 199 | }; |
| 200 | |
Paolo Bonzini | fc111b1 | 2016-03-15 13:49:25 +0100 | [diff] [blame] | 201 | /** |
| 202 | * TriCoreCPU: |
| 203 | * @env: #CPUTriCoreState |
| 204 | * |
| 205 | * A TriCore CPU. |
| 206 | */ |
| 207 | struct TriCoreCPU { |
| 208 | /*< private >*/ |
| 209 | CPUState parent_obj; |
| 210 | /*< public >*/ |
| 211 | |
| 212 | CPUTriCoreState env; |
| 213 | }; |
| 214 | |
| 215 | static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env) |
| 216 | { |
| 217 | return TRICORE_CPU(container_of(env, TriCoreCPU, env)); |
| 218 | } |
| 219 | |
| 220 | #define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e)) |
| 221 | |
| 222 | #define ENV_OFFSET offsetof(TriCoreCPU, env) |
| 223 | |
| 224 | hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
Markus Armbruster | 90c84c5 | 2019-04-17 21:18:02 +0200 | [diff] [blame] | 225 | void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
Paolo Bonzini | fc111b1 | 2016-03-15 13:49:25 +0100 | [diff] [blame] | 226 | |
| 227 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 228 | #define MASK_PCXI_PCPN 0xff000000 |
David Brenken | ce46335 | 2018-03-01 16:56:19 +0100 | [diff] [blame] | 229 | #define MASK_PCXI_PIE_1_3 0x00800000 |
| 230 | #define MASK_PCXI_PIE_1_6 0x00200000 |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 231 | #define MASK_PCXI_UL 0x00400000 |
| 232 | #define MASK_PCXI_PCXS 0x000f0000 |
| 233 | #define MASK_PCXI_PCXO 0x0000ffff |
| 234 | |
| 235 | #define MASK_PSW_USB 0xff000000 |
| 236 | #define MASK_USB_C 0x80000000 |
| 237 | #define MASK_USB_V 0x40000000 |
| 238 | #define MASK_USB_SV 0x20000000 |
| 239 | #define MASK_USB_AV 0x10000000 |
| 240 | #define MASK_USB_SAV 0x08000000 |
| 241 | #define MASK_PSW_PRS 0x00003000 |
| 242 | #define MASK_PSW_IO 0x00000c00 |
| 243 | #define MASK_PSW_IS 0x00000200 |
| 244 | #define MASK_PSW_GW 0x00000100 |
| 245 | #define MASK_PSW_CDE 0x00000080 |
| 246 | #define MASK_PSW_CDC 0x0000007f |
Bastian Koppelmann | 996a729 | 2016-03-11 16:03:11 +0100 | [diff] [blame] | 247 | #define MASK_PSW_FPU_RM 0x3000000 |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 248 | |
| 249 | #define MASK_SYSCON_PRO_TEN 0x2 |
| 250 | #define MASK_SYSCON_FCD_SF 0x1 |
| 251 | |
| 252 | #define MASK_CPUID_MOD 0xffff0000 |
| 253 | #define MASK_CPUID_MOD_32B 0x0000ff00 |
| 254 | #define MASK_CPUID_REV 0x000000ff |
| 255 | |
| 256 | #define MASK_ICR_PIPN 0x00ff0000 |
David Brenken | d1cbc28 | 2018-03-01 16:56:18 +0100 | [diff] [blame] | 257 | #define MASK_ICR_IE_1_3 0x00000100 |
| 258 | #define MASK_ICR_IE_1_6 0x00008000 |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 259 | #define MASK_ICR_CCPN 0x000000ff |
| 260 | |
| 261 | #define MASK_FCX_FCXS 0x000f0000 |
| 262 | #define MASK_FCX_FCXO 0x0000ffff |
| 263 | |
| 264 | #define MASK_LCX_LCXS 0x000f0000 |
| 265 | #define MASK_LCX_LCX0 0x0000ffff |
| 266 | |
Bastian Koppelmann | b724b01 | 2015-02-25 12:29:24 +0000 | [diff] [blame] | 267 | #define MASK_DBGSR_DE 0x1 |
| 268 | #define MASK_DBGSR_HALT 0x6 |
| 269 | #define MASK_DBGSR_SUSP 0x10 |
| 270 | #define MASK_DBGSR_PREVSUSP 0x20 |
| 271 | #define MASK_DBGSR_PEVT 0x40 |
| 272 | #define MASK_DBGSR_EVTSRC 0x1f00 |
| 273 | |
Bastian Koppelmann | 40a1f64 | 2015-01-21 16:16:01 +0000 | [diff] [blame] | 274 | #define TRICORE_HFLAG_KUU 0x3 |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 275 | #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */ |
| 276 | #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */ |
| 277 | #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */ |
| 278 | |
| 279 | enum tricore_features { |
| 280 | TRICORE_FEATURE_13, |
| 281 | TRICORE_FEATURE_131, |
| 282 | TRICORE_FEATURE_16, |
Bastian Koppelmann | 6d2afc8 | 2015-05-06 20:18:41 +0200 | [diff] [blame] | 283 | TRICORE_FEATURE_161, |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | static inline int tricore_feature(CPUTriCoreState *env, int feature) |
| 287 | { |
| 288 | return (env->features & (1ULL << feature)) != 0; |
| 289 | } |
| 290 | |
| 291 | /* TriCore Traps Classes*/ |
| 292 | enum { |
| 293 | TRAPC_NONE = -1, |
| 294 | TRAPC_MMU = 0, |
| 295 | TRAPC_PROT = 1, |
| 296 | TRAPC_INSN_ERR = 2, |
| 297 | TRAPC_CTX_MNG = 3, |
| 298 | TRAPC_SYSBUS = 4, |
| 299 | TRAPC_ASSERT = 5, |
| 300 | TRAPC_SYSCALL = 6, |
| 301 | TRAPC_NMI = 7, |
Bastian Koppelmann | 518d7fd | 2016-02-19 14:43:43 +0100 | [diff] [blame] | 302 | TRAPC_IRQ = 8 |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 303 | }; |
| 304 | |
| 305 | /* Class 0 TIN */ |
| 306 | enum { |
| 307 | TIN0_VAF = 0, |
| 308 | TIN0_VAP = 1, |
| 309 | }; |
| 310 | |
| 311 | /* Class 1 TIN */ |
| 312 | enum { |
| 313 | TIN1_PRIV = 1, |
| 314 | TIN1_MPR = 2, |
| 315 | TIN1_MPW = 3, |
| 316 | TIN1_MPX = 4, |
| 317 | TIN1_MPP = 5, |
| 318 | TIN1_MPN = 6, |
| 319 | TIN1_GRWP = 7, |
| 320 | }; |
| 321 | |
| 322 | /* Class 2 TIN */ |
| 323 | enum { |
| 324 | TIN2_IOPC = 1, |
| 325 | TIN2_UOPC = 2, |
| 326 | TIN2_OPD = 3, |
| 327 | TIN2_ALN = 4, |
| 328 | TIN2_MEM = 5, |
| 329 | }; |
| 330 | |
| 331 | /* Class 3 TIN */ |
| 332 | enum { |
| 333 | TIN3_FCD = 1, |
| 334 | TIN3_CDO = 2, |
| 335 | TIN3_CDU = 3, |
| 336 | TIN3_FCU = 4, |
| 337 | TIN3_CSU = 5, |
| 338 | TIN3_CTYP = 6, |
| 339 | TIN3_NEST = 7, |
| 340 | }; |
| 341 | |
| 342 | /* Class 4 TIN */ |
| 343 | enum { |
| 344 | TIN4_PSE = 1, |
| 345 | TIN4_DSE = 2, |
| 346 | TIN4_DAE = 3, |
| 347 | TIN4_CAE = 4, |
| 348 | TIN4_PIE = 5, |
| 349 | TIN4_DIE = 6, |
| 350 | }; |
| 351 | |
| 352 | /* Class 5 TIN */ |
| 353 | enum { |
| 354 | TIN5_OVF = 1, |
| 355 | TIN5_SOVF = 1, |
| 356 | }; |
| 357 | |
| 358 | /* Class 6 TIN |
| 359 | * |
| 360 | * Is always TIN6_SYS |
| 361 | */ |
| 362 | |
| 363 | /* Class 7 TIN */ |
| 364 | enum { |
| 365 | TIN7_NMI = 0, |
| 366 | }; |
| 367 | |
| 368 | uint32_t psw_read(CPUTriCoreState *env); |
| 369 | void psw_write(CPUTriCoreState *env, uint32_t val); |
| 370 | |
Bastian Koppelmann | 996a729 | 2016-03-11 16:03:11 +0100 | [diff] [blame] | 371 | void fpu_set_state(CPUTriCoreState *env); |
| 372 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 373 | #define MMU_USER_IDX 2 |
| 374 | |
Markus Armbruster | 0442428 | 2019-04-17 21:17:57 +0200 | [diff] [blame] | 375 | void tricore_cpu_list(void); |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 376 | |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 377 | #define cpu_signal_handler cpu_tricore_signal_handler |
| 378 | #define cpu_list tricore_cpu_list |
| 379 | |
Benjamin Herrenschmidt | 97ed5cc | 2015-08-17 17:34:10 +1000 | [diff] [blame] | 380 | static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 381 | { |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | |
| 386 | |
| 387 | #include "exec/cpu-all.h" |
| 388 | |
| 389 | enum { |
| 390 | /* 1 bit to define user level / supervisor access */ |
| 391 | ACCESS_USER = 0x00, |
| 392 | ACCESS_SUPER = 0x01, |
| 393 | /* 1 bit to indicate direction */ |
| 394 | ACCESS_STORE = 0x02, |
| 395 | /* Type of instruction that generated the access */ |
| 396 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 397 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 398 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 399 | }; |
| 400 | |
| 401 | void cpu_state_reset(CPUTriCoreState *s); |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 402 | void tricore_tcg_init(void); |
| 403 | int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); |
| 404 | |
| 405 | static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, |
Emilio G. Cota | 89fee74 | 2016-04-07 13:19:22 -0400 | [diff] [blame] | 406 | target_ulong *cs_base, uint32_t *flags) |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 407 | { |
| 408 | *pc = env->PC; |
| 409 | *cs_base = 0; |
| 410 | *flags = 0; |
| 411 | } |
| 412 | |
Igor Mammedov | b9ad9d5 | 2017-10-05 15:51:03 +0200 | [diff] [blame] | 413 | #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU |
| 414 | #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX |
Igor Mammedov | 0dacec8 | 2018-02-07 11:40:25 +0100 | [diff] [blame] | 415 | #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 416 | |
| 417 | /* helpers.c */ |
Richard Henderson | 68d6eee | 2019-04-03 07:27:29 +0700 | [diff] [blame] | 418 | bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 419 | MMUAccessType access_type, int mmu_idx, |
| 420 | bool probe, uintptr_t retaddr); |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 421 | |
Markus Armbruster | 07f5a25 | 2016-06-29 11:05:55 +0200 | [diff] [blame] | 422 | #endif /* TRICORE_CPU_H */ |