bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * defines common to all virtual CPUs |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 18 | */ |
| 19 | #ifndef CPU_ALL_H |
| 20 | #define CPU_ALL_H |
| 21 | |
blueswir1 | 7d99a00 | 2009-01-14 19:00:36 +0000 | [diff] [blame] | 22 | #include "qemu-common.h" |
Paolo Bonzini | b3c4bbe | 2011-10-28 10:52:42 +0100 | [diff] [blame] | 23 | #include "qemu-tls.h" |
Paul Brook | 1ad2134 | 2009-05-19 16:17:58 +0100 | [diff] [blame] | 24 | #include "cpu-common.h" |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 25 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 26 | /* some important defines: |
| 27 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 28 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned |
| 29 | * memory accesses. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 30 | * |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 31 | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 32 | * otherwise little endian. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 33 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 34 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 35 | * |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 36 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
| 37 | */ |
| 38 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 39 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 40 | #define BSWAP_NEEDED |
| 41 | #endif |
| 42 | |
| 43 | #ifdef BSWAP_NEEDED |
| 44 | |
| 45 | static inline uint16_t tswap16(uint16_t s) |
| 46 | { |
| 47 | return bswap16(s); |
| 48 | } |
| 49 | |
| 50 | static inline uint32_t tswap32(uint32_t s) |
| 51 | { |
| 52 | return bswap32(s); |
| 53 | } |
| 54 | |
| 55 | static inline uint64_t tswap64(uint64_t s) |
| 56 | { |
| 57 | return bswap64(s); |
| 58 | } |
| 59 | |
| 60 | static inline void tswap16s(uint16_t *s) |
| 61 | { |
| 62 | *s = bswap16(*s); |
| 63 | } |
| 64 | |
| 65 | static inline void tswap32s(uint32_t *s) |
| 66 | { |
| 67 | *s = bswap32(*s); |
| 68 | } |
| 69 | |
| 70 | static inline void tswap64s(uint64_t *s) |
| 71 | { |
| 72 | *s = bswap64(*s); |
| 73 | } |
| 74 | |
| 75 | #else |
| 76 | |
| 77 | static inline uint16_t tswap16(uint16_t s) |
| 78 | { |
| 79 | return s; |
| 80 | } |
| 81 | |
| 82 | static inline uint32_t tswap32(uint32_t s) |
| 83 | { |
| 84 | return s; |
| 85 | } |
| 86 | |
| 87 | static inline uint64_t tswap64(uint64_t s) |
| 88 | { |
| 89 | return s; |
| 90 | } |
| 91 | |
| 92 | static inline void tswap16s(uint16_t *s) |
| 93 | { |
| 94 | } |
| 95 | |
| 96 | static inline void tswap32s(uint32_t *s) |
| 97 | { |
| 98 | } |
| 99 | |
| 100 | static inline void tswap64s(uint64_t *s) |
| 101 | { |
| 102 | } |
| 103 | |
| 104 | #endif |
| 105 | |
| 106 | #if TARGET_LONG_SIZE == 4 |
| 107 | #define tswapl(s) tswap32(s) |
| 108 | #define tswapls(s) tswap32s((uint32_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 109 | #define bswaptls(s) bswap32s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 110 | #else |
| 111 | #define tswapl(s) tswap64(s) |
| 112 | #define tswapls(s) tswap64s((uint64_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 113 | #define bswaptls(s) bswap64s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 114 | #endif |
| 115 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 116 | /* CPU memory access without any memory or io remapping */ |
| 117 | |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 118 | /* |
| 119 | * the generic syntax for the memory accesses is: |
| 120 | * |
| 121 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) |
| 122 | * |
| 123 | * store: st{type}{size}{endian}_{access_type}(ptr, val) |
| 124 | * |
| 125 | * type is: |
| 126 | * (empty): integer access |
| 127 | * f : float access |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 128 | * |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 129 | * sign is: |
| 130 | * (empty): for floats or 32 bit size |
| 131 | * u : unsigned |
| 132 | * s : signed |
| 133 | * |
| 134 | * size is: |
| 135 | * b: 8 bits |
| 136 | * w: 16 bits |
| 137 | * l: 32 bits |
| 138 | * q: 64 bits |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 139 | * |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 140 | * endian is: |
| 141 | * (empty): target cpu endianness or 8 bit access |
| 142 | * r : reversed target cpu endianness (not implemented yet) |
| 143 | * be : big endian (not implemented yet) |
| 144 | * le : little endian (not implemented yet) |
| 145 | * |
| 146 | * access_type is: |
| 147 | * raw : host memory access |
| 148 | * user : user mode access using soft MMU |
| 149 | * kernel : kernel mode access using soft MMU |
| 150 | */ |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 151 | |
Paolo Bonzini | cbbab92 | 2011-07-28 12:10:30 +0200 | [diff] [blame] | 152 | /* target-endianness CPU memory access functions */ |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 153 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 154 | #define lduw_p(p) lduw_be_p(p) |
| 155 | #define ldsw_p(p) ldsw_be_p(p) |
| 156 | #define ldl_p(p) ldl_be_p(p) |
| 157 | #define ldq_p(p) ldq_be_p(p) |
| 158 | #define ldfl_p(p) ldfl_be_p(p) |
| 159 | #define ldfq_p(p) ldfq_be_p(p) |
| 160 | #define stw_p(p, v) stw_be_p(p, v) |
| 161 | #define stl_p(p, v) stl_be_p(p, v) |
| 162 | #define stq_p(p, v) stq_be_p(p, v) |
| 163 | #define stfl_p(p, v) stfl_be_p(p, v) |
| 164 | #define stfq_p(p, v) stfq_be_p(p, v) |
| 165 | #else |
| 166 | #define lduw_p(p) lduw_le_p(p) |
| 167 | #define ldsw_p(p) ldsw_le_p(p) |
| 168 | #define ldl_p(p) ldl_le_p(p) |
| 169 | #define ldq_p(p) ldq_le_p(p) |
| 170 | #define ldfl_p(p) ldfl_le_p(p) |
| 171 | #define ldfq_p(p) ldfq_le_p(p) |
| 172 | #define stw_p(p, v) stw_le_p(p, v) |
| 173 | #define stl_p(p, v) stl_le_p(p, v) |
| 174 | #define stq_p(p, v) stq_le_p(p, v) |
| 175 | #define stfl_p(p, v) stfl_le_p(p, v) |
| 176 | #define stfq_p(p, v) stfq_le_p(p, v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 177 | #endif |
| 178 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 179 | /* MMU memory access macros */ |
| 180 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 181 | #if defined(CONFIG_USER_ONLY) |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 182 | #include <assert.h> |
| 183 | #include "qemu-types.h" |
| 184 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 185 | /* On some host systems the guest address space is reserved on the host. |
| 186 | * This allows the guest address space to be offset to a convenient location. |
| 187 | */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 188 | #if defined(CONFIG_USE_GUEST_BASE) |
| 189 | extern unsigned long guest_base; |
| 190 | extern int have_guest_base; |
Paul Brook | 68a1c81 | 2010-05-29 02:27:35 +0100 | [diff] [blame] | 191 | extern unsigned long reserved_va; |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 192 | #define GUEST_BASE guest_base |
Aurelien Jarno | 18e9ea8 | 2010-07-30 21:09:10 +0200 | [diff] [blame] | 193 | #define RESERVED_VA reserved_va |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 194 | #else |
| 195 | #define GUEST_BASE 0ul |
Aurelien Jarno | 18e9ea8 | 2010-07-30 21:09:10 +0200 | [diff] [blame] | 196 | #define RESERVED_VA 0ul |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 197 | #endif |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 198 | |
| 199 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ |
Peter Maydell | 8d9dde9 | 2012-03-09 14:33:20 +0000 | [diff] [blame] | 200 | #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) |
Richard Henderson | b9f8312 | 2010-03-10 14:36:58 -0800 | [diff] [blame] | 201 | |
| 202 | #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS |
| 203 | #define h2g_valid(x) 1 |
| 204 | #else |
| 205 | #define h2g_valid(x) ({ \ |
| 206 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ |
Alexander Graf | 39879bb | 2012-02-02 03:14:18 +0100 | [diff] [blame] | 207 | (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ |
| 208 | (!RESERVED_VA || (__guest < RESERVED_VA)); \ |
Richard Henderson | b9f8312 | 2010-03-10 14:36:58 -0800 | [diff] [blame] | 209 | }) |
| 210 | #endif |
| 211 | |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 212 | #define h2g(x) ({ \ |
| 213 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ |
| 214 | /* Check if given address fits target address space */ \ |
Richard Henderson | b9f8312 | 2010-03-10 14:36:58 -0800 | [diff] [blame] | 215 | assert(h2g_valid(x)); \ |
aurel32 | 0e62fd7 | 2008-12-08 18:12:11 +0000 | [diff] [blame] | 216 | (abi_ulong)__ret; \ |
| 217 | }) |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 218 | |
| 219 | #define saddr(x) g2h(x) |
| 220 | #define laddr(x) g2h(x) |
| 221 | |
| 222 | #else /* !CONFIG_USER_ONLY */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 223 | /* NOTE: we use double casts if pointers and target_ulong have |
| 224 | different sizes */ |
Stefan Weil | 27b0dc1 | 2012-04-15 15:18:29 +0200 | [diff] [blame] | 225 | #define saddr(x) (uint8_t *)(intptr_t)(x) |
| 226 | #define laddr(x) (uint8_t *)(intptr_t)(x) |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 227 | #endif |
| 228 | |
| 229 | #define ldub_raw(p) ldub_p(laddr((p))) |
| 230 | #define ldsb_raw(p) ldsb_p(laddr((p))) |
| 231 | #define lduw_raw(p) lduw_p(laddr((p))) |
| 232 | #define ldsw_raw(p) ldsw_p(laddr((p))) |
| 233 | #define ldl_raw(p) ldl_p(laddr((p))) |
| 234 | #define ldq_raw(p) ldq_p(laddr((p))) |
| 235 | #define ldfl_raw(p) ldfl_p(laddr((p))) |
| 236 | #define ldfq_raw(p) ldfq_p(laddr((p))) |
| 237 | #define stb_raw(p, v) stb_p(saddr((p)), v) |
| 238 | #define stw_raw(p, v) stw_p(saddr((p)), v) |
| 239 | #define stl_raw(p, v) stl_p(saddr((p)), v) |
| 240 | #define stq_raw(p, v) stq_p(saddr((p)), v) |
| 241 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) |
| 242 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 243 | |
| 244 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 245 | #if defined(CONFIG_USER_ONLY) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 246 | |
| 247 | /* if user mode, no other memory access functions */ |
| 248 | #define ldub(p) ldub_raw(p) |
| 249 | #define ldsb(p) ldsb_raw(p) |
| 250 | #define lduw(p) lduw_raw(p) |
| 251 | #define ldsw(p) ldsw_raw(p) |
| 252 | #define ldl(p) ldl_raw(p) |
| 253 | #define ldq(p) ldq_raw(p) |
| 254 | #define ldfl(p) ldfl_raw(p) |
| 255 | #define ldfq(p) ldfq_raw(p) |
| 256 | #define stb(p, v) stb_raw(p, v) |
| 257 | #define stw(p, v) stw_raw(p, v) |
| 258 | #define stl(p, v) stl_raw(p, v) |
| 259 | #define stq(p, v) stq_raw(p, v) |
| 260 | #define stfl(p, v) stfl_raw(p, v) |
| 261 | #define stfq(p, v) stfq_raw(p, v) |
| 262 | |
Blue Swirl | e141ab5 | 2011-09-18 14:55:46 +0000 | [diff] [blame] | 263 | #ifndef CONFIG_TCG_PASS_AREG0 |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 264 | #define ldub_code(p) ldub_raw(p) |
| 265 | #define ldsb_code(p) ldsb_raw(p) |
| 266 | #define lduw_code(p) lduw_raw(p) |
| 267 | #define ldsw_code(p) ldsw_raw(p) |
| 268 | #define ldl_code(p) ldl_raw(p) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 269 | #define ldq_code(p) ldq_raw(p) |
Blue Swirl | e141ab5 | 2011-09-18 14:55:46 +0000 | [diff] [blame] | 270 | #else |
| 271 | #define cpu_ldub_code(env1, p) ldub_raw(p) |
| 272 | #define cpu_ldsb_code(env1, p) ldsb_raw(p) |
| 273 | #define cpu_lduw_code(env1, p) lduw_raw(p) |
| 274 | #define cpu_ldsw_code(env1, p) ldsw_raw(p) |
| 275 | #define cpu_ldl_code(env1, p) ldl_raw(p) |
| 276 | #define cpu_ldq_code(env1, p) ldq_raw(p) |
| 277 | #endif |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 278 | |
| 279 | #define ldub_kernel(p) ldub_raw(p) |
| 280 | #define ldsb_kernel(p) ldsb_raw(p) |
| 281 | #define lduw_kernel(p) lduw_raw(p) |
| 282 | #define ldsw_kernel(p) ldsw_raw(p) |
| 283 | #define ldl_kernel(p) ldl_raw(p) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 284 | #define ldq_kernel(p) ldq_raw(p) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 285 | #define ldfl_kernel(p) ldfl_raw(p) |
| 286 | #define ldfq_kernel(p) ldfq_raw(p) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 287 | #define stb_kernel(p, v) stb_raw(p, v) |
| 288 | #define stw_kernel(p, v) stw_raw(p, v) |
| 289 | #define stl_kernel(p, v) stl_raw(p, v) |
| 290 | #define stq_kernel(p, v) stq_raw(p, v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 291 | #define stfl_kernel(p, v) stfl_raw(p, v) |
| 292 | #define stfq_kernel(p, vt) stfq_raw(p, v) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 293 | |
| 294 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 295 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 296 | /* page related stuff */ |
| 297 | |
aurel32 | 0387544 | 2008-04-22 20:45:18 +0000 | [diff] [blame] | 298 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 299 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
| 300 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
| 301 | |
Stefan Weil | c6d5067 | 2012-03-16 20:23:49 +0100 | [diff] [blame] | 302 | /* ??? These should be the larger of uintptr_t and target_ulong. */ |
| 303 | extern uintptr_t qemu_real_host_page_size; |
| 304 | extern uintptr_t qemu_host_page_size; |
| 305 | extern uintptr_t qemu_host_page_mask; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 306 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 307 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 308 | |
| 309 | /* same as PROT_xxx */ |
| 310 | #define PAGE_READ 0x0001 |
| 311 | #define PAGE_WRITE 0x0002 |
| 312 | #define PAGE_EXEC 0x0004 |
| 313 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) |
| 314 | #define PAGE_VALID 0x0008 |
| 315 | /* original state of the write flag (used when tracking self-modifying |
| 316 | code */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 317 | #define PAGE_WRITE_ORG 0x0010 |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 318 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
| 319 | /* FIXME: Code that sets/uses this is broken and needs to go away. */ |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 320 | #define PAGE_RESERVED 0x0020 |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 321 | #endif |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 322 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 323 | #if defined(CONFIG_USER_ONLY) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 324 | void page_dump(FILE *f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 325 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 326 | typedef int (*walk_memory_regions_fn)(void *, abi_ulong, |
| 327 | abi_ulong, unsigned long); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 328 | int walk_memory_regions(void *, walk_memory_regions_fn); |
| 329 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 330 | int page_get_flags(target_ulong address); |
| 331 | void page_set_flags(target_ulong start, target_ulong end, int flags); |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 332 | int page_check_range(target_ulong start, target_ulong len, int flags); |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 333 | #endif |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 334 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 335 | CPUArchState *cpu_copy(CPUArchState *env); |
| 336 | CPUArchState *qemu_get_cpu(int cpu); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 337 | |
Jan Kiszka | f5c848e | 2011-01-21 21:48:08 +0100 | [diff] [blame] | 338 | #define CPU_DUMP_CODE 0x00010000 |
| 339 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 340 | void cpu_dump_state(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf, |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 341 | int flags); |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 342 | void cpu_dump_statistics(CPUArchState *env, FILE *f, fprintf_function cpu_fprintf, |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 343 | int flags); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 344 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 345 | void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) |
Stefan Weil | 2c80e42 | 2010-10-13 20:54:27 +0200 | [diff] [blame] | 346 | GCC_FMT_ATTR(2, 3); |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 347 | extern CPUArchState *first_cpu; |
| 348 | DECLARE_TLS(CPUArchState *,cpu_single_env); |
Jan Kiszka | 4a2dd92 | 2011-12-05 15:18:54 +0100 | [diff] [blame] | 349 | #define cpu_single_env tls_var(cpu_single_env) |
Paolo Bonzini | db1a497 | 2010-03-10 11:38:55 +0100 | [diff] [blame] | 350 | |
Richard Henderson | 9c76219 | 2011-05-04 13:34:24 -0700 | [diff] [blame] | 351 | /* Flags for use in ENV->INTERRUPT_PENDING. |
| 352 | |
| 353 | The numbers assigned here are non-sequential in order to preserve |
| 354 | binary compatibility with the vmstate dump. Bit 0 (0x0001) was |
| 355 | previously used for CPU_INTERRUPT_EXIT, and is cleared when loading |
| 356 | the vmstate dump. */ |
| 357 | |
| 358 | /* External hardware interrupt pending. This is typically used for |
| 359 | interrupts from devices. */ |
| 360 | #define CPU_INTERRUPT_HARD 0x0002 |
| 361 | |
| 362 | /* Exit the current TB. This is typically used when some system-level device |
| 363 | makes some change to the memory mapping. E.g. the a20 line change. */ |
| 364 | #define CPU_INTERRUPT_EXITTB 0x0004 |
| 365 | |
| 366 | /* Halt the CPU. */ |
| 367 | #define CPU_INTERRUPT_HALT 0x0020 |
| 368 | |
| 369 | /* Debug event pending. */ |
| 370 | #define CPU_INTERRUPT_DEBUG 0x0080 |
| 371 | |
| 372 | /* Several target-specific external hardware interrupts. Each target/cpu.h |
| 373 | should define proper names based on these defines. */ |
| 374 | #define CPU_INTERRUPT_TGT_EXT_0 0x0008 |
| 375 | #define CPU_INTERRUPT_TGT_EXT_1 0x0010 |
| 376 | #define CPU_INTERRUPT_TGT_EXT_2 0x0040 |
| 377 | #define CPU_INTERRUPT_TGT_EXT_3 0x0200 |
| 378 | #define CPU_INTERRUPT_TGT_EXT_4 0x1000 |
| 379 | |
| 380 | /* Several target-specific internal interrupts. These differ from the |
Dong Xu Wang | 07f3507 | 2011-11-22 18:06:26 +0800 | [diff] [blame] | 381 | preceding target-specific interrupts in that they are intended to |
Richard Henderson | 9c76219 | 2011-05-04 13:34:24 -0700 | [diff] [blame] | 382 | originate from within the cpu itself, typically in response to some |
| 383 | instruction being executed. These, therefore, are not masked while |
| 384 | single-stepping within the debugger. */ |
| 385 | #define CPU_INTERRUPT_TGT_INT_0 0x0100 |
| 386 | #define CPU_INTERRUPT_TGT_INT_1 0x0400 |
| 387 | #define CPU_INTERRUPT_TGT_INT_2 0x0800 |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 388 | #define CPU_INTERRUPT_TGT_INT_3 0x2000 |
Richard Henderson | 9c76219 | 2011-05-04 13:34:24 -0700 | [diff] [blame] | 389 | |
Jan Kiszka | d362e75 | 2012-02-17 18:31:17 +0100 | [diff] [blame] | 390 | /* First unused bit: 0x4000. */ |
Richard Henderson | 9c76219 | 2011-05-04 13:34:24 -0700 | [diff] [blame] | 391 | |
Richard Henderson | 3125f76 | 2011-05-04 13:34:25 -0700 | [diff] [blame] | 392 | /* The set of all bits that should be masked when single-stepping. */ |
| 393 | #define CPU_INTERRUPT_SSTEP_MASK \ |
| 394 | (CPU_INTERRUPT_HARD \ |
| 395 | | CPU_INTERRUPT_TGT_EXT_0 \ |
| 396 | | CPU_INTERRUPT_TGT_EXT_1 \ |
| 397 | | CPU_INTERRUPT_TGT_EXT_2 \ |
| 398 | | CPU_INTERRUPT_TGT_EXT_3 \ |
| 399 | | CPU_INTERRUPT_TGT_EXT_4) |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 400 | |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 401 | #ifndef CONFIG_USER_ONLY |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 402 | typedef void (*CPUInterruptHandler)(CPUArchState *, int); |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 403 | |
| 404 | extern CPUInterruptHandler cpu_interrupt_handler; |
| 405 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 406 | static inline void cpu_interrupt(CPUArchState *s, int mask) |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 407 | { |
| 408 | cpu_interrupt_handler(s, mask); |
| 409 | } |
| 410 | #else /* USER_ONLY */ |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 411 | void cpu_interrupt(CPUArchState *env, int mask); |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 412 | #endif /* USER_ONLY */ |
| 413 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 414 | void cpu_reset_interrupt(CPUArchState *env, int mask); |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 415 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 416 | void cpu_exit(CPUArchState *s); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 417 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 418 | bool qemu_cpu_has_work(CPUArchState *env); |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 419 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 420 | /* Breakpoint/watchpoint flags */ |
| 421 | #define BP_MEM_READ 0x01 |
| 422 | #define BP_MEM_WRITE 0x02 |
| 423 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 424 | #define BP_STOP_BEFORE_ACCESS 0x04 |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 425 | #define BP_WATCHPOINT_HIT 0x08 |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 426 | #define BP_GDB 0x10 |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 427 | #define BP_CPU 0x20 |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 428 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 429 | int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 430 | CPUBreakpoint **breakpoint); |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 431 | int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); |
| 432 | void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); |
| 433 | void cpu_breakpoint_remove_all(CPUArchState *env, int mask); |
| 434 | int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 435 | int flags, CPUWatchpoint **watchpoint); |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 436 | int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 437 | target_ulong len, int flags); |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 438 | void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); |
| 439 | void cpu_watchpoint_remove_all(CPUArchState *env, int mask); |
edgar_igl | 60897d3 | 2008-05-09 08:25:14 +0000 | [diff] [blame] | 440 | |
| 441 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
| 442 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
| 443 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
| 444 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 445 | void cpu_single_step(CPUArchState *env, int enabled); |
| 446 | void cpu_state_reset(CPUArchState *s); |
| 447 | int cpu_is_stopped(CPUArchState *env); |
| 448 | void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 449 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 450 | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 451 | #define CPU_LOG_TB_IN_ASM (1 << 1) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 452 | #define CPU_LOG_TB_OP (1 << 2) |
| 453 | #define CPU_LOG_TB_OP_OPT (1 << 3) |
| 454 | #define CPU_LOG_INT (1 << 4) |
| 455 | #define CPU_LOG_EXEC (1 << 5) |
| 456 | #define CPU_LOG_PCALL (1 << 6) |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 457 | #define CPU_LOG_IOPORT (1 << 7) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 458 | #define CPU_LOG_TB_CPU (1 << 8) |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 459 | #define CPU_LOG_RESET (1 << 9) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 460 | |
| 461 | /* define log items */ |
| 462 | typedef struct CPULogItem { |
| 463 | int mask; |
| 464 | const char *name; |
| 465 | const char *help; |
| 466 | } CPULogItem; |
| 467 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 468 | extern const CPULogItem cpu_log_items[]; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 469 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 470 | void cpu_set_log(int log_flags); |
| 471 | void cpu_set_log_filename(const char *filename); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 472 | int cpu_str_to_log_mask(const char *str); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 473 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 474 | #if !defined(CONFIG_USER_ONLY) |
| 475 | |
Paul Brook | 4fcc562 | 2010-03-01 03:46:18 +0000 | [diff] [blame] | 476 | /* Return the physical page corresponding to a virtual one. Use it |
| 477 | only for debugging because no protection checks are done. Return -1 |
| 478 | if no page found. */ |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 479 | target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr); |
Paul Brook | 4fcc562 | 2010-03-01 03:46:18 +0000 | [diff] [blame] | 480 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 481 | /* memory API */ |
| 482 | |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 483 | extern int phys_ram_fd; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 484 | extern ram_addr_t ram_size; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 485 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 486 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ |
| 487 | #define RAM_PREALLOC_MASK (1 << 0) |
| 488 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 489 | typedef struct RAMBlock { |
Avi Kivity | 7c63736 | 2011-12-21 13:09:49 +0200 | [diff] [blame] | 490 | struct MemoryRegion *mr; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 491 | uint8_t *host; |
| 492 | ram_addr_t offset; |
| 493 | ram_addr_t length; |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 494 | uint32_t flags; |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 495 | char idstr[256]; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 496 | QLIST_ENTRY(RAMBlock) next; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 497 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 498 | int fd; |
| 499 | #endif |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 500 | } RAMBlock; |
| 501 | |
| 502 | typedef struct RAMList { |
| 503 | uint8_t *phys_dirty; |
Paolo Bonzini | 85d59fe | 2011-08-12 13:18:14 +0200 | [diff] [blame] | 504 | QLIST_HEAD(, RAMBlock) blocks; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 505 | } RAMList; |
| 506 | extern RAMList ram_list; |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 507 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 508 | extern const char *mem_path; |
| 509 | extern int mem_prealloc; |
| 510 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 511 | /* Flags stored in the low bits of the TLB virtual address. These are |
| 512 | defined so that fast path ram access is all zeros. */ |
| 513 | /* Zero if TLB entry is valid. */ |
| 514 | #define TLB_INVALID_MASK (1 << 3) |
| 515 | /* Set if TLB entry references a clean RAM page. The iotlb entry will |
| 516 | contain the page physical address. */ |
| 517 | #define TLB_NOTDIRTY (1 << 4) |
| 518 | /* Set if TLB entry is an IO callback. */ |
| 519 | #define TLB_MMIO (1 << 5) |
| 520 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 521 | void cpu_tlb_update_dirty(CPUArchState *env); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 522 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 523 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 524 | #endif /* !CONFIG_USER_ONLY */ |
| 525 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 526 | int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr, |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 527 | uint8_t *buf, int len, int is_write); |
| 528 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 529 | #endif /* CPU_ALL_H */ |