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thscd1a3f62007-09-29 19:40:09 +00001/*
2 * SuperH Timer modules.
3 *
4 * Copyright (c) 2007 Magnus Damm
5 * Based on arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
7 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10008 * This code is licensed under the GPL.
thscd1a3f62007-09-29 19:40:09 +00009 */
10
Peter Maydell282bc812016-01-26 18:17:18 +000011#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010012#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010013#include "hw/sh4/sh.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010014#include "qemu/timer.h"
Alex Bligh6a1751b2013-08-21 16:02:47 +010015#include "qemu/main-loop.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010016#include "hw/ptimer.h"
thscd1a3f62007-09-29 19:40:09 +000017
18//#define DEBUG_TIMER
19
20#define TIMER_TCR_TPSC (7 << 0)
21#define TIMER_TCR_CKEG (3 << 3)
22#define TIMER_TCR_UNIE (1 << 5)
23#define TIMER_TCR_ICPE (3 << 6)
24#define TIMER_TCR_UNF (1 << 8)
25#define TIMER_TCR_ICPF (1 << 9)
26#define TIMER_TCR_RESERVED (0x3f << 10)
27
28#define TIMER_FEAT_CAPT (1 << 0)
29#define TIMER_FEAT_EXTCLK (1 << 1)
30
aurel32e7786f22009-02-07 15:18:47 +000031#define OFFSET_TCOR 0
32#define OFFSET_TCNT 1
33#define OFFSET_TCR 2
34#define OFFSET_TCPR 3
35
thscd1a3f62007-09-29 19:40:09 +000036typedef struct {
37 ptimer_state *timer;
38 uint32_t tcnt;
39 uint32_t tcor;
40 uint32_t tcr;
41 uint32_t tcpr;
42 int freq;
43 int int_level;
balrog703243a2007-12-12 01:11:42 +000044 int old_level;
thscd1a3f62007-09-29 19:40:09 +000045 int feat;
46 int enabled;
aurel3296e2fc42008-11-21 21:06:42 +000047 qemu_irq irq;
thscd1a3f62007-09-29 19:40:09 +000048} sh_timer_state;
49
50/* Check all active timers, and schedule the next timer interrupt. */
51
52static void sh_timer_update(sh_timer_state *s)
53{
balrog703243a2007-12-12 01:11:42 +000054 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
55
56 if (new_level != s->old_level)
aurel3296e2fc42008-11-21 21:06:42 +000057 qemu_set_irq (s->irq, new_level);
balrog703243a2007-12-12 01:11:42 +000058
59 s->old_level = s->int_level;
60 s->int_level = new_level;
thscd1a3f62007-09-29 19:40:09 +000061}
62
Avi Kivitya8170e52012-10-23 12:30:10 +020063static uint32_t sh_timer_read(void *opaque, hwaddr offset)
thscd1a3f62007-09-29 19:40:09 +000064{
65 sh_timer_state *s = (sh_timer_state *)opaque;
66
67 switch (offset >> 2) {
aurel32e7786f22009-02-07 15:18:47 +000068 case OFFSET_TCOR:
thscd1a3f62007-09-29 19:40:09 +000069 return s->tcor;
aurel32e7786f22009-02-07 15:18:47 +000070 case OFFSET_TCNT:
thscd1a3f62007-09-29 19:40:09 +000071 return ptimer_get_count(s->timer);
aurel32e7786f22009-02-07 15:18:47 +000072 case OFFSET_TCR:
thscd1a3f62007-09-29 19:40:09 +000073 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
aurel32e7786f22009-02-07 15:18:47 +000074 case OFFSET_TCPR:
thscd1a3f62007-09-29 19:40:09 +000075 if (s->feat & TIMER_FEAT_CAPT)
76 return s->tcpr;
Paolo Bonziniedd75412018-08-01 17:14:09 +020077 /* fall through */
thscd1a3f62007-09-29 19:40:09 +000078 default:
Paul Brook2ac71172009-05-08 02:35:15 +010079 hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
thscd1a3f62007-09-29 19:40:09 +000080 return 0;
81 }
82}
83
Avi Kivitya8170e52012-10-23 12:30:10 +020084static void sh_timer_write(void *opaque, hwaddr offset,
thscd1a3f62007-09-29 19:40:09 +000085 uint32_t value)
86{
87 sh_timer_state *s = (sh_timer_state *)opaque;
88 int freq;
89
90 switch (offset >> 2) {
aurel32e7786f22009-02-07 15:18:47 +000091 case OFFSET_TCOR:
thscd1a3f62007-09-29 19:40:09 +000092 s->tcor = value;
93 ptimer_set_limit(s->timer, s->tcor, 0);
94 break;
aurel32e7786f22009-02-07 15:18:47 +000095 case OFFSET_TCNT:
thscd1a3f62007-09-29 19:40:09 +000096 s->tcnt = value;
97 ptimer_set_count(s->timer, s->tcnt);
98 break;
aurel32e7786f22009-02-07 15:18:47 +000099 case OFFSET_TCR:
thscd1a3f62007-09-29 19:40:09 +0000100 if (s->enabled) {
101 /* Pause the timer if it is running. This may cause some
102 inaccuracy dure to rounding, but avoids a whole lot of other
103 messyness. */
104 ptimer_stop(s->timer);
105 }
106 freq = s->freq;
107 /* ??? Need to recalculate expiry time after changing divisor. */
108 switch (value & TIMER_TCR_TPSC) {
109 case 0: freq >>= 2; break;
110 case 1: freq >>= 4; break;
111 case 2: freq >>= 6; break;
112 case 3: freq >>= 8; break;
113 case 4: freq >>= 10; break;
114 case 6:
115 case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
Paul Brook2ac71172009-05-08 02:35:15 +0100116 default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
thscd1a3f62007-09-29 19:40:09 +0000117 }
118 switch ((value & TIMER_TCR_CKEG) >> 3) {
119 case 0: break;
120 case 1:
121 case 2:
122 case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
Paul Brook2ac71172009-05-08 02:35:15 +0100123 default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
thscd1a3f62007-09-29 19:40:09 +0000124 }
125 switch ((value & TIMER_TCR_ICPE) >> 6) {
126 case 0: break;
127 case 2:
128 case 3: if (s->feat & TIMER_FEAT_CAPT) break;
Paul Brook2ac71172009-05-08 02:35:15 +0100129 default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
thscd1a3f62007-09-29 19:40:09 +0000130 }
131 if ((value & TIMER_TCR_UNF) == 0)
132 s->int_level = 0;
133
134 value &= ~TIMER_TCR_UNF;
135
136 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
Paul Brook2ac71172009-05-08 02:35:15 +0100137 hw_error("sh_timer_write: Reserved ICPF value\n");
thscd1a3f62007-09-29 19:40:09 +0000138
139 value &= ~TIMER_TCR_ICPF; /* capture not supported */
140
141 if (value & TIMER_TCR_RESERVED)
Paul Brook2ac71172009-05-08 02:35:15 +0100142 hw_error("sh_timer_write: Reserved TCR bits set\n");
thscd1a3f62007-09-29 19:40:09 +0000143 s->tcr = value;
144 ptimer_set_limit(s->timer, s->tcor, 0);
145 ptimer_set_freq(s->timer, freq);
146 if (s->enabled) {
147 /* Restart the timer if still enabled. */
148 ptimer_run(s->timer, 0);
149 }
150 break;
aurel32e7786f22009-02-07 15:18:47 +0000151 case OFFSET_TCPR:
thscd1a3f62007-09-29 19:40:09 +0000152 if (s->feat & TIMER_FEAT_CAPT) {
153 s->tcpr = value;
154 break;
155 }
156 default:
Paul Brook2ac71172009-05-08 02:35:15 +0100157 hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
thscd1a3f62007-09-29 19:40:09 +0000158 }
159 sh_timer_update(s);
160}
161
162static void sh_timer_start_stop(void *opaque, int enable)
163{
164 sh_timer_state *s = (sh_timer_state *)opaque;
165
166#ifdef DEBUG_TIMER
167 printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
168#endif
169
170 if (s->enabled && !enable) {
171 ptimer_stop(s->timer);
172 }
173 if (!s->enabled && enable) {
174 ptimer_run(s->timer, 0);
175 }
176 s->enabled = !!enable;
177
178#ifdef DEBUG_TIMER
179 printf("sh_timer_start_stop done %d\n", s->enabled);
180#endif
181}
182
183static void sh_timer_tick(void *opaque)
184{
185 sh_timer_state *s = (sh_timer_state *)opaque;
186 s->int_level = s->enabled;
187 sh_timer_update(s);
188}
189
aurel3296e2fc42008-11-21 21:06:42 +0000190static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
thscd1a3f62007-09-29 19:40:09 +0000191{
192 sh_timer_state *s;
193 QEMUBH *bh;
194
Anthony Liguori7267c092011-08-20 22:09:37 -0500195 s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
thscd1a3f62007-09-29 19:40:09 +0000196 s->freq = freq;
197 s->feat = feat;
198 s->tcor = 0xffffffff;
199 s->tcnt = 0xffffffff;
200 s->tcpr = 0xdeadbeef;
aurel32e7786f22009-02-07 15:18:47 +0000201 s->tcr = 0;
thscd1a3f62007-09-29 19:40:09 +0000202 s->enabled = 0;
balrog703243a2007-12-12 01:11:42 +0000203 s->irq = irq;
thscd1a3f62007-09-29 19:40:09 +0000204
205 bh = qemu_bh_new(sh_timer_tick, s);
Dmitry Osipenkoe7ea81c2016-09-22 18:13:06 +0100206 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
aurel32e7786f22009-02-07 15:18:47 +0000207
208 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
209 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
210 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
211 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
thscd1a3f62007-09-29 19:40:09 +0000212 /* ??? Save/restore. */
213 return s;
214}
215
216typedef struct {
Benoît Canet89e29452011-11-17 14:23:00 +0100217 MemoryRegion iomem;
218 MemoryRegion iomem_p4;
219 MemoryRegion iomem_a7;
thscd1a3f62007-09-29 19:40:09 +0000220 void *timer[3];
221 int level[3];
222 uint32_t tocr;
223 uint32_t tstr;
thscd1a3f62007-09-29 19:40:09 +0000224 int feat;
225} tmu012_state;
226
Avi Kivitya8170e52012-10-23 12:30:10 +0200227static uint64_t tmu012_read(void *opaque, hwaddr offset,
Benoît Canet89e29452011-11-17 14:23:00 +0100228 unsigned size)
thscd1a3f62007-09-29 19:40:09 +0000229{
230 tmu012_state *s = (tmu012_state *)opaque;
231
232#ifdef DEBUG_TIMER
233 printf("tmu012_read 0x%lx\n", (unsigned long) offset);
234#endif
thscd1a3f62007-09-29 19:40:09 +0000235
236 if (offset >= 0x20) {
237 if (!(s->feat & TMU012_FEAT_3CHAN))
Paul Brook2ac71172009-05-08 02:35:15 +0100238 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
thscd1a3f62007-09-29 19:40:09 +0000239 return sh_timer_read(s->timer[2], offset - 0x20);
240 }
241
242 if (offset >= 0x14)
243 return sh_timer_read(s->timer[1], offset - 0x14);
244
245 if (offset >= 0x08)
246 return sh_timer_read(s->timer[0], offset - 0x08);
247
248 if (offset == 4)
249 return s->tstr;
250
251 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
252 return s->tocr;
253
Paul Brook2ac71172009-05-08 02:35:15 +0100254 hw_error("tmu012_write: Bad offset %x\n", (int)offset);
thscd1a3f62007-09-29 19:40:09 +0000255 return 0;
256}
257
Avi Kivitya8170e52012-10-23 12:30:10 +0200258static void tmu012_write(void *opaque, hwaddr offset,
Benoît Canet89e29452011-11-17 14:23:00 +0100259 uint64_t value, unsigned size)
thscd1a3f62007-09-29 19:40:09 +0000260{
261 tmu012_state *s = (tmu012_state *)opaque;
262
263#ifdef DEBUG_TIMER
264 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
265#endif
thscd1a3f62007-09-29 19:40:09 +0000266
267 if (offset >= 0x20) {
268 if (!(s->feat & TMU012_FEAT_3CHAN))
Paul Brook2ac71172009-05-08 02:35:15 +0100269 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
thscd1a3f62007-09-29 19:40:09 +0000270 sh_timer_write(s->timer[2], offset - 0x20, value);
271 return;
272 }
273
274 if (offset >= 0x14) {
275 sh_timer_write(s->timer[1], offset - 0x14, value);
276 return;
277 }
278
279 if (offset >= 0x08) {
280 sh_timer_write(s->timer[0], offset - 0x08, value);
281 return;
282 }
283
284 if (offset == 4) {
285 sh_timer_start_stop(s->timer[0], value & (1 << 0));
286 sh_timer_start_stop(s->timer[1], value & (1 << 1));
287 if (s->feat & TMU012_FEAT_3CHAN)
288 sh_timer_start_stop(s->timer[2], value & (1 << 2));
289 else
290 if (value & (1 << 2))
Paul Brook2ac71172009-05-08 02:35:15 +0100291 hw_error("tmu012_write: Bad channel\n");
thscd1a3f62007-09-29 19:40:09 +0000292
293 s->tstr = value;
294 return;
295 }
296
297 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
298 s->tocr = value & (1 << 0);
299 }
300}
301
Benoît Canet89e29452011-11-17 14:23:00 +0100302static const MemoryRegionOps tmu012_ops = {
303 .read = tmu012_read,
304 .write = tmu012_write,
305 .endianness = DEVICE_NATIVE_ENDIAN,
thscd1a3f62007-09-29 19:40:09 +0000306};
307
Avi Kivitya8170e52012-10-23 12:30:10 +0200308void tmu012_init(MemoryRegion *sysmem, hwaddr base,
Benoît Canet89e29452011-11-17 14:23:00 +0100309 int feat, uint32_t freq,
aurel3296e2fc42008-11-21 21:06:42 +0000310 qemu_irq ch0_irq, qemu_irq ch1_irq,
311 qemu_irq ch2_irq0, qemu_irq ch2_irq1)
thscd1a3f62007-09-29 19:40:09 +0000312{
thscd1a3f62007-09-29 19:40:09 +0000313 tmu012_state *s;
314 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
315
Anthony Liguori7267c092011-08-20 22:09:37 -0500316 s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
thscd1a3f62007-09-29 19:40:09 +0000317 s->feat = feat;
balrog703243a2007-12-12 01:11:42 +0000318 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
319 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
thscd1a3f62007-09-29 19:40:09 +0000320 if (feat & TMU012_FEAT_3CHAN)
balrog703243a2007-12-12 01:11:42 +0000321 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
322 ch2_irq0); /* ch2_irq1 not supported */
Benoît Canet89e29452011-11-17 14:23:00 +0100323
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400324 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
Benoît Canet89e29452011-11-17 14:23:00 +0100325 "timer", 0x100000000ULL);
326
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400327 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
Benoît Canet89e29452011-11-17 14:23:00 +0100328 &s->iomem, 0, 0x1000);
329 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
330
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400331 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
Benoît Canet89e29452011-11-17 14:23:00 +0100332 &s->iomem, 0, 0x1000);
333 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
thscd1a3f62007-09-29 19:40:09 +0000334 /* ??? Save/restore. */
335}