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bellard267002c2004-06-03 18:46:20 +00001/*
j_mayer3cbee152007-10-28 23:42:18 +00002 * QEMU PowerMac CUDA device support
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer3cbee152007-10-28 23:42:18 +00004 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
ths5fafdf22007-09-16 21:08:06 +00006 *
bellard267002c2004-06-03 18:46:20 +00007 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
pbrook87ecb682007-11-17 17:14:51 +000025#include "hw.h"
j_mayer3cbee152007-10-28 23:42:18 +000026#include "ppc_mac.h"
Laurent Vivier7a880d92011-09-04 08:41:15 +000027#include "adb.h"
pbrook87ecb682007-11-17 17:14:51 +000028#include "qemu-timer.h"
29#include "sysemu.h"
bellard267002c2004-06-03 18:46:20 +000030
bellard61271e52005-07-07 21:45:18 +000031/* XXX: implement all timer modes */
32
blueswir1ea026b22008-12-24 09:38:16 +000033/* debug CUDA */
bellard819e7122004-06-21 16:47:13 +000034//#define DEBUG_CUDA
blueswir1ea026b22008-12-24 09:38:16 +000035
36/* debug CUDA packets */
bellard819e7122004-06-21 16:47:13 +000037//#define DEBUG_CUDA_PACKET
38
blueswir1ea026b22008-12-24 09:38:16 +000039#ifdef DEBUG_CUDA
Blue Swirl001faf32009-05-13 17:53:17 +000040#define CUDA_DPRINTF(fmt, ...) \
41 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
blueswir1ea026b22008-12-24 09:38:16 +000042#else
Blue Swirl001faf32009-05-13 17:53:17 +000043#define CUDA_DPRINTF(fmt, ...)
blueswir1ea026b22008-12-24 09:38:16 +000044#endif
45
bellard267002c2004-06-03 18:46:20 +000046/* Bits in B data register: all active low */
47#define TREQ 0x08 /* Transfer request (input) */
48#define TACK 0x10 /* Transfer acknowledge (output) */
49#define TIP 0x20 /* Transfer in progress (output) */
50
51/* Bits in ACR */
52#define SR_CTRL 0x1c /* Shift register control bits */
53#define SR_EXT 0x0c /* Shift on external clock */
54#define SR_OUT 0x10 /* Shift out if 1 */
55
56/* Bits in IFR and IER */
57#define IER_SET 0x80 /* set bits in IER */
58#define IER_CLR 0 /* clear bits in IER */
59#define SR_INT 0x04 /* Shift register full/empty */
60#define T1_INT 0x40 /* Timer 1 interrupt */
bellard61271e52005-07-07 21:45:18 +000061#define T2_INT 0x20 /* Timer 2 interrupt */
bellard267002c2004-06-03 18:46:20 +000062
63/* Bits in ACR */
64#define T1MODE 0xc0 /* Timer 1 mode */
65#define T1MODE_CONT 0x40 /* continuous interrupts */
66
67/* commands (1st byte) */
68#define ADB_PACKET 0
69#define CUDA_PACKET 1
70#define ERROR_PACKET 2
71#define TIMER_PACKET 3
72#define POWER_PACKET 4
73#define MACIIC_PACKET 5
74#define PMU_PACKET 6
75
76
77/* CUDA commands (2nd byte) */
78#define CUDA_WARM_START 0x0
79#define CUDA_AUTOPOLL 0x1
80#define CUDA_GET_6805_ADDR 0x2
81#define CUDA_GET_TIME 0x3
82#define CUDA_GET_PRAM 0x7
83#define CUDA_SET_6805_ADDR 0x8
84#define CUDA_SET_TIME 0x9
85#define CUDA_POWERDOWN 0xa
86#define CUDA_POWERUP_TIME 0xb
87#define CUDA_SET_PRAM 0xc
88#define CUDA_MS_RESET 0xd
89#define CUDA_SEND_DFAC 0xe
90#define CUDA_BATTERY_SWAP_SENSE 0x10
91#define CUDA_RESET_SYSTEM 0x11
92#define CUDA_SET_IPL 0x12
93#define CUDA_FILE_SERVER_FLAG 0x13
94#define CUDA_SET_AUTO_RATE 0x14
95#define CUDA_GET_AUTO_RATE 0x16
96#define CUDA_SET_DEVICE_LIST 0x19
97#define CUDA_GET_DEVICE_LIST 0x1a
98#define CUDA_SET_ONE_SECOND_MODE 0x1b
99#define CUDA_SET_POWER_MESSAGES 0x21
100#define CUDA_GET_SET_IIC 0x22
101#define CUDA_WAKEUP 0x23
102#define CUDA_TIMER_TICKLE 0x24
103#define CUDA_COMBINED_FORMAT_IIC 0x25
104
105#define CUDA_TIMER_FREQ (4700000 / 6)
bellarde2733d22004-06-21 22:46:10 +0000106#define CUDA_ADB_POLL_FREQ 50
bellard267002c2004-06-03 18:46:20 +0000107
bellardd7ce2962005-02-09 00:07:08 +0000108/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
109#define RTC_OFFSET 2082844800
110
bellard267002c2004-06-03 18:46:20 +0000111typedef struct CUDATimer {
ths5fafdf22007-09-16 21:08:06 +0000112 int index;
bellard61271e52005-07-07 21:45:18 +0000113 uint16_t latch;
bellard267002c2004-06-03 18:46:20 +0000114 uint16_t counter_value; /* counter value at load time */
115 int64_t load_time;
116 int64_t next_irq_time;
117 QEMUTimer *timer;
118} CUDATimer;
119
120typedef struct CUDAState {
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300121 MemoryRegion mem;
bellard267002c2004-06-03 18:46:20 +0000122 /* cuda registers */
123 uint8_t b; /* B-side data */
124 uint8_t a; /* A-side data */
125 uint8_t dirb; /* B-side direction (1=output) */
126 uint8_t dira; /* A-side direction (1=output) */
127 uint8_t sr; /* Shift register */
128 uint8_t acr; /* Auxiliary control register */
129 uint8_t pcr; /* Peripheral control register */
130 uint8_t ifr; /* Interrupt flag register */
131 uint8_t ier; /* Interrupt enable register */
132 uint8_t anh; /* A-side data, no handshake */
133
134 CUDATimer timers[2];
ths3b46e622007-09-17 08:09:54 +0000135
aurel325703c172009-01-15 18:57:15 +0000136 uint32_t tick_offset;
137
bellard267002c2004-06-03 18:46:20 +0000138 uint8_t last_b; /* last value of B register */
139 uint8_t last_acr; /* last value of B register */
ths3b46e622007-09-17 08:09:54 +0000140
bellard267002c2004-06-03 18:46:20 +0000141 int data_in_size;
142 int data_in_index;
143 int data_out_index;
144
pbrookd537cf62007-04-07 18:14:41 +0000145 qemu_irq irq;
bellard267002c2004-06-03 18:46:20 +0000146 uint8_t autopoll;
147 uint8_t data_in[128];
148 uint8_t data_out[16];
bellarde2733d22004-06-21 22:46:10 +0000149 QEMUTimer *adb_poll_timer;
bellard267002c2004-06-03 18:46:20 +0000150} CUDAState;
151
152static CUDAState cuda_state;
153ADBBusState adb_bus;
154
155static void cuda_update(CUDAState *s);
ths5fafdf22007-09-16 21:08:06 +0000156static void cuda_receive_packet_from_host(CUDAState *s,
bellard267002c2004-06-03 18:46:20 +0000157 const uint8_t *data, int len);
ths5fafdf22007-09-16 21:08:06 +0000158static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
bellard819e7122004-06-21 16:47:13 +0000159 int64_t current_time);
bellard267002c2004-06-03 18:46:20 +0000160
161static void cuda_update_irq(CUDAState *s)
162{
bellard819e7122004-06-21 16:47:13 +0000163 if (s->ifr & s->ier & (SR_INT | T1_INT)) {
pbrookd537cf62007-04-07 18:14:41 +0000164 qemu_irq_raise(s->irq);
bellard267002c2004-06-03 18:46:20 +0000165 } else {
pbrookd537cf62007-04-07 18:14:41 +0000166 qemu_irq_lower(s->irq);
bellard267002c2004-06-03 18:46:20 +0000167 }
168}
169
170static unsigned int get_counter(CUDATimer *s)
171{
172 int64_t d;
173 unsigned int counter;
174
Paolo Bonzini74475452011-03-11 16:47:48 +0100175 d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time,
Juan Quintela6ee093c2009-09-10 03:04:26 +0200176 CUDA_TIMER_FREQ, get_ticks_per_sec());
bellard61271e52005-07-07 21:45:18 +0000177 if (s->index == 0) {
178 /* the timer goes down from latch to -1 (period of latch + 2) */
179 if (d <= (s->counter_value + 1)) {
180 counter = (s->counter_value - d) & 0xffff;
181 } else {
182 counter = (d - (s->counter_value + 1)) % (s->latch + 2);
ths5fafdf22007-09-16 21:08:06 +0000183 counter = (s->latch - counter) & 0xffff;
bellard61271e52005-07-07 21:45:18 +0000184 }
bellard267002c2004-06-03 18:46:20 +0000185 } else {
bellard61271e52005-07-07 21:45:18 +0000186 counter = (s->counter_value - d) & 0xffff;
bellard267002c2004-06-03 18:46:20 +0000187 }
188 return counter;
189}
190
bellard819e7122004-06-21 16:47:13 +0000191static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
bellard267002c2004-06-03 18:46:20 +0000192{
blueswir1ea026b22008-12-24 09:38:16 +0000193 CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
Paolo Bonzini74475452011-03-11 16:47:48 +0100194 ti->load_time = qemu_get_clock_ns(vm_clock);
bellard819e7122004-06-21 16:47:13 +0000195 ti->counter_value = val;
196 cuda_timer_update(s, ti, ti->load_time);
bellard267002c2004-06-03 18:46:20 +0000197}
198
199static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
200{
bellard61271e52005-07-07 21:45:18 +0000201 int64_t d, next_time;
202 unsigned int counter;
203
bellard267002c2004-06-03 18:46:20 +0000204 /* current counter value */
ths5fafdf22007-09-16 21:08:06 +0000205 d = muldiv64(current_time - s->load_time,
Juan Quintela6ee093c2009-09-10 03:04:26 +0200206 CUDA_TIMER_FREQ, get_ticks_per_sec());
bellard61271e52005-07-07 21:45:18 +0000207 /* the timer goes down from latch to -1 (period of latch + 2) */
208 if (d <= (s->counter_value + 1)) {
209 counter = (s->counter_value - d) & 0xffff;
210 } else {
211 counter = (d - (s->counter_value + 1)) % (s->latch + 2);
ths5fafdf22007-09-16 21:08:06 +0000212 counter = (s->latch - counter) & 0xffff;
bellard61271e52005-07-07 21:45:18 +0000213 }
ths3b46e622007-09-17 08:09:54 +0000214
bellard61271e52005-07-07 21:45:18 +0000215 /* Note: we consider the irq is raised on 0 */
216 if (counter == 0xffff) {
217 next_time = d + s->latch + 1;
218 } else if (counter == 0) {
219 next_time = d + s->latch + 2;
220 } else {
221 next_time = d + counter;
bellard267002c2004-06-03 18:46:20 +0000222 }
blueswir1ea026b22008-12-24 09:38:16 +0000223 CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
224 s->latch, d, next_time - d);
Juan Quintela6ee093c2009-09-10 03:04:26 +0200225 next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) +
bellard267002c2004-06-03 18:46:20 +0000226 s->load_time;
227 if (next_time <= current_time)
228 next_time = current_time + 1;
229 return next_time;
230}
231
ths5fafdf22007-09-16 21:08:06 +0000232static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
bellard819e7122004-06-21 16:47:13 +0000233 int64_t current_time)
234{
235 if (!ti->timer)
236 return;
237 if ((s->acr & T1MODE) != T1MODE_CONT) {
238 qemu_del_timer(ti->timer);
239 } else {
240 ti->next_irq_time = get_next_irq_time(ti, current_time);
241 qemu_mod_timer(ti->timer, ti->next_irq_time);
242 }
243}
244
bellard267002c2004-06-03 18:46:20 +0000245static void cuda_timer1(void *opaque)
246{
247 CUDAState *s = opaque;
248 CUDATimer *ti = &s->timers[0];
249
bellard819e7122004-06-21 16:47:13 +0000250 cuda_timer_update(s, ti, ti->next_irq_time);
bellard267002c2004-06-03 18:46:20 +0000251 s->ifr |= T1_INT;
252 cuda_update_irq(s);
253}
254
Anthony Liguoric227f092009-10-01 16:12:16 -0500255static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
bellard267002c2004-06-03 18:46:20 +0000256{
257 CUDAState *s = opaque;
258 uint32_t val;
259
260 addr = (addr >> 9) & 0xf;
261 switch(addr) {
262 case 0:
263 val = s->b;
264 break;
265 case 1:
266 val = s->a;
267 break;
268 case 2:
269 val = s->dirb;
270 break;
271 case 3:
272 val = s->dira;
273 break;
274 case 4:
275 val = get_counter(&s->timers[0]) & 0xff;
276 s->ifr &= ~T1_INT;
277 cuda_update_irq(s);
278 break;
279 case 5:
280 val = get_counter(&s->timers[0]) >> 8;
bellard267002c2004-06-03 18:46:20 +0000281 cuda_update_irq(s);
282 break;
283 case 6:
284 val = s->timers[0].latch & 0xff;
285 break;
286 case 7:
bellard61271e52005-07-07 21:45:18 +0000287 /* XXX: check this */
bellard267002c2004-06-03 18:46:20 +0000288 val = (s->timers[0].latch >> 8) & 0xff;
289 break;
290 case 8:
291 val = get_counter(&s->timers[1]) & 0xff;
bellard61271e52005-07-07 21:45:18 +0000292 s->ifr &= ~T2_INT;
bellard267002c2004-06-03 18:46:20 +0000293 break;
294 case 9:
295 val = get_counter(&s->timers[1]) >> 8;
296 break;
297 case 10:
bellard819e7122004-06-21 16:47:13 +0000298 val = s->sr;
299 s->ifr &= ~SR_INT;
300 cuda_update_irq(s);
bellard267002c2004-06-03 18:46:20 +0000301 break;
302 case 11:
303 val = s->acr;
304 break;
305 case 12:
306 val = s->pcr;
307 break;
308 case 13:
309 val = s->ifr;
ths5fafdf22007-09-16 21:08:06 +0000310 if (s->ifr & s->ier)
bellardb7c7b182005-07-23 14:01:47 +0000311 val |= 0x80;
bellard267002c2004-06-03 18:46:20 +0000312 break;
313 case 14:
bellardb7c7b182005-07-23 14:01:47 +0000314 val = s->ier | 0x80;
bellard267002c2004-06-03 18:46:20 +0000315 break;
316 default:
317 case 15:
318 val = s->anh;
319 break;
320 }
Blue Swirl3c83eb42010-04-18 08:45:03 +0000321 if (addr != 13 || val != 0) {
blueswir1ea026b22008-12-24 09:38:16 +0000322 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
Blue Swirl3c83eb42010-04-18 08:45:03 +0000323 }
324
bellard267002c2004-06-03 18:46:20 +0000325 return val;
326}
327
Anthony Liguoric227f092009-10-01 16:12:16 -0500328static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard267002c2004-06-03 18:46:20 +0000329{
330 CUDAState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000331
bellard267002c2004-06-03 18:46:20 +0000332 addr = (addr >> 9) & 0xf;
blueswir1ea026b22008-12-24 09:38:16 +0000333 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
bellard267002c2004-06-03 18:46:20 +0000334
335 switch(addr) {
336 case 0:
337 s->b = val;
338 cuda_update(s);
339 break;
340 case 1:
341 s->a = val;
342 break;
343 case 2:
344 s->dirb = val;
345 break;
346 case 3:
347 s->dira = val;
348 break;
349 case 4:
bellard61271e52005-07-07 21:45:18 +0000350 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
Paolo Bonzini74475452011-03-11 16:47:48 +0100351 cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
bellard267002c2004-06-03 18:46:20 +0000352 break;
353 case 5:
bellard61271e52005-07-07 21:45:18 +0000354 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
355 s->ifr &= ~T1_INT;
356 set_counter(s, &s->timers[0], s->timers[0].latch);
bellard267002c2004-06-03 18:46:20 +0000357 break;
358 case 6:
359 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
Paolo Bonzini74475452011-03-11 16:47:48 +0100360 cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
bellard267002c2004-06-03 18:46:20 +0000361 break;
362 case 7:
363 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
bellard61271e52005-07-07 21:45:18 +0000364 s->ifr &= ~T1_INT;
Paolo Bonzini74475452011-03-11 16:47:48 +0100365 cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
bellard267002c2004-06-03 18:46:20 +0000366 break;
367 case 8:
bellard61271e52005-07-07 21:45:18 +0000368 s->timers[1].latch = val;
bellard819e7122004-06-21 16:47:13 +0000369 set_counter(s, &s->timers[1], val);
bellard267002c2004-06-03 18:46:20 +0000370 break;
371 case 9:
bellard61271e52005-07-07 21:45:18 +0000372 set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
bellard267002c2004-06-03 18:46:20 +0000373 break;
374 case 10:
375 s->sr = val;
376 break;
377 case 11:
378 s->acr = val;
Paolo Bonzini74475452011-03-11 16:47:48 +0100379 cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
bellard267002c2004-06-03 18:46:20 +0000380 cuda_update(s);
381 break;
382 case 12:
383 s->pcr = val;
384 break;
385 case 13:
386 /* reset bits */
387 s->ifr &= ~val;
388 cuda_update_irq(s);
389 break;
390 case 14:
391 if (val & IER_SET) {
392 /* set bits */
393 s->ier |= val & 0x7f;
394 } else {
395 /* reset bits */
396 s->ier &= ~val;
397 }
398 cuda_update_irq(s);
399 break;
400 default:
401 case 15:
402 s->anh = val;
403 break;
404 }
405}
406
407/* NOTE: TIP and TREQ are negated */
408static void cuda_update(CUDAState *s)
409{
bellard819e7122004-06-21 16:47:13 +0000410 int packet_received, len;
bellard267002c2004-06-03 18:46:20 +0000411
bellard819e7122004-06-21 16:47:13 +0000412 packet_received = 0;
413 if (!(s->b & TIP)) {
414 /* transfer requested from host */
415
416 if (s->acr & SR_OUT) {
417 /* data output */
418 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
419 if (s->data_out_index < sizeof(s->data_out)) {
blueswir1ea026b22008-12-24 09:38:16 +0000420 CUDA_DPRINTF("send: %02x\n", s->sr);
bellard819e7122004-06-21 16:47:13 +0000421 s->data_out[s->data_out_index++] = s->sr;
422 s->ifr |= SR_INT;
423 cuda_update_irq(s);
424 }
bellard267002c2004-06-03 18:46:20 +0000425 }
bellard819e7122004-06-21 16:47:13 +0000426 } else {
427 if (s->data_in_index < s->data_in_size) {
428 /* data input */
429 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
430 s->sr = s->data_in[s->data_in_index++];
blueswir1ea026b22008-12-24 09:38:16 +0000431 CUDA_DPRINTF("recv: %02x\n", s->sr);
bellard819e7122004-06-21 16:47:13 +0000432 /* indicate end of transfer */
433 if (s->data_in_index >= s->data_in_size) {
434 s->b = (s->b | TREQ);
435 }
436 s->ifr |= SR_INT;
437 cuda_update_irq(s);
438 }
439 }
440 }
441 } else {
442 /* no transfer requested: handle sync case */
443 if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
444 /* update TREQ state each time TACK change state */
445 if (s->b & TACK)
446 s->b = (s->b | TREQ);
447 else
448 s->b = (s->b & ~TREQ);
bellard267002c2004-06-03 18:46:20 +0000449 s->ifr |= SR_INT;
450 cuda_update_irq(s);
bellard819e7122004-06-21 16:47:13 +0000451 } else {
452 if (!(s->last_b & TIP)) {
thse91c8a72007-06-03 13:35:16 +0000453 /* handle end of host to cuda transfer */
bellard819e7122004-06-21 16:47:13 +0000454 packet_received = (s->data_out_index > 0);
thse91c8a72007-06-03 13:35:16 +0000455 /* always an IRQ at the end of transfer */
bellard819e7122004-06-21 16:47:13 +0000456 s->ifr |= SR_INT;
457 cuda_update_irq(s);
458 }
459 /* signal if there is data to read */
460 if (s->data_in_index < s->data_in_size) {
461 s->b = (s->b & ~TREQ);
462 }
bellard267002c2004-06-03 18:46:20 +0000463 }
464 }
465
bellard267002c2004-06-03 18:46:20 +0000466 s->last_acr = s->acr;
467 s->last_b = s->b;
bellard819e7122004-06-21 16:47:13 +0000468
469 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
470 recursively */
471 if (packet_received) {
472 len = s->data_out_index;
473 s->data_out_index = 0;
474 cuda_receive_packet_from_host(s, s->data_out, len);
475 }
bellard267002c2004-06-03 18:46:20 +0000476}
477
ths5fafdf22007-09-16 21:08:06 +0000478static void cuda_send_packet_to_host(CUDAState *s,
bellard267002c2004-06-03 18:46:20 +0000479 const uint8_t *data, int len)
480{
bellard819e7122004-06-21 16:47:13 +0000481#ifdef DEBUG_CUDA_PACKET
482 {
483 int i;
484 printf("cuda_send_packet_to_host:\n");
485 for(i = 0; i < len; i++)
486 printf(" %02x", data[i]);
487 printf("\n");
488 }
489#endif
bellard267002c2004-06-03 18:46:20 +0000490 memcpy(s->data_in, data, len);
491 s->data_in_size = len;
492 s->data_in_index = 0;
493 cuda_update(s);
494 s->ifr |= SR_INT;
495 cuda_update_irq(s);
496}
497
bellard7db4eea2004-07-06 20:57:47 +0000498static void cuda_adb_poll(void *opaque)
bellarde2733d22004-06-21 22:46:10 +0000499{
500 CUDAState *s = opaque;
501 uint8_t obuf[ADB_MAX_OUT_LEN + 2];
502 int olen;
503
504 olen = adb_poll(&adb_bus, obuf + 2);
505 if (olen > 0) {
506 obuf[0] = ADB_PACKET;
507 obuf[1] = 0x40; /* polled data */
508 cuda_send_packet_to_host(s, obuf, olen + 2);
509 }
ths5fafdf22007-09-16 21:08:06 +0000510 qemu_mod_timer(s->adb_poll_timer,
Paolo Bonzini74475452011-03-11 16:47:48 +0100511 qemu_get_clock_ns(vm_clock) +
Juan Quintela6ee093c2009-09-10 03:04:26 +0200512 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
bellarde2733d22004-06-21 22:46:10 +0000513}
514
ths5fafdf22007-09-16 21:08:06 +0000515static void cuda_receive_packet(CUDAState *s,
bellard267002c2004-06-03 18:46:20 +0000516 const uint8_t *data, int len)
517{
518 uint8_t obuf[16];
aurel325703c172009-01-15 18:57:15 +0000519 int autopoll;
520 uint32_t ti;
bellard267002c2004-06-03 18:46:20 +0000521
522 switch(data[0]) {
523 case CUDA_AUTOPOLL:
bellarde2733d22004-06-21 22:46:10 +0000524 autopoll = (data[1] != 0);
525 if (autopoll != s->autopoll) {
526 s->autopoll = autopoll;
527 if (autopoll) {
ths5fafdf22007-09-16 21:08:06 +0000528 qemu_mod_timer(s->adb_poll_timer,
Paolo Bonzini74475452011-03-11 16:47:48 +0100529 qemu_get_clock_ns(vm_clock) +
Juan Quintela6ee093c2009-09-10 03:04:26 +0200530 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
bellarde2733d22004-06-21 22:46:10 +0000531 } else {
532 qemu_del_timer(s->adb_poll_timer);
533 }
534 }
bellard267002c2004-06-03 18:46:20 +0000535 obuf[0] = CUDA_PACKET;
536 obuf[1] = data[1];
537 cuda_send_packet_to_host(s, obuf, 2);
538 break;
bellarddccfafc2005-04-23 18:16:54 +0000539 case CUDA_SET_TIME:
aurel325703c172009-01-15 18:57:15 +0000540 ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
Paolo Bonzini74475452011-03-11 16:47:48 +0100541 s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
aurel325703c172009-01-15 18:57:15 +0000542 obuf[0] = CUDA_PACKET;
543 obuf[1] = 0;
544 obuf[2] = 0;
545 cuda_send_packet_to_host(s, obuf, 3);
546 break;
547 case CUDA_GET_TIME:
Paolo Bonzini74475452011-03-11 16:47:48 +0100548 ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
bellard267002c2004-06-03 18:46:20 +0000549 obuf[0] = CUDA_PACKET;
550 obuf[1] = 0;
551 obuf[2] = 0;
552 obuf[3] = ti >> 24;
553 obuf[4] = ti >> 16;
554 obuf[5] = ti >> 8;
555 obuf[6] = ti;
556 cuda_send_packet_to_host(s, obuf, 7);
557 break;
bellard267002c2004-06-03 18:46:20 +0000558 case CUDA_FILE_SERVER_FLAG:
559 case CUDA_SET_DEVICE_LIST:
560 case CUDA_SET_AUTO_RATE:
561 case CUDA_SET_POWER_MESSAGES:
562 obuf[0] = CUDA_PACKET;
563 obuf[1] = 0;
564 cuda_send_packet_to_host(s, obuf, 2);
565 break;
bellardd7ce2962005-02-09 00:07:08 +0000566 case CUDA_POWERDOWN:
567 obuf[0] = CUDA_PACKET;
568 obuf[1] = 0;
569 cuda_send_packet_to_host(s, obuf, 2);
aurel32c76ee252009-01-15 18:57:25 +0000570 qemu_system_shutdown_request();
571 break;
j_mayer06869702007-09-19 04:46:57 +0000572 case CUDA_RESET_SYSTEM:
573 obuf[0] = CUDA_PACKET;
574 obuf[1] = 0;
575 cuda_send_packet_to_host(s, obuf, 2);
576 qemu_system_reset_request();
577 break;
bellard267002c2004-06-03 18:46:20 +0000578 default:
579 break;
580 }
581}
582
ths5fafdf22007-09-16 21:08:06 +0000583static void cuda_receive_packet_from_host(CUDAState *s,
bellard267002c2004-06-03 18:46:20 +0000584 const uint8_t *data, int len)
585{
bellard819e7122004-06-21 16:47:13 +0000586#ifdef DEBUG_CUDA_PACKET
587 {
588 int i;
bellardcadae952005-06-05 15:24:23 +0000589 printf("cuda_receive_packet_from_host:\n");
bellard819e7122004-06-21 16:47:13 +0000590 for(i = 0; i < len; i++)
591 printf(" %02x", data[i]);
592 printf("\n");
593 }
594#endif
bellard267002c2004-06-03 18:46:20 +0000595 switch(data[0]) {
596 case ADB_PACKET:
bellarde2733d22004-06-21 22:46:10 +0000597 {
598 uint8_t obuf[ADB_MAX_OUT_LEN + 2];
599 int olen;
600 olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
bellard38f0b142004-07-12 20:16:00 +0000601 if (olen > 0) {
bellarde2733d22004-06-21 22:46:10 +0000602 obuf[0] = ADB_PACKET;
603 obuf[1] = 0x00;
604 } else {
bellard38f0b142004-07-12 20:16:00 +0000605 /* error */
bellarde2733d22004-06-21 22:46:10 +0000606 obuf[0] = ADB_PACKET;
bellard38f0b142004-07-12 20:16:00 +0000607 obuf[1] = -olen;
608 olen = 0;
bellarde2733d22004-06-21 22:46:10 +0000609 }
610 cuda_send_packet_to_host(s, obuf, olen + 2);
611 }
bellard267002c2004-06-03 18:46:20 +0000612 break;
613 case CUDA_PACKET:
614 cuda_receive_packet(s, data + 1, len - 1);
615 break;
616 }
617}
618
Anthony Liguoric227f092009-10-01 16:12:16 -0500619static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
bellard267002c2004-06-03 18:46:20 +0000620{
621}
622
Anthony Liguoric227f092009-10-01 16:12:16 -0500623static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
bellard267002c2004-06-03 18:46:20 +0000624{
625}
626
Anthony Liguoric227f092009-10-01 16:12:16 -0500627static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
bellard267002c2004-06-03 18:46:20 +0000628{
629 return 0;
630}
631
Anthony Liguoric227f092009-10-01 16:12:16 -0500632static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
bellard267002c2004-06-03 18:46:20 +0000633{
634 return 0;
635}
636
Stefan Weila348f102012-02-05 10:19:07 +0000637static const MemoryRegionOps cuda_ops = {
Alexander Grafea0a7eb2011-09-08 18:51:17 +0200638 .old_mmio = {
639 .write = {
640 cuda_writeb,
641 cuda_writew,
642 cuda_writel,
643 },
644 .read = {
645 cuda_readb,
646 cuda_readw,
647 cuda_readl,
648 },
649 },
650 .endianness = DEVICE_NATIVE_ENDIAN,
bellard267002c2004-06-03 18:46:20 +0000651};
652
Juan Quintelac0a93a92010-12-02 13:53:24 +0100653static bool cuda_timer_exist(void *opaque, int version_id)
blueswir19b649972008-12-30 19:01:19 +0000654{
Juan Quintelac0a93a92010-12-02 13:53:24 +0100655 CUDATimer *s = opaque;
656
657 return s->timer != NULL;
blueswir19b649972008-12-30 19:01:19 +0000658}
659
Juan Quintelac0a93a92010-12-02 13:53:24 +0100660static const VMStateDescription vmstate_cuda_timer = {
661 .name = "cuda_timer",
662 .version_id = 0,
663 .minimum_version_id = 0,
664 .minimum_version_id_old = 0,
665 .fields = (VMStateField[]) {
666 VMSTATE_UINT16(latch, CUDATimer),
667 VMSTATE_UINT16(counter_value, CUDATimer),
668 VMSTATE_INT64(load_time, CUDATimer),
669 VMSTATE_INT64(next_irq_time, CUDATimer),
670 VMSTATE_TIMER_TEST(timer, CUDATimer, cuda_timer_exist),
671 VMSTATE_END_OF_LIST()
672 }
673};
blueswir19b649972008-12-30 19:01:19 +0000674
Juan Quintelac0a93a92010-12-02 13:53:24 +0100675static const VMStateDescription vmstate_cuda = {
676 .name = "cuda",
677 .version_id = 1,
678 .minimum_version_id = 1,
679 .minimum_version_id_old = 1,
680 .fields = (VMStateField[]) {
681 VMSTATE_UINT8(a, CUDAState),
682 VMSTATE_UINT8(b, CUDAState),
683 VMSTATE_UINT8(dira, CUDAState),
684 VMSTATE_UINT8(dirb, CUDAState),
685 VMSTATE_UINT8(sr, CUDAState),
686 VMSTATE_UINT8(acr, CUDAState),
687 VMSTATE_UINT8(pcr, CUDAState),
688 VMSTATE_UINT8(ifr, CUDAState),
689 VMSTATE_UINT8(ier, CUDAState),
690 VMSTATE_UINT8(anh, CUDAState),
691 VMSTATE_INT32(data_in_size, CUDAState),
692 VMSTATE_INT32(data_in_index, CUDAState),
693 VMSTATE_INT32(data_out_index, CUDAState),
694 VMSTATE_UINT8(autopoll, CUDAState),
695 VMSTATE_BUFFER(data_in, CUDAState),
696 VMSTATE_BUFFER(data_out, CUDAState),
697 VMSTATE_UINT32(tick_offset, CUDAState),
698 VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
699 vmstate_cuda_timer, CUDATimer),
700 VMSTATE_END_OF_LIST()
701 }
702};
blueswir19b649972008-12-30 19:01:19 +0000703
blueswir16e6b7362008-12-28 18:27:10 +0000704static void cuda_reset(void *opaque)
705{
706 CUDAState *s = opaque;
707
708 s->b = 0;
709 s->a = 0;
710 s->dirb = 0;
711 s->dira = 0;
712 s->sr = 0;
713 s->acr = 0;
714 s->pcr = 0;
715 s->ifr = 0;
716 s->ier = 0;
717 // s->ier = T1_INT | SR_INT;
718 s->anh = 0;
719 s->data_in_size = 0;
720 s->data_in_index = 0;
721 s->data_out_index = 0;
722 s->autopoll = 0;
723
724 s->timers[0].latch = 0xffff;
725 set_counter(s, &s->timers[0], 0xffff);
726
727 s->timers[1].latch = 0;
728 set_counter(s, &s->timers[1], 0xffff);
729}
730
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300731void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
bellard267002c2004-06-03 18:46:20 +0000732{
aurel325703c172009-01-15 18:57:15 +0000733 struct tm tm;
bellard267002c2004-06-03 18:46:20 +0000734 CUDAState *s = &cuda_state;
bellard267002c2004-06-03 18:46:20 +0000735
bellard819e7122004-06-21 16:47:13 +0000736 s->irq = irq;
737
bellard61271e52005-07-07 21:45:18 +0000738 s->timers[0].index = 0;
Paolo Bonzini74475452011-03-11 16:47:48 +0100739 s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
bellard61271e52005-07-07 21:45:18 +0000740
741 s->timers[1].index = 1;
bellarde2733d22004-06-21 22:46:10 +0000742
aurel329c554c12009-01-18 12:16:26 +0000743 qemu_get_timedate(&tm, 0);
744 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
aurel325703c172009-01-15 18:57:15 +0000745
Paolo Bonzini74475452011-03-11 16:47:48 +0100746 s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
Alexander Grafea0a7eb2011-09-08 18:51:17 +0200747 memory_region_init_io(&s->mem, &cuda_ops, s, "cuda", 0x2000);
748
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300749 *cuda_mem = &s->mem;
Juan Quintelac0a93a92010-12-02 13:53:24 +0100750 vmstate_register(NULL, -1, &vmstate_cuda, s);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200751 qemu_register_reset(cuda_reset, s);
bellard267002c2004-06-03 18:46:20 +0000752}