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aliguori244ab902009-02-05 21:23:50 +00001/*
2 * DMA helper functions
3 *
4 * Copyright (c) 2009 Red Hat
5 *
6 * This work is licensed under the terms of the GNU General Public License
7 * (GNU GPL), version 2 or later.
8 */
9
10#include "dma.h"
Kevin Wolfc57c4652011-11-24 06:15:28 -050011#include "trace.h"
David Gibsone5332e62012-06-27 14:50:43 +100012#include "range.h"
13#include "qemu-thread.h"
aliguori244ab902009-02-05 21:23:50 +000014
David Gibsone5332e62012-06-27 14:50:43 +100015/* #define DEBUG_IOMMU */
16
17static void do_dma_memory_set(dma_addr_t addr, uint8_t c, dma_addr_t len)
David Gibsond86a77f2012-06-27 14:50:38 +100018{
19#define FILLBUF_SIZE 512
20 uint8_t fillbuf[FILLBUF_SIZE];
21 int l;
22
23 memset(fillbuf, c, FILLBUF_SIZE);
24 while (len > 0) {
25 l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
26 cpu_physical_memory_rw(addr, fillbuf, l, true);
27 len -= len;
28 addr += len;
29 }
David Gibsone5332e62012-06-27 14:50:43 +100030}
31
32int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
33{
Benjamin Herrenschmidt7a0bac42012-06-27 14:50:47 +100034 dma_barrier(dma, DMA_DIRECTION_FROM_DEVICE);
35
David Gibsone5332e62012-06-27 14:50:43 +100036 if (dma_has_iommu(dma)) {
37 return iommu_dma_memory_set(dma, addr, c, len);
38 }
39 do_dma_memory_set(addr, c, len);
40
David Gibsond86a77f2012-06-27 14:50:38 +100041 return 0;
42}
43
David Gibsonc65bcef2012-06-27 14:50:40 +100044void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, DMAContext *dma)
aliguori244ab902009-02-05 21:23:50 +000045{
Anthony Liguori7267c092011-08-20 22:09:37 -050046 qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
aliguori244ab902009-02-05 21:23:50 +000047 qsg->nsg = 0;
48 qsg->nalloc = alloc_hint;
49 qsg->size = 0;
David Gibsonc65bcef2012-06-27 14:50:40 +100050 qsg->dma = dma;
aliguori244ab902009-02-05 21:23:50 +000051}
52
David Gibsond3231182011-10-31 17:06:46 +110053void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
aliguori244ab902009-02-05 21:23:50 +000054{
55 if (qsg->nsg == qsg->nalloc) {
56 qsg->nalloc = 2 * qsg->nalloc + 1;
Anthony Liguori7267c092011-08-20 22:09:37 -050057 qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
aliguori244ab902009-02-05 21:23:50 +000058 }
59 qsg->sg[qsg->nsg].base = base;
60 qsg->sg[qsg->nsg].len = len;
61 qsg->size += len;
62 ++qsg->nsg;
63}
64
65void qemu_sglist_destroy(QEMUSGList *qsg)
66{
Anthony Liguori7267c092011-08-20 22:09:37 -050067 g_free(qsg->sg);
aliguori244ab902009-02-05 21:23:50 +000068}
69
aliguori59a703e2009-02-05 21:23:58 +000070typedef struct {
aliguori37b78422009-03-20 18:26:16 +000071 BlockDriverAIOCB common;
aliguori59a703e2009-02-05 21:23:58 +000072 BlockDriverState *bs;
73 BlockDriverAIOCB *acb;
74 QEMUSGList *sg;
75 uint64_t sector_num;
David Gibson43cf8ae2012-03-27 13:42:23 +110076 DMADirection dir;
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +020077 bool in_cancel;
aliguori59a703e2009-02-05 21:23:58 +000078 int sg_cur_index;
David Gibsond3231182011-10-31 17:06:46 +110079 dma_addr_t sg_cur_byte;
aliguori59a703e2009-02-05 21:23:58 +000080 QEMUIOVector iov;
81 QEMUBH *bh;
Christoph Hellwigcb144cc2011-05-19 10:57:59 +020082 DMAIOFunc *io_func;
aliguori37b78422009-03-20 18:26:16 +000083} DMAAIOCB;
aliguori59a703e2009-02-05 21:23:58 +000084
85static void dma_bdrv_cb(void *opaque, int ret);
86
87static void reschedule_dma(void *opaque)
88{
aliguori37b78422009-03-20 18:26:16 +000089 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
aliguori59a703e2009-02-05 21:23:58 +000090
91 qemu_bh_delete(dbs->bh);
92 dbs->bh = NULL;
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +020093 dma_bdrv_cb(dbs, 0);
aliguori59a703e2009-02-05 21:23:58 +000094}
95
96static void continue_after_map_failure(void *opaque)
97{
aliguori37b78422009-03-20 18:26:16 +000098 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
aliguori59a703e2009-02-05 21:23:58 +000099
100 dbs->bh = qemu_bh_new(reschedule_dma, dbs);
101 qemu_bh_schedule(dbs->bh);
102}
103
aliguori7403b142009-03-28 16:11:25 +0000104static void dma_bdrv_unmap(DMAAIOCB *dbs)
aliguori59a703e2009-02-05 21:23:58 +0000105{
aliguori59a703e2009-02-05 21:23:58 +0000106 int i;
107
aliguori59a703e2009-02-05 21:23:58 +0000108 for (i = 0; i < dbs->iov.niov; ++i) {
David Gibsonc65bcef2012-06-27 14:50:40 +1000109 dma_memory_unmap(dbs->sg->dma, dbs->iov.iov[i].iov_base,
110 dbs->iov.iov[i].iov_len, dbs->dir,
111 dbs->iov.iov[i].iov_len);
aliguori59a703e2009-02-05 21:23:58 +0000112 }
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +0200113 qemu_iovec_reset(&dbs->iov);
114}
115
116static void dma_complete(DMAAIOCB *dbs, int ret)
117{
Kevin Wolfc57c4652011-11-24 06:15:28 -0500118 trace_dma_complete(dbs, ret, dbs->common.cb);
119
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +0200120 dma_bdrv_unmap(dbs);
121 if (dbs->common.cb) {
122 dbs->common.cb(dbs->common.opaque, ret);
123 }
124 qemu_iovec_destroy(&dbs->iov);
125 if (dbs->bh) {
126 qemu_bh_delete(dbs->bh);
127 dbs->bh = NULL;
128 }
129 if (!dbs->in_cancel) {
130 /* Requests may complete while dma_aio_cancel is in progress. In
131 * this case, the AIOCB should not be released because it is still
132 * referenced by dma_aio_cancel. */
133 qemu_aio_release(dbs);
134 }
aliguori7403b142009-03-28 16:11:25 +0000135}
136
blueswir1856ae5c2009-04-07 17:57:09 +0000137static void dma_bdrv_cb(void *opaque, int ret)
aliguori7403b142009-03-28 16:11:25 +0000138{
139 DMAAIOCB *dbs = (DMAAIOCB *)opaque;
David Gibsonc65bcef2012-06-27 14:50:40 +1000140 dma_addr_t cur_addr, cur_len;
aliguori7403b142009-03-28 16:11:25 +0000141 void *mem;
142
Kevin Wolfc57c4652011-11-24 06:15:28 -0500143 trace_dma_bdrv_cb(dbs, ret);
144
aliguori7403b142009-03-28 16:11:25 +0000145 dbs->acb = NULL;
146 dbs->sector_num += dbs->iov.size / 512;
147 dma_bdrv_unmap(dbs);
aliguori59a703e2009-02-05 21:23:58 +0000148
149 if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +0200150 dma_complete(dbs, ret);
aliguori59a703e2009-02-05 21:23:58 +0000151 return;
152 }
153
154 while (dbs->sg_cur_index < dbs->sg->nsg) {
155 cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
156 cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
David Gibsonc65bcef2012-06-27 14:50:40 +1000157 mem = dma_memory_map(dbs->sg->dma, cur_addr, &cur_len, dbs->dir);
aliguori59a703e2009-02-05 21:23:58 +0000158 if (!mem)
159 break;
160 qemu_iovec_add(&dbs->iov, mem, cur_len);
161 dbs->sg_cur_byte += cur_len;
162 if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
163 dbs->sg_cur_byte = 0;
164 ++dbs->sg_cur_index;
165 }
166 }
167
168 if (dbs->iov.size == 0) {
Kevin Wolfc57c4652011-11-24 06:15:28 -0500169 trace_dma_map_wait(dbs);
aliguori59a703e2009-02-05 21:23:58 +0000170 cpu_register_map_client(dbs, continue_after_map_failure);
171 return;
172 }
173
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200174 dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov,
175 dbs->iov.size / 512, dma_bdrv_cb, dbs);
Paolo Bonzini6bee44e2011-11-14 17:50:52 +0100176 assert(dbs->acb);
aliguori59a703e2009-02-05 21:23:58 +0000177}
178
Christoph Hellwigc16b5a22009-05-25 12:37:32 +0200179static void dma_aio_cancel(BlockDriverAIOCB *acb)
180{
181 DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
182
Kevin Wolfc57c4652011-11-24 06:15:28 -0500183 trace_dma_aio_cancel(dbs);
184
Christoph Hellwigc16b5a22009-05-25 12:37:32 +0200185 if (dbs->acb) {
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +0200186 BlockDriverAIOCB *acb = dbs->acb;
187 dbs->acb = NULL;
188 dbs->in_cancel = true;
189 bdrv_aio_cancel(acb);
190 dbs->in_cancel = false;
Christoph Hellwigc16b5a22009-05-25 12:37:32 +0200191 }
Paolo Bonzinic3adb5b2011-09-16 16:40:02 +0200192 dbs->common.cb = NULL;
193 dma_complete(dbs, 0);
Christoph Hellwigc16b5a22009-05-25 12:37:32 +0200194}
195
196static AIOPool dma_aio_pool = {
197 .aiocb_size = sizeof(DMAAIOCB),
198 .cancel = dma_aio_cancel,
199};
200
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200201BlockDriverAIOCB *dma_bdrv_io(
aliguori59a703e2009-02-05 21:23:58 +0000202 BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num,
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200203 DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
David Gibson43cf8ae2012-03-27 13:42:23 +1100204 void *opaque, DMADirection dir)
aliguori59a703e2009-02-05 21:23:58 +0000205{
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200206 DMAAIOCB *dbs = qemu_aio_get(&dma_aio_pool, bs, cb, opaque);
aliguori59a703e2009-02-05 21:23:58 +0000207
David Gibson43cf8ae2012-03-27 13:42:23 +1100208 trace_dma_bdrv_io(dbs, bs, sector_num, (dir == DMA_DIRECTION_TO_DEVICE));
Kevin Wolfc57c4652011-11-24 06:15:28 -0500209
aliguori37b78422009-03-20 18:26:16 +0000210 dbs->acb = NULL;
aliguori59a703e2009-02-05 21:23:58 +0000211 dbs->bs = bs;
aliguori59a703e2009-02-05 21:23:58 +0000212 dbs->sg = sg;
213 dbs->sector_num = sector_num;
214 dbs->sg_cur_index = 0;
215 dbs->sg_cur_byte = 0;
David Gibson43cf8ae2012-03-27 13:42:23 +1100216 dbs->dir = dir;
Christoph Hellwigcb144cc2011-05-19 10:57:59 +0200217 dbs->io_func = io_func;
aliguori59a703e2009-02-05 21:23:58 +0000218 dbs->bh = NULL;
219 qemu_iovec_init(&dbs->iov, sg->nsg);
220 dma_bdrv_cb(dbs, 0);
aliguori37b78422009-03-20 18:26:16 +0000221 return &dbs->common;
aliguori59a703e2009-02-05 21:23:58 +0000222}
223
224
225BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
226 QEMUSGList *sg, uint64_t sector,
227 void (*cb)(void *opaque, int ret), void *opaque)
228{
David Gibson43cf8ae2012-03-27 13:42:23 +1100229 return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque,
230 DMA_DIRECTION_FROM_DEVICE);
aliguori59a703e2009-02-05 21:23:58 +0000231}
232
233BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
234 QEMUSGList *sg, uint64_t sector,
235 void (*cb)(void *opaque, int ret), void *opaque)
236{
David Gibson43cf8ae2012-03-27 13:42:23 +1100237 return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque,
238 DMA_DIRECTION_TO_DEVICE);
aliguori59a703e2009-02-05 21:23:58 +0000239}
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200240
241
David Gibsonc65bcef2012-06-27 14:50:40 +1000242static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
243 DMADirection dir)
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200244{
245 uint64_t resid;
246 int sg_cur_index;
247
248 resid = sg->size;
249 sg_cur_index = 0;
250 len = MIN(len, resid);
251 while (len > 0) {
252 ScatterGatherEntry entry = sg->sg[sg_cur_index++];
253 int32_t xfer = MIN(len, entry.len);
David Gibsonc65bcef2012-06-27 14:50:40 +1000254 dma_memory_rw(sg->dma, entry.base, ptr, xfer, dir);
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200255 ptr += xfer;
256 len -= xfer;
257 resid -= xfer;
258 }
259
260 return resid;
261}
262
263uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
264{
David Gibsonc65bcef2012-06-27 14:50:40 +1000265 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200266}
267
268uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
269{
David Gibsonc65bcef2012-06-27 14:50:40 +1000270 return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
Paolo Bonzini8171ee32011-07-06 08:02:14 +0200271}
Paolo Bonzini84a69352011-09-05 14:20:29 +0200272
273void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
274 QEMUSGList *sg, enum BlockAcctType type)
275{
276 bdrv_acct_start(bs, cookie, sg->size, type);
277}
David Gibsone5332e62012-06-27 14:50:43 +1000278
279bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
280 DMADirection dir)
281{
282 target_phys_addr_t paddr, plen;
283
284#ifdef DEBUG_IOMMU
285 fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
286 " len=0x" DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
287#endif
288
289 while (len) {
290 if (dma->translate(dma, addr, &paddr, &plen, dir) != 0) {
291 return false;
292 }
293
294 /* The translation might be valid for larger regions. */
295 if (plen > len) {
296 plen = len;
297 }
298
299 len -= plen;
300 addr += plen;
301 }
302
303 return true;
304}
305
306int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
307 void *buf, dma_addr_t len, DMADirection dir)
308{
309 target_phys_addr_t paddr, plen;
310 int err;
311
312#ifdef DEBUG_IOMMU
313 fprintf(stderr, "dma_memory_rw context=%p addr=0x" DMA_ADDR_FMT " len=0x"
314 DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
315#endif
316
317 while (len) {
318 err = dma->translate(dma, addr, &paddr, &plen, dir);
319 if (err) {
320 /*
321 * In case of failure on reads from the guest, we clean the
322 * destination buffer so that a device that doesn't test
323 * for errors will not expose qemu internal memory.
324 */
325 memset(buf, 0, len);
326 return -1;
327 }
328
329 /* The translation might be valid for larger regions. */
330 if (plen > len) {
331 plen = len;
332 }
333
334 cpu_physical_memory_rw(paddr, buf, plen,
335 dir == DMA_DIRECTION_FROM_DEVICE);
336
337 len -= plen;
338 addr += plen;
339 buf += plen;
340 }
341
342 return 0;
343}
344
345int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
346 dma_addr_t len)
347{
348 target_phys_addr_t paddr, plen;
349 int err;
350
351#ifdef DEBUG_IOMMU
352 fprintf(stderr, "dma_memory_set context=%p addr=0x" DMA_ADDR_FMT
353 " len=0x" DMA_ADDR_FMT "\n", dma, addr, len);
354#endif
355
356 while (len) {
357 err = dma->translate(dma, addr, &paddr, &plen,
358 DMA_DIRECTION_FROM_DEVICE);
359 if (err) {
360 return err;
361 }
362
363 /* The translation might be valid for larger regions. */
364 if (plen > len) {
365 plen = len;
366 }
367
368 do_dma_memory_set(paddr, c, plen);
369
370 len -= plen;
371 addr += plen;
372 }
373
374 return 0;
375}
376
377void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
378 DMAMapFunc map, DMAUnmapFunc unmap)
379{
380#ifdef DEBUG_IOMMU
381 fprintf(stderr, "dma_context_init(%p, %p, %p, %p)\n",
382 dma, translate, map, unmap);
383#endif
384 dma->translate = translate;
385 dma->map = map;
386 dma->unmap = unmap;
387}
388
389void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len,
390 DMADirection dir)
391{
392 int err;
393 target_phys_addr_t paddr, plen;
394 void *buf;
395
396 if (dma->map) {
397 return dma->map(dma, addr, len, dir);
398 }
399
400 plen = *len;
401 err = dma->translate(dma, addr, &paddr, &plen, dir);
402 if (err) {
403 return NULL;
404 }
405
406 /*
407 * If this is true, the virtual region is contiguous,
408 * but the translated physical region isn't. We just
409 * clamp *len, much like cpu_physical_memory_map() does.
410 */
411 if (plen < *len) {
412 *len = plen;
413 }
414
415 buf = cpu_physical_memory_map(paddr, &plen,
416 dir == DMA_DIRECTION_FROM_DEVICE);
417 *len = plen;
418
419 return buf;
420}
421
422void iommu_dma_memory_unmap(DMAContext *dma, void *buffer, dma_addr_t len,
423 DMADirection dir, dma_addr_t access_len)
424{
425 if (dma->unmap) {
426 dma->unmap(dma, buffer, len, dir, access_len);
427 return;
428 }
429
430 cpu_physical_memory_unmap(buffer, len,
431 dir == DMA_DIRECTION_FROM_DEVICE,
432 access_len);
433
434}