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ths663e8e52007-04-02 12:35:34 +00001/*
2 * QEMU i8255x (PRO100) emulation
3 *
Stefan Weil1b4f97d2011-04-30 22:40:04 +02004 * Copyright (C) 2006-2011 Stefan Weil
ths663e8e52007-04-02 12:35:34 +00005 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
Stefan Weil230a1672010-03-02 22:37:47 +01009 * This program is free software: you can redistribute it and/or modify
ths663e8e52007-04-02 12:35:34 +000010 * it under the terms of the GNU General Public License as published by
Stefan Weil230a1672010-03-02 22:37:47 +010011 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
ths663e8e52007-04-02 12:35:34 +000013 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
Stefan Weil230a1672010-03-02 22:37:47 +010020 * along with this program. If not, see <http://www.gnu.org/licenses/>.
ths663e8e52007-04-02 12:35:34 +000021 *
22 * Tested features (i82559):
Stefan Weile5e23ab2011-04-30 22:40:08 +020023 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
ths663e8e52007-04-02 12:35:34 +000024 * Linux networking (i386) ok
25 *
26 * Untested:
ths663e8e52007-04-02 12:35:34 +000027 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
Stefan Weilba19f2d2010-03-02 22:37:46 +010033 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
ths663e8e52007-04-02 12:35:34 +000041 */
42
ths663e8e52007-04-02 12:35:34 +000043#include <stddef.h> /* offsetof */
pbrook87ecb682007-11-17 17:14:51 +000044#include "hw.h"
Michael S. Tsirkina2cb15b2012-12-12 14:24:50 +020045#include "pci/pci.h"
Paolo Bonzini1422e322012-10-24 08:43:34 +020046#include "net/net.h"
ths663e8e52007-04-02 12:35:34 +000047#include "eeprom93xx.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010048#include "sysemu/sysemu.h"
49#include "sysemu/dma.h"
ths663e8e52007-04-02 12:35:34 +000050
Stefan Weil792f1d62011-04-30 22:40:07 +020051/* QEMU sends frames smaller than 60 bytes to ethernet nics.
52 * Such frames are rejected by real nics and their emulations.
53 * To avoid this behaviour, other nic emulations pad received
54 * frames. The following definition enables this padding for
55 * eepro100, too. We keep the define around in case it might
56 * become useful the future if the core networking is ever
57 * changed to pad short packets itself. */
58#define CONFIG_PAD_RECEIVED_FRAMES
59
ths663e8e52007-04-02 12:35:34 +000060#define KiB 1024
61
Stefan Weilaac443e2009-09-19 12:11:36 +020062/* Debug EEPRO100 card. */
Stefan Weilce0e58b2010-03-02 22:37:41 +010063#if 0
64# define DEBUG_EEPRO100
65#endif
ths663e8e52007-04-02 12:35:34 +000066
67#ifdef DEBUG_EEPRO100
Blue Swirl001faf32009-05-13 17:53:17 +000068#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
ths663e8e52007-04-02 12:35:34 +000069#else
Blue Swirl001faf32009-05-13 17:53:17 +000070#define logout(fmt, ...) ((void)0)
ths663e8e52007-04-02 12:35:34 +000071#endif
72
73/* Set flags to 0 to disable debug output. */
Stefan Weilaac443e2009-09-19 12:11:36 +020074#define INT 1 /* interrupt related actions */
75#define MDI 1 /* mdi related actions */
76#define OTHER 1
77#define RXTX 1
78#define EEPROM 1 /* eeprom related actions */
ths663e8e52007-04-02 12:35:34 +000079
80#define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
Kevin Wolf7f1e9d42009-09-23 17:42:42 +020082#define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
ths663e8e52007-04-02 12:35:34 +000083
84#define MAX_ETH_FRAME_SIZE 1514
85
86/* This driver supports several different devices which are declared here. */
Stefan Weilc4c270e2009-09-19 13:02:09 +020087#define i82550 0x82550
ths663e8e52007-04-02 12:35:34 +000088#define i82551 0x82551
Stefan Weilc4c270e2009-09-19 13:02:09 +020089#define i82557A 0x82557a
ths663e8e52007-04-02 12:35:34 +000090#define i82557B 0x82557b
91#define i82557C 0x82557c
Stefan Weilc4c270e2009-09-19 13:02:09 +020092#define i82558A 0x82558a
ths663e8e52007-04-02 12:35:34 +000093#define i82558B 0x82558b
Stefan Weilc4c270e2009-09-19 13:02:09 +020094#define i82559A 0x82559a
95#define i82559B 0x82559b
ths663e8e52007-04-02 12:35:34 +000096#define i82559C 0x82559c
97#define i82559ER 0x82559e
98#define i82562 0x82562
Stefan Weildb667a12010-04-06 13:44:04 +020099#define i82801 0x82801
ths663e8e52007-04-02 12:35:34 +0000100
Stefan Weilaac443e2009-09-19 12:11:36 +0200101/* Use 64 word EEPROM. TODO: could be a runtime option. */
ths663e8e52007-04-02 12:35:34 +0000102#define EEPROM_SIZE 64
103
104#define PCI_MEM_SIZE (4 * KiB)
105#define PCI_IO_SIZE 64
106#define PCI_FLASH_SIZE (128 * KiB)
107
108#define BIT(n) (1 << (n))
109#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110
111/* The SCB accepts the following controls for the Tx and Rx units: */
112#define CU_NOP 0x0000 /* No operation. */
113#define CU_START 0x0010 /* CU start. */
114#define CU_RESUME 0x0020 /* CU resume. */
115#define CU_STATSADDR 0x0040 /* Load dump counters address. */
116#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
117#define CU_CMD_BASE 0x0060 /* Load CU base address. */
118#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
119#define CU_SRESUME 0x00a0 /* CU static resume. */
120
121#define RU_NOP 0x0000
122#define RX_START 0x0001
123#define RX_RESUME 0x0002
Stefan Weile8240122010-03-02 22:37:53 +0100124#define RU_ABORT 0x0004
ths663e8e52007-04-02 12:35:34 +0000125#define RX_ADDR_LOAD 0x0006
126#define RX_RESUMENR 0x0007
127#define INT_MASK 0x0100
128#define DRVR_INT 0x0200 /* Driver generated interrupt. */
129
Stefan Weil558c8632010-04-06 13:44:03 +0200130typedef struct {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600131 const char *name;
132 const char *desc;
Anthony Liguori40021f02011-12-04 12:22:06 -0600133 uint16_t device_id;
134 uint8_t revision;
135 uint16_t subsystem_vendor_id;
136 uint16_t subsystem_id;
137
Stefan Weil558c8632010-04-06 13:44:03 +0200138 uint32_t device;
Stefan Weil558c8632010-04-06 13:44:03 +0200139 uint8_t stats_size;
140 bool has_extended_tcb_support;
141 bool power_management;
142} E100PCIDeviceInfo;
143
ths663e8e52007-04-02 12:35:34 +0000144/* Offsets to the various registers.
145 All accesses need not be longword aligned. */
Stefan Weile5e23ab2011-04-30 22:40:08 +0200146typedef enum {
Stefan Weil0908bba2010-03-02 22:37:42 +0100147 SCBStatus = 0, /* Status Word. */
ths663e8e52007-04-02 12:35:34 +0000148 SCBAck = 1,
149 SCBCmd = 2, /* Rx/Command Unit command and status. */
150 SCBIntmask = 3,
151 SCBPointer = 4, /* General purpose pointer. */
152 SCBPort = 8, /* Misc. commands and operands. */
Stefan Weil0908bba2010-03-02 22:37:42 +0100153 SCBflash = 12, /* Flash memory control. */
154 SCBeeprom = 14, /* EEPROM control. */
ths663e8e52007-04-02 12:35:34 +0000155 SCBCtrlMDI = 16, /* MDI interface control. */
156 SCBEarlyRx = 20, /* Early receive byte count. */
Stefan Weil0908bba2010-03-02 22:37:42 +0100157 SCBFlow = 24, /* Flow Control. */
158 SCBpmdr = 27, /* Power Management Driver. */
159 SCBgctrl = 28, /* General Control. */
160 SCBgstat = 29, /* General Status. */
Stefan Weile5e23ab2011-04-30 22:40:08 +0200161} E100RegisterOffset;
ths663e8e52007-04-02 12:35:34 +0000162
163/* A speedo3 transmit buffer descriptor with two buffers... */
164typedef struct {
165 uint16_t status;
166 uint16_t command;
167 uint32_t link; /* void * */
Stefan Weil7b8737d2009-12-20 16:52:24 +0100168 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
ths663e8e52007-04-02 12:35:34 +0000169 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
170 uint8_t tx_threshold; /* transmit threshold */
171 uint8_t tbd_count; /* TBD number */
Stefan Weile7493b22010-03-02 22:37:59 +0100172#if 0
173 /* This constitutes two "TBD" entries: hdr and data */
174 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
175 int32_t tx_buf_size0; /* Length of Tx hdr. */
176 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
177 int32_t tx_buf_size1; /* Length of Tx data. */
178#endif
Anthony Liguoric227f092009-10-01 16:12:16 -0500179} eepro100_tx_t;
ths663e8e52007-04-02 12:35:34 +0000180
181/* Receive frame descriptor. */
182typedef struct {
183 int16_t status;
184 uint16_t command;
185 uint32_t link; /* struct RxFD * */
186 uint32_t rx_buf_addr; /* void * */
187 uint16_t count;
188 uint16_t size;
Stefan Weil27112f12011-04-30 22:40:06 +0200189 /* Ethernet frame data follows. */
Anthony Liguoric227f092009-10-01 16:12:16 -0500190} eepro100_rx_t;
ths663e8e52007-04-02 12:35:34 +0000191
Stefan Weilced52962010-03-02 22:37:49 +0100192typedef enum {
193 COMMAND_EL = BIT(15),
194 COMMAND_S = BIT(14),
195 COMMAND_I = BIT(13),
196 COMMAND_NC = BIT(4),
197 COMMAND_SF = BIT(3),
198 COMMAND_CMD = BITS(2, 0),
199} scb_command_bit;
200
201typedef enum {
202 STATUS_C = BIT(15),
203 STATUS_OK = BIT(13),
204} scb_status_bit;
205
ths663e8e52007-04-02 12:35:34 +0000206typedef struct {
207 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
Stefan Weilcc02c662010-03-02 22:37:55 +0100208 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
209 tx_multiple_collisions, tx_total_collisions;
ths663e8e52007-04-02 12:35:34 +0000210 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
Stefan Weilcc02c662010-03-02 22:37:55 +0100211 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
212 rx_short_frame_errors;
ths663e8e52007-04-02 12:35:34 +0000213 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
214 uint16_t xmt_tco_frames, rcv_tco_frames;
Stefan Weilba42b642009-10-30 13:36:21 +0100215 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
216 uint32_t reserved[4];
Anthony Liguoric227f092009-10-01 16:12:16 -0500217} eepro100_stats_t;
ths663e8e52007-04-02 12:35:34 +0000218
219typedef enum {
220 cu_idle = 0,
221 cu_suspended = 1,
222 cu_active = 2,
223 cu_lpq_active = 2,
224 cu_hqp_active = 3
Anthony Liguoric227f092009-10-01 16:12:16 -0500225} cu_state_t;
ths663e8e52007-04-02 12:35:34 +0000226
227typedef enum {
228 ru_idle = 0,
229 ru_suspended = 1,
230 ru_no_resources = 2,
231 ru_ready = 4
Anthony Liguoric227f092009-10-01 16:12:16 -0500232} ru_state_t;
ths663e8e52007-04-02 12:35:34 +0000233
ths663e8e52007-04-02 12:35:34 +0000234typedef struct {
Juan Quintela273a2142009-08-24 18:42:37 +0200235 PCIDevice dev;
Stefan Weil010ec622010-09-29 21:59:55 +0200236 /* Hash register (multicast mask array, multiple individual addresses). */
237 uint8_t mult[8];
Avi Kivity5e6ffdd2011-08-08 16:09:09 +0300238 MemoryRegion mmio_bar;
239 MemoryRegion io_bar;
240 MemoryRegion flash_bar;
Mark McLoughline00e3652009-11-25 18:49:16 +0000241 NICState *nic;
Gerd Hoffmann508ef932009-10-21 15:25:36 +0200242 NICConf conf;
ths663e8e52007-04-02 12:35:34 +0000243 uint8_t scb_stat; /* SCB stat/ack byte */
244 uint8_t int_stat; /* PCI interrupt status */
Stefan Weil3706c432009-10-09 19:49:58 +0200245 /* region must not be saved by nic_save. */
ths663e8e52007-04-02 12:35:34 +0000246 uint16_t mdimem[32];
Anthony Liguoric227f092009-10-01 16:12:16 -0500247 eeprom_t *eeprom;
ths663e8e52007-04-02 12:35:34 +0000248 uint32_t device; /* device variant */
ths663e8e52007-04-02 12:35:34 +0000249 /* (cu_base + cu_offset) address the next command block in the command block list. */
250 uint32_t cu_base; /* CU base address */
251 uint32_t cu_offset; /* CU address offset */
252 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
253 uint32_t ru_base; /* RU base address */
254 uint32_t ru_offset; /* RU address offset */
Anthony Liguoric227f092009-10-01 16:12:16 -0500255 uint32_t statsaddr; /* pointer to eepro100_stats_t */
Stefan Weilba42b642009-10-30 13:36:21 +0100256
Stefan Weilf3a52e52009-12-20 16:52:22 +0100257 /* Temporary status information (no need to save these values),
258 * used while processing CU commands. */
259 eepro100_tx_t tx; /* transmit buffer descriptor */
260 uint32_t cb_address; /* = cu_base + cu_offset */
261
Stefan Weilba42b642009-10-30 13:36:21 +0100262 /* Statistical counters. Also used for wake-up packet (i82559). */
263 eepro100_stats_t statistics;
264
Stefan Weile5e23ab2011-04-30 22:40:08 +0200265 /* Data in mem is always in the byte order of the controller (le).
266 * It must be dword aligned to allow direct access to 32 bit values. */
Dong Xu Wang3a931132011-11-29 16:52:38 +0800267 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
Stefan Weile5e23ab2011-04-30 22:40:08 +0200268
ths663e8e52007-04-02 12:35:34 +0000269 /* Configuration bytes. */
270 uint8_t configuration[22];
271
Juan Quintela151b2982009-10-19 15:37:57 +0200272 /* vmstate for each particular nic */
273 VMStateDescription *vmstate;
Stefan Weilba42b642009-10-30 13:36:21 +0100274
275 /* Quasi static device properties (no need to save them). */
276 uint16_t stats_size;
277 bool has_extended_tcb_support;
ths663e8e52007-04-02 12:35:34 +0000278} EEPRO100State;
279
Stefan Weil6cded3a2010-03-02 22:37:43 +0100280/* Word indices in EEPROM. */
281typedef enum {
282 EEPROM_CNFG_MDIX = 0x03,
283 EEPROM_ID = 0x05,
284 EEPROM_PHY_ID = 0x06,
285 EEPROM_VENDOR_ID = 0x0c,
286 EEPROM_CONFIG_ASF = 0x0d,
287 EEPROM_DEVICE_ID = 0x23,
288 EEPROM_SMBUS_ADDR = 0x90,
289} EEPROMOffset;
290
Stefan Weilb1e87012010-03-02 22:37:51 +0100291/* Bit values for EEPROM ID word. */
292typedef enum {
293 EEPROM_ID_MDM = BIT(0), /* Modem */
294 EEPROM_ID_STB = BIT(1), /* Standby Enable */
295 EEPROM_ID_WMR = BIT(2), /* ??? */
296 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
297 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
298 EEPROM_ID_ALT = BIT(7), /* */
299 /* BITS(10, 8) device revision */
300 EEPROM_ID_BD = BIT(11), /* boot disable */
301 EEPROM_ID_ID = BIT(13), /* id bit */
302 /* BITS(15, 14) signature */
303 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
304} eeprom_id_bit;
305
ths663e8e52007-04-02 12:35:34 +0000306/* Default values for MDI (PHY) registers */
307static const uint16_t eepro100_mdi_default[] = {
308 /* MDI Registers 0 - 6, 7 */
309 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
310 /* MDI Registers 8 - 15 */
311 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
312 /* MDI Registers 16 - 31 */
313 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315};
316
317/* Readonly mask for MDI (PHY) registers */
318static const uint16_t eepro100_mdi_mask[] = {
319 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
322 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323};
324
Stefan Weil69f3ce72012-04-10 20:48:54 +0200325#define POLYNOMIAL 0x04c11db6
326
Anthony Liguori40021f02011-12-04 12:22:06 -0600327static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
328
Stefan Weil69f3ce72012-04-10 20:48:54 +0200329/* From FreeBSD (locally modified). */
330static unsigned e100_compute_mcast_idx(const uint8_t *ep)
331{
332 uint32_t crc;
333 int carry, i, j;
334 uint8_t b;
335
336 crc = 0xffffffff;
337 for (i = 0; i < 6; i++) {
338 b = *ep++;
339 for (j = 0; j < 8; j++) {
340 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
341 crc <<= 1;
342 b >>= 1;
343 if (carry) {
344 crc = ((crc ^ POLYNOMIAL) | carry);
345 }
346 }
347 }
348 return (crc & BITS(7, 2)) >> 2;
349}
350
Stefan Weile5e23ab2011-04-30 22:40:08 +0200351/* Read a 16 bit control/status (CSR) register. */
352static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
353{
354 assert(!((uintptr_t)&s->mem[addr] & 1));
355 return le16_to_cpup((uint16_t *)&s->mem[addr]);
356}
357
358/* Read a 32 bit control/status (CSR) register. */
359static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
360{
361 assert(!((uintptr_t)&s->mem[addr] & 3));
362 return le32_to_cpup((uint32_t *)&s->mem[addr]);
363}
364
365/* Write a 16 bit control/status (CSR) register. */
366static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
367 uint16_t val)
368{
369 assert(!((uintptr_t)&s->mem[addr] & 1));
370 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
371}
372
373/* Read a 32 bit control/status (CSR) register. */
374static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
375 uint32_t val)
376{
377 assert(!((uintptr_t)&s->mem[addr] & 3));
378 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
379}
380
ths663e8e52007-04-02 12:35:34 +0000381#if defined(DEBUG_EEPRO100)
382static const char *nic_dump(const uint8_t * buf, unsigned size)
383{
384 static char dump[3 * 16 + 1];
385 char *p = &dump[0];
Stefan Weilaac443e2009-09-19 12:11:36 +0200386 if (size > 16) {
ths663e8e52007-04-02 12:35:34 +0000387 size = 16;
Stefan Weilaac443e2009-09-19 12:11:36 +0200388 }
ths663e8e52007-04-02 12:35:34 +0000389 while (size-- > 0) {
390 p += sprintf(p, " %02x", *buf++);
391 }
392 return dump;
393}
394#endif /* DEBUG_EEPRO100 */
395
396enum scb_stat_ack {
397 stat_ack_not_ours = 0x00,
398 stat_ack_sw_gen = 0x04,
399 stat_ack_rnr = 0x10,
400 stat_ack_cu_idle = 0x20,
401 stat_ack_frame_rx = 0x40,
402 stat_ack_cu_cmd_done = 0x80,
403 stat_ack_not_present = 0xFF,
404 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
405 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
406};
407
408static void disable_interrupt(EEPRO100State * s)
409{
410 if (s->int_stat) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200411 TRACE(INT, logout("interrupt disabled\n"));
Juan Quintela273a2142009-08-24 18:42:37 +0200412 qemu_irq_lower(s->dev.irq[0]);
ths663e8e52007-04-02 12:35:34 +0000413 s->int_stat = 0;
414 }
415}
416
417static void enable_interrupt(EEPRO100State * s)
418{
419 if (!s->int_stat) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200420 TRACE(INT, logout("interrupt enabled\n"));
Juan Quintela273a2142009-08-24 18:42:37 +0200421 qemu_irq_raise(s->dev.irq[0]);
ths663e8e52007-04-02 12:35:34 +0000422 s->int_stat = 1;
423 }
424}
425
426static void eepro100_acknowledge(EEPRO100State * s)
427{
428 s->scb_stat &= ~s->mem[SCBAck];
429 s->mem[SCBAck] = s->scb_stat;
430 if (s->scb_stat == 0) {
431 disable_interrupt(s);
432 }
433}
434
Stefan Weile715c8e2010-03-02 22:37:52 +0100435static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
ths663e8e52007-04-02 12:35:34 +0000436{
437 uint8_t mask = ~s->mem[SCBIntmask];
Stefan Weile715c8e2010-03-02 22:37:52 +0100438 s->mem[SCBAck] |= status;
439 status = s->scb_stat = s->mem[SCBAck];
440 status &= (mask | 0x0f);
Stefan Weile7493b22010-03-02 22:37:59 +0100441#if 0
442 status &= (~s->mem[SCBIntmask] | 0x0xf);
443#endif
Stefan Weile715c8e2010-03-02 22:37:52 +0100444 if (status && (mask & 0x01)) {
ths663e8e52007-04-02 12:35:34 +0000445 /* SCB mask and SCB Bit M do not disable interrupt. */
446 enable_interrupt(s);
447 } else if (s->int_stat) {
448 disable_interrupt(s);
449 }
450}
451
452static void eepro100_cx_interrupt(EEPRO100State * s)
453{
454 /* CU completed action command. */
455 /* Transmit not ok (82557 only, not in emulation). */
456 eepro100_interrupt(s, 0x80);
457}
458
459static void eepro100_cna_interrupt(EEPRO100State * s)
460{
461 /* CU left the active state. */
462 eepro100_interrupt(s, 0x20);
463}
464
465static void eepro100_fr_interrupt(EEPRO100State * s)
466{
467 /* RU received a complete frame. */
468 eepro100_interrupt(s, 0x40);
469}
470
ths663e8e52007-04-02 12:35:34 +0000471static void eepro100_rnr_interrupt(EEPRO100State * s)
472{
473 /* RU is not ready. */
474 eepro100_interrupt(s, 0x10);
475}
ths663e8e52007-04-02 12:35:34 +0000476
477static void eepro100_mdi_interrupt(EEPRO100State * s)
478{
479 /* MDI completed read or write cycle. */
480 eepro100_interrupt(s, 0x08);
481}
482
483static void eepro100_swi_interrupt(EEPRO100State * s)
484{
485 /* Software has requested an interrupt. */
486 eepro100_interrupt(s, 0x04);
487}
488
489#if 0
490static void eepro100_fcp_interrupt(EEPRO100State * s)
491{
492 /* Flow control pause interrupt (82558 and later). */
493 eepro100_interrupt(s, 0x01);
494}
495#endif
496
Anthony Liguori40021f02011-12-04 12:22:06 -0600497static void e100_pci_reset(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000498{
Anthony Liguori40021f02011-12-04 12:22:06 -0600499 E100PCIDeviceInfo *info = eepro100_get_class(s);
ths663e8e52007-04-02 12:35:34 +0000500 uint32_t device = s->device;
Juan Quintela273a2142009-08-24 18:42:37 +0200501 uint8_t *pci_conf = s->dev.config;
ths663e8e52007-04-02 12:35:34 +0000502
Stefan Weilaac443e2009-09-19 12:11:36 +0200503 TRACE(OTHER, logout("%p\n", s));
ths663e8e52007-04-02 12:35:34 +0000504
ths663e8e52007-04-02 12:35:34 +0000505 /* PCI Status */
Stefan Weilae543b42010-04-06 13:44:07 +0200506 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
507 PCI_STATUS_FAST_BACK);
ths663e8e52007-04-02 12:35:34 +0000508 /* PCI Latency Timer */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200509 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
Stefan Weilae543b42010-04-06 13:44:07 +0200510 /* Capability Pointer is set by PCI framework. */
Stefan Weilf62719c2010-04-06 13:44:09 +0200511 /* Interrupt Line */
512 /* Interrupt Pin */
513 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
ths663e8e52007-04-02 12:35:34 +0000514 /* Minimum Grant */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200515 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
ths663e8e52007-04-02 12:35:34 +0000516 /* Maximum Latency */
Michael S. Tsirkin15e89f52010-03-03 14:00:21 +0200517 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
ths663e8e52007-04-02 12:35:34 +0000518
Anthony Liguori40021f02011-12-04 12:22:06 -0600519 s->stats_size = info->stats_size;
520 s->has_extended_tcb_support = info->has_extended_tcb_support;
Stefan Weil558c8632010-04-06 13:44:03 +0200521
ths663e8e52007-04-02 12:35:34 +0000522 switch (device) {
Stefan Weilba42b642009-10-30 13:36:21 +0100523 case i82550:
ths663e8e52007-04-02 12:35:34 +0000524 case i82551:
Stefan Weilba42b642009-10-30 13:36:21 +0100525 case i82557A:
ths663e8e52007-04-02 12:35:34 +0000526 case i82557B:
ths663e8e52007-04-02 12:35:34 +0000527 case i82557C:
Stefan Weilba42b642009-10-30 13:36:21 +0100528 case i82558A:
ths663e8e52007-04-02 12:35:34 +0000529 case i82558B:
Stefan Weilba42b642009-10-30 13:36:21 +0100530 case i82559A:
Stefan Weilba42b642009-10-30 13:36:21 +0100531 case i82559B:
Stefan Weil558c8632010-04-06 13:44:03 +0200532 case i82559ER:
533 case i82562:
Stefan Weildb667a12010-04-06 13:44:04 +0200534 case i82801:
ths663e8e52007-04-02 12:35:34 +0000535 case i82559C:
Stefan Weilba42b642009-10-30 13:36:21 +0100536 break;
ths663e8e52007-04-02 12:35:34 +0000537 default:
538 logout("Device %X is undefined!\n", device);
539 }
540
Stefan Weil3dec59a2010-04-06 13:44:05 +0200541 /* Standard TxCB. */
542 s->configuration[6] |= BIT(4);
543
Stefan Weil558c8632010-04-06 13:44:03 +0200544 /* Standard statistical counters. */
Stefan Weilba42b642009-10-30 13:36:21 +0100545 s->configuration[6] |= BIT(5);
546
547 if (s->stats_size == 80) {
548 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
549 if (s->configuration[6] & BIT(2)) {
550 /* TCO statistical counters. */
551 assert(s->configuration[6] & BIT(5));
552 } else {
553 if (s->configuration[6] & BIT(5)) {
554 /* No extended statistical counters, i82557 compatible. */
555 s->stats_size = 64;
556 } else {
557 /* i82558 compatible. */
558 s->stats_size = 76;
559 }
560 }
561 } else {
562 if (s->configuration[6] & BIT(5)) {
563 /* No extended statistical counters. */
564 s->stats_size = 64;
565 }
566 }
567 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
568
Anthony Liguori40021f02011-12-04 12:22:06 -0600569 if (info->power_management) {
Stefan Weilba42b642009-10-30 13:36:21 +0100570 /* Power Management Capabilities */
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300571 int cfg_offset = 0xdc;
Isaku Yamahataca770892010-09-06 16:46:16 +0900572 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
573 cfg_offset, PCI_PM_SIZEOF);
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300574 assert(r >= 0);
575 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
Stefan Weilae543b42010-04-06 13:44:07 +0200576#if 0 /* TODO: replace dummy code for power management emulation. */
Michael S. Tsirkin8bbd1ce2010-04-07 10:55:47 +0300577 /* TODO: Power Management Control / Status. */
578 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
579 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
580 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
Stefan Weilae543b42010-04-06 13:44:07 +0200581#endif
Stefan Weilba42b642009-10-30 13:36:21 +0100582 }
583
584#if EEPROM_SIZE > 0
ths663e8e52007-04-02 12:35:34 +0000585 if (device == i82557C || device == i82558B || device == i82559C) {
Stefan Weile7493b22010-03-02 22:37:59 +0100586 /*
587 TODO: get vendor id from EEPROM for i82557C or later.
588 TODO: get device id from EEPROM for i82557C or later.
589 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
590 TODO: header type is determined by EEPROM for i82559.
591 TODO: get subsystem id from EEPROM for i82557C or later.
592 TODO: get subsystem vendor id from EEPROM for i82557C or later.
593 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
594 TODO: capability pointer depends on EEPROM for i82558.
595 */
ths663e8e52007-04-02 12:35:34 +0000596 logout("Get device id and revision from EEPROM!!!\n");
597 }
Stefan Weilba42b642009-10-30 13:36:21 +0100598#endif /* EEPROM_SIZE > 0 */
ths663e8e52007-04-02 12:35:34 +0000599}
600
601static void nic_selective_reset(EEPRO100State * s)
602{
603 size_t i;
604 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
Stefan Weile7493b22010-03-02 22:37:59 +0100605#if 0
606 eeprom93xx_reset(s->eeprom);
607#endif
Gerd Hoffmann508ef932009-10-21 15:25:36 +0200608 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
Stefan Weilb1e87012010-03-02 22:37:51 +0100609 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
=?UTF-8?q?Reimar=20D=C3=B6ffinger?=f4e94df2009-09-12 15:42:01 +0200610 if (s->device == i82557B || s->device == i82557C)
611 eeprom_contents[5] = 0x0100;
Stefan Weil6cded3a2010-03-02 22:37:43 +0100612 eeprom_contents[EEPROM_PHY_ID] = 1;
ths663e8e52007-04-02 12:35:34 +0000613 uint16_t sum = 0;
614 for (i = 0; i < EEPROM_SIZE - 1; i++) {
615 sum += eeprom_contents[i];
616 }
617 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
Stefan Weilaac443e2009-09-19 12:11:36 +0200618 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
ths663e8e52007-04-02 12:35:34 +0000619
620 memset(s->mem, 0, sizeof(s->mem));
Stefan Weile5e23ab2011-04-30 22:40:08 +0200621 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
ths663e8e52007-04-02 12:35:34 +0000622
623 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
624 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
625}
626
627static void nic_reset(void *opaque)
628{
Juan Quintela769cf7a2009-08-24 18:42:36 +0200629 EEPRO100State *s = opaque;
Stefan Weilaac443e2009-09-19 12:11:36 +0200630 TRACE(OTHER, logout("%p\n", s));
Stefan Weil010ec622010-09-29 21:59:55 +0200631 /* TODO: Clearing of hash register for selective reset, too? */
Stefan Weil7b8737d2009-12-20 16:52:24 +0100632 memset(&s->mult[0], 0, sizeof(s->mult));
ths663e8e52007-04-02 12:35:34 +0000633 nic_selective_reset(s);
634}
635
636#if defined(DEBUG_EEPRO100)
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100637static const char * const e100_reg[PCI_IO_SIZE / 4] = {
ths663e8e52007-04-02 12:35:34 +0000638 "Command/Status",
639 "General Pointer",
640 "Port",
641 "EEPROM/Flash Control",
642 "MDI Control",
643 "Receive DMA Byte Count",
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100644 "Flow Control",
ths663e8e52007-04-02 12:35:34 +0000645 "General Status/Control"
646};
647
648static char *regname(uint32_t addr)
649{
David Benjaminec169282009-11-25 21:20:10 -0500650 static char buf[32];
ths663e8e52007-04-02 12:35:34 +0000651 if (addr < PCI_IO_SIZE) {
Stefan Weilb8f6ba02009-11-27 12:06:02 +0100652 const char *r = e100_reg[addr / 4];
ths663e8e52007-04-02 12:35:34 +0000653 if (r != 0) {
Stefan Weil41cbc232009-09-19 12:29:59 +0200654 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
ths663e8e52007-04-02 12:35:34 +0000655 } else {
Stefan Weil41cbc232009-09-19 12:29:59 +0200656 snprintf(buf, sizeof(buf), "0x%02x", addr);
ths663e8e52007-04-02 12:35:34 +0000657 }
658 } else {
Stefan Weil41cbc232009-09-19 12:29:59 +0200659 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
ths663e8e52007-04-02 12:35:34 +0000660 }
661 return buf;
662}
663#endif /* DEBUG_EEPRO100 */
664
ths663e8e52007-04-02 12:35:34 +0000665/*****************************************************************************
666 *
667 * Command emulation.
668 *
669 ****************************************************************************/
670
671#if 0
672static uint16_t eepro100_read_command(EEPRO100State * s)
673{
674 uint16_t val = 0xffff;
Stefan Weile7493b22010-03-02 22:37:59 +0100675 TRACE(OTHER, logout("val=0x%04x\n", val));
ths663e8e52007-04-02 12:35:34 +0000676 return val;
677}
678#endif
679
680/* Commands that can be put in a command list entry. */
681enum commands {
682 CmdNOp = 0,
683 CmdIASetup = 1,
684 CmdConfigure = 2,
685 CmdMulticastList = 3,
686 CmdTx = 4,
687 CmdTDR = 5, /* load microcode */
688 CmdDump = 6,
689 CmdDiagnose = 7,
690
691 /* And some extra flags: */
692 CmdSuspend = 0x4000, /* Suspend after completion. */
693 CmdIntr = 0x2000, /* Interrupt after completion. */
694 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
695};
696
Anthony Liguoric227f092009-10-01 16:12:16 -0500697static cu_state_t get_cu_state(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000698{
Stefan Weilced52962010-03-02 22:37:49 +0100699 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
ths663e8e52007-04-02 12:35:34 +0000700}
701
Anthony Liguoric227f092009-10-01 16:12:16 -0500702static void set_cu_state(EEPRO100State * s, cu_state_t state)
ths663e8e52007-04-02 12:35:34 +0000703{
Stefan Weilced52962010-03-02 22:37:49 +0100704 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
ths663e8e52007-04-02 12:35:34 +0000705}
706
Anthony Liguoric227f092009-10-01 16:12:16 -0500707static ru_state_t get_ru_state(EEPRO100State * s)
ths663e8e52007-04-02 12:35:34 +0000708{
Stefan Weilced52962010-03-02 22:37:49 +0100709 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
ths663e8e52007-04-02 12:35:34 +0000710}
711
Anthony Liguoric227f092009-10-01 16:12:16 -0500712static void set_ru_state(EEPRO100State * s, ru_state_t state)
ths663e8e52007-04-02 12:35:34 +0000713{
Stefan Weilced52962010-03-02 22:37:49 +0100714 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
ths663e8e52007-04-02 12:35:34 +0000715}
716
717static void dump_statistics(EEPRO100State * s)
718{
719 /* Dump statistical data. Most data is never changed by the emulation
720 * and always 0, so we first just copy the whole block and then those
721 * values which really matter.
722 * Number of data should check configuration!!!
723 */
David Gibsone965d4b2011-11-04 12:03:32 +1100724 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100725 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
726 s->statistics.tx_good_frames);
727 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
728 s->statistics.rx_good_frames);
729 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
730 s->statistics.rx_resource_errors);
731 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
732 s->statistics.rx_short_frame_errors);
Stefan Weile7493b22010-03-02 22:37:59 +0100733#if 0
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100734 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
735 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
Stefan Weile7493b22010-03-02 22:37:59 +0100736 missing("CU dump statistical counters");
737#endif
ths663e8e52007-04-02 12:35:34 +0000738}
739
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100740static void read_cb(EEPRO100State *s)
741{
David Gibsone965d4b2011-11-04 12:03:32 +1100742 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100743 s->tx.status = le16_to_cpu(s->tx.status);
744 s->tx.command = le16_to_cpu(s->tx.command);
745 s->tx.link = le32_to_cpu(s->tx.link);
746 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
747 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
748}
749
Stefan Weilf3a52e52009-12-20 16:52:22 +0100750static void tx_command(EEPRO100State *s)
751{
Stefan Weil7b8737d2009-12-20 16:52:24 +0100752 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100753 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
754 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
755 uint8_t buf[2600];
756 uint16_t size = 0;
757 uint32_t tbd_address = s->cb_address + 0x10;
758 TRACE(RXTX, logout
759 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
760 tbd_array, tcb_bytes, s->tx.tbd_count));
761
762 if (tcb_bytes > 2600) {
763 logout("TCB byte count too large, using 2600\n");
764 tcb_bytes = 2600;
765 }
766 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
767 logout
768 ("illegal values of TBD array address and TCB byte count!\n");
769 }
770 assert(tcb_bytes <= sizeof(buf));
771 while (size < tcb_bytes) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100772 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
773 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
Stefan Weile7493b22010-03-02 22:37:59 +0100774#if 0
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100775 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
Stefan Weile7493b22010-03-02 22:37:59 +0100776#endif
Stefan Weilf3a52e52009-12-20 16:52:22 +0100777 tbd_address += 8;
778 TRACE(RXTX, logout
779 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
780 tx_buffer_address, tx_buffer_size));
781 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100782 pci_dma_read(&s->dev, tx_buffer_address, &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100783 size += tx_buffer_size;
784 }
785 if (tbd_array == 0xffffffff) {
786 /* Simplified mode. Was already handled by code above. */
787 } else {
788 /* Flexible mode. */
789 uint8_t tbd_count = 0;
790 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
791 /* Extended Flexible TCB. */
792 for (; tbd_count < 2; tbd_count++) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100793 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
794 tbd_address);
795 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
796 tbd_address + 4);
797 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
798 tbd_address + 6);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100799 tbd_address += 8;
800 TRACE(RXTX, logout
801 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
802 tx_buffer_address, tx_buffer_size));
803 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100804 pci_dma_read(&s->dev, tx_buffer_address,
805 &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100806 size += tx_buffer_size;
807 if (tx_buffer_el & 1) {
808 break;
809 }
810 }
811 }
812 tbd_address = tbd_array;
813 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100814 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
815 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
816 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100817 tbd_address += 8;
818 TRACE(RXTX, logout
819 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
820 tx_buffer_address, tx_buffer_size));
821 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100822 pci_dma_read(&s->dev, tx_buffer_address,
823 &buf[size], tx_buffer_size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100824 size += tx_buffer_size;
825 if (tx_buffer_el & 1) {
826 break;
827 }
828 }
829 }
830 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
Jason Wangb356f762013-01-30 19:12:22 +0800831 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
Stefan Weilf3a52e52009-12-20 16:52:22 +0100832 s->statistics.tx_good_frames++;
833 /* Transmit with bad status would raise an CX/TNO interrupt.
834 * (82557 only). Emulation never has bad status. */
Stefan Weile7493b22010-03-02 22:37:59 +0100835#if 0
836 eepro100_cx_interrupt(s);
837#endif
Stefan Weilf3a52e52009-12-20 16:52:22 +0100838}
839
Stefan Weil7b8737d2009-12-20 16:52:24 +0100840static void set_multicast_list(EEPRO100State *s)
841{
842 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
843 uint16_t i;
844 memset(&s->mult[0], 0, sizeof(s->mult));
845 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
846 for (i = 0; i < multicast_count; i += 6) {
847 uint8_t multicast_addr[6];
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100848 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
Stefan Weil7b8737d2009-12-20 16:52:24 +0100849 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
Stefan Weil69f3ce72012-04-10 20:48:54 +0200850 unsigned mcast_idx = e100_compute_mcast_idx(multicast_addr);
Stefan Weil7b8737d2009-12-20 16:52:24 +0100851 assert(mcast_idx < 64);
852 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
853 }
854}
855
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200856static void action_command(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +0000857{
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200858 for (;;) {
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100859 bool bit_el;
860 bool bit_s;
861 bool bit_i;
862 bool bit_nc;
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200863 uint16_t ok_status = STATUS_OK;
Stefan Weil3d0f4b92010-03-02 22:37:57 +0100864 s->cb_address = s->cu_base + s->cu_offset;
865 read_cb(s);
866 bit_el = ((s->tx.command & COMMAND_EL) != 0);
867 bit_s = ((s->tx.command & COMMAND_S) != 0);
868 bit_i = ((s->tx.command & COMMAND_I) != 0);
869 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
870#if 0
871 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
872#endif
873 s->cu_offset = s->tx.link;
874 TRACE(OTHER,
875 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
876 s->tx.status, s->tx.command, s->tx.link));
877 switch (s->tx.command & COMMAND_CMD) {
ths663e8e52007-04-02 12:35:34 +0000878 case CmdNOp:
879 /* Do nothing. */
880 break;
881 case CmdIASetup:
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100882 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
Stefan Weilce0e58b2010-03-02 22:37:41 +0100883 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
ths663e8e52007-04-02 12:35:34 +0000884 break;
885 case CmdConfigure:
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100886 pci_dma_read(&s->dev, s->cb_address + 8,
887 &s->configuration[0], sizeof(s->configuration));
Stefan Weil010ec622010-09-29 21:59:55 +0200888 TRACE(OTHER, logout("configuration: %s\n",
889 nic_dump(&s->configuration[0], 16)));
890 TRACE(OTHER, logout("configuration: %s\n",
891 nic_dump(&s->configuration[16],
892 ARRAY_SIZE(s->configuration) - 16)));
893 if (s->configuration[20] & BIT(6)) {
894 TRACE(OTHER, logout("Multiple IA bit\n"));
895 }
ths663e8e52007-04-02 12:35:34 +0000896 break;
897 case CmdMulticastList:
Stefan Weil7b8737d2009-12-20 16:52:24 +0100898 set_multicast_list(s);
ths663e8e52007-04-02 12:35:34 +0000899 break;
900 case CmdTx:
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200901 if (bit_nc) {
902 missing("CmdTx: NC = 0");
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200903 ok_status = 0;
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200904 break;
905 }
Stefan Weilf3a52e52009-12-20 16:52:22 +0100906 tx_command(s);
ths663e8e52007-04-02 12:35:34 +0000907 break;
908 case CmdTDR:
Stefan Weilaac443e2009-09-19 12:11:36 +0200909 TRACE(OTHER, logout("load microcode\n"));
ths663e8e52007-04-02 12:35:34 +0000910 /* Starting with offset 8, the command contains
911 * 64 dwords microcode which we just ignore here. */
912 break;
Stefan Weilf80a7fc2010-03-02 22:37:58 +0100913 case CmdDiagnose:
914 TRACE(OTHER, logout("diagnose\n"));
915 /* Make sure error flag is not set. */
916 s->tx.status = 0;
917 break;
ths663e8e52007-04-02 12:35:34 +0000918 default:
919 missing("undefined command");
Stefan Weil75f5a6c2010-04-06 13:44:02 +0200920 ok_status = 0;
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200921 break;
ths663e8e52007-04-02 12:35:34 +0000922 }
Kevin Wolf7f1e9d42009-09-23 17:42:42 +0200923 /* Write new status. */
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +1100924 stw_le_pci_dma(&s->dev, s->cb_address,
925 s->tx.status | ok_status | STATUS_C);
ths663e8e52007-04-02 12:35:34 +0000926 if (bit_i) {
927 /* CU completed action. */
928 eepro100_cx_interrupt(s);
929 }
930 if (bit_el) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200931 /* CU becomes idle. Terminate command loop. */
ths663e8e52007-04-02 12:35:34 +0000932 set_cu_state(s, cu_idle);
933 eepro100_cna_interrupt(s);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200934 break;
ths663e8e52007-04-02 12:35:34 +0000935 } else if (bit_s) {
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200936 /* CU becomes suspended. Terminate command loop. */
ths663e8e52007-04-02 12:35:34 +0000937 set_cu_state(s, cu_suspended);
938 eepro100_cna_interrupt(s);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200939 break;
ths663e8e52007-04-02 12:35:34 +0000940 } else {
941 /* More entries in list. */
Stefan Weilaac443e2009-09-19 12:11:36 +0200942 TRACE(OTHER, logout("CU list with at least one more entry\n"));
ths663e8e52007-04-02 12:35:34 +0000943 }
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200944 }
945 TRACE(OTHER, logout("CU list empty\n"));
946 /* List is empty. Now CU is idle or suspended. */
947}
948
949static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
950{
Stefan Weilcb25a3f2010-03-02 22:37:54 +0100951 cu_state_t cu_state;
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200952 switch (val) {
953 case CU_NOP:
954 /* No operation. */
955 break;
956 case CU_START:
Stefan Weilcb25a3f2010-03-02 22:37:54 +0100957 cu_state = get_cu_state(s);
958 if (cu_state != cu_idle && cu_state != cu_suspended) {
959 /* Intel documentation says that CU must be idle or suspended
960 * for the CU start command. */
961 logout("unexpected CU state is %u\n", cu_state);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200962 }
963 set_cu_state(s, cu_active);
Stefan Weil27a05002011-04-30 22:40:10 +0200964 s->cu_offset = e100_read_reg4(s, SCBPointer);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200965 action_command(s);
ths663e8e52007-04-02 12:35:34 +0000966 break;
967 case CU_RESUME:
968 if (get_cu_state(s) != cu_suspended) {
969 logout("bad CU resume from CU state %u\n", get_cu_state(s));
970 /* Workaround for bad Linux eepro100 driver which resumes
971 * from idle state. */
Stefan Weile7493b22010-03-02 22:37:59 +0100972#if 0
973 missing("cu resume");
974#endif
ths663e8e52007-04-02 12:35:34 +0000975 set_cu_state(s, cu_suspended);
976 }
977 if (get_cu_state(s) == cu_suspended) {
Stefan Weilaac443e2009-09-19 12:11:36 +0200978 TRACE(OTHER, logout("CU resuming\n"));
ths663e8e52007-04-02 12:35:34 +0000979 set_cu_state(s, cu_active);
Stefan Weil5fa9a0a2009-10-19 21:03:26 +0200980 action_command(s);
ths663e8e52007-04-02 12:35:34 +0000981 }
982 break;
983 case CU_STATSADDR:
984 /* Load dump counters address. */
Stefan Weil27a05002011-04-30 22:40:10 +0200985 s->statsaddr = e100_read_reg4(s, SCBPointer);
Stefan Weilc16ada92011-11-23 22:20:30 +0100986 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
987 if (s->statsaddr & 3) {
988 /* Memory must be Dword aligned. */
989 logout("unaligned dump counters address\n");
990 /* Handling of misaligned addresses is undefined.
991 * Here we align the address by ignoring the lower bits. */
992 /* TODO: Test unaligned dump counter address on real hardware. */
993 s->statsaddr &= ~3;
994 }
ths663e8e52007-04-02 12:35:34 +0000995 break;
996 case CU_SHOWSTATS:
997 /* Dump statistical counters. */
Stefan Weilaac443e2009-09-19 12:11:36 +0200998 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
ths663e8e52007-04-02 12:35:34 +0000999 dump_statistics(s);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001000 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
ths663e8e52007-04-02 12:35:34 +00001001 break;
1002 case CU_CMD_BASE:
1003 /* Load CU base. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001004 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
Stefan Weil27a05002011-04-30 22:40:10 +02001005 s->cu_base = e100_read_reg4(s, SCBPointer);
ths663e8e52007-04-02 12:35:34 +00001006 break;
1007 case CU_DUMPSTATS:
1008 /* Dump and reset statistical counters. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001009 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
ths663e8e52007-04-02 12:35:34 +00001010 dump_statistics(s);
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001011 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
ths663e8e52007-04-02 12:35:34 +00001012 memset(&s->statistics, 0, sizeof(s->statistics));
1013 break;
1014 case CU_SRESUME:
1015 /* CU static resume. */
1016 missing("CU static resume");
1017 break;
1018 default:
1019 missing("Undefined CU command");
1020 }
1021}
1022
1023static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1024{
1025 switch (val) {
1026 case RU_NOP:
1027 /* No operation. */
1028 break;
1029 case RX_START:
1030 /* RU start. */
1031 if (get_ru_state(s) != ru_idle) {
1032 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
Stefan Weile7493b22010-03-02 22:37:59 +01001033#if 0
1034 assert(!"wrong RU state");
1035#endif
ths663e8e52007-04-02 12:35:34 +00001036 }
1037 set_ru_state(s, ru_ready);
Stefan Weil27a05002011-04-30 22:40:10 +02001038 s->ru_offset = e100_read_reg4(s, SCBPointer);
Jason Wangb356f762013-01-30 19:12:22 +08001039 qemu_flush_queued_packets(qemu_get_queue(s->nic));
Stefan Weilaac443e2009-09-19 12:11:36 +02001040 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
ths663e8e52007-04-02 12:35:34 +00001041 break;
1042 case RX_RESUME:
1043 /* Restart RU. */
1044 if (get_ru_state(s) != ru_suspended) {
1045 logout("RU state is %u, should be %u\n", get_ru_state(s),
1046 ru_suspended);
Stefan Weile7493b22010-03-02 22:37:59 +01001047#if 0
1048 assert(!"wrong RU state");
1049#endif
ths663e8e52007-04-02 12:35:34 +00001050 }
1051 set_ru_state(s, ru_ready);
1052 break;
Stefan Weile8240122010-03-02 22:37:53 +01001053 case RU_ABORT:
1054 /* RU abort. */
1055 if (get_ru_state(s) == ru_ready) {
1056 eepro100_rnr_interrupt(s);
1057 }
1058 set_ru_state(s, ru_idle);
1059 break;
ths663e8e52007-04-02 12:35:34 +00001060 case RX_ADDR_LOAD:
1061 /* Load RU base. */
Stefan Weilaac443e2009-09-19 12:11:36 +02001062 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
Stefan Weil27a05002011-04-30 22:40:10 +02001063 s->ru_base = e100_read_reg4(s, SCBPointer);
ths663e8e52007-04-02 12:35:34 +00001064 break;
1065 default:
1066 logout("val=0x%02x (undefined RU command)\n", val);
1067 missing("Undefined SU command");
1068 }
1069}
1070
1071static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1072{
1073 eepro100_ru_command(s, val & 0x0f);
1074 eepro100_cu_command(s, val & 0xf0);
1075 if ((val) == 0) {
Stefan Weilaac443e2009-09-19 12:11:36 +02001076 TRACE(OTHER, logout("val=0x%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001077 }
1078 /* Clear command byte after command was accepted. */
1079 s->mem[SCBCmd] = 0;
1080}
1081
1082/*****************************************************************************
1083 *
1084 * EEPROM emulation.
1085 *
1086 ****************************************************************************/
1087
1088#define EEPROM_CS 0x02
1089#define EEPROM_SK 0x01
1090#define EEPROM_DI 0x04
1091#define EEPROM_DO 0x08
1092
1093static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1094{
Stefan Weile5e23ab2011-04-30 22:40:08 +02001095 uint16_t val = e100_read_reg2(s, SCBeeprom);
ths663e8e52007-04-02 12:35:34 +00001096 if (eeprom93xx_read(s->eeprom)) {
1097 val |= EEPROM_DO;
1098 } else {
1099 val &= ~EEPROM_DO;
1100 }
Stefan Weilaac443e2009-09-19 12:11:36 +02001101 TRACE(EEPROM, logout("val=0x%04x\n", val));
ths663e8e52007-04-02 12:35:34 +00001102 return val;
1103}
1104
Anthony Liguoric227f092009-10-01 16:12:16 -05001105static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
ths663e8e52007-04-02 12:35:34 +00001106{
Stefan Weilaac443e2009-09-19 12:11:36 +02001107 TRACE(EEPROM, logout("val=0x%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001108
Stefan Weilebabb672011-04-26 10:29:36 +02001109 /* mask unwritable bits */
Stefan Weile7493b22010-03-02 22:37:59 +01001110#if 0
1111 val = SET_MASKED(val, 0x31, eeprom->value);
1112#endif
ths663e8e52007-04-02 12:35:34 +00001113
1114 int eecs = ((val & EEPROM_CS) != 0);
1115 int eesk = ((val & EEPROM_SK) != 0);
1116 int eedi = ((val & EEPROM_DI) != 0);
1117 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1118}
1119
ths663e8e52007-04-02 12:35:34 +00001120/*****************************************************************************
1121 *
1122 * MDI emulation.
1123 *
1124 ****************************************************************************/
1125
1126#if defined(DEBUG_EEPRO100)
Reimar Döffinger6a0b9cc2009-09-12 15:20:24 +00001127static const char * const mdi_op_name[] = {
ths663e8e52007-04-02 12:35:34 +00001128 "opcode 0",
1129 "write",
1130 "read",
1131 "opcode 3"
1132};
1133
Reimar Döffinger6a0b9cc2009-09-12 15:20:24 +00001134static const char * const mdi_reg_name[] = {
ths663e8e52007-04-02 12:35:34 +00001135 "Control",
1136 "Status",
1137 "PHY Identification (Word 1)",
1138 "PHY Identification (Word 2)",
1139 "Auto-Negotiation Advertisement",
1140 "Auto-Negotiation Link Partner Ability",
1141 "Auto-Negotiation Expansion"
1142};
Stefan Weilaac443e2009-09-19 12:11:36 +02001143
1144static const char *reg2name(uint8_t reg)
1145{
1146 static char buffer[10];
1147 const char *p = buffer;
1148 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1149 p = mdi_reg_name[reg];
1150 } else {
1151 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1152 }
1153 return p;
1154}
ths663e8e52007-04-02 12:35:34 +00001155#endif /* DEBUG_EEPRO100 */
1156
1157static uint32_t eepro100_read_mdi(EEPRO100State * s)
1158{
Stefan Weile5e23ab2011-04-30 22:40:08 +02001159 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
ths663e8e52007-04-02 12:35:34 +00001160
1161#ifdef DEBUG_EEPRO100
1162 uint8_t raiseint = (val & BIT(29)) >> 29;
1163 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1164 uint8_t phy = (val & BITS(25, 21)) >> 21;
1165 uint8_t reg = (val & BITS(20, 16)) >> 16;
1166 uint16_t data = (val & BITS(15, 0));
1167#endif
1168 /* Emulation takes no time to finish MDI transaction. */
1169 val |= BIT(28);
1170 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1171 val, raiseint, mdi_op_name[opcode], phy,
Stefan Weilaac443e2009-09-19 12:11:36 +02001172 reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001173 return val;
1174}
1175
Stefan Weil0113f482011-04-30 22:40:11 +02001176static void eepro100_write_mdi(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +00001177{
Stefan Weil0113f482011-04-30 22:40:11 +02001178 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
ths663e8e52007-04-02 12:35:34 +00001179 uint8_t raiseint = (val & BIT(29)) >> 29;
1180 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1181 uint8_t phy = (val & BITS(25, 21)) >> 21;
1182 uint8_t reg = (val & BITS(20, 16)) >> 16;
1183 uint16_t data = (val & BITS(15, 0));
Stefan Weilaac443e2009-09-19 12:11:36 +02001184 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1185 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001186 if (phy != 1) {
1187 /* Unsupported PHY address. */
Stefan Weile7493b22010-03-02 22:37:59 +01001188#if 0
1189 logout("phy must be 1 but is %u\n", phy);
1190#endif
ths663e8e52007-04-02 12:35:34 +00001191 data = 0;
1192 } else if (opcode != 1 && opcode != 2) {
1193 /* Unsupported opcode. */
1194 logout("opcode must be 1 or 2 but is %u\n", opcode);
1195 data = 0;
1196 } else if (reg > 6) {
1197 /* Unsupported register. */
1198 logout("register must be 0...6 but is %u\n", reg);
1199 data = 0;
1200 } else {
1201 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1202 val, raiseint, mdi_op_name[opcode], phy,
Stefan Weilaac443e2009-09-19 12:11:36 +02001203 reg2name(reg), data));
ths663e8e52007-04-02 12:35:34 +00001204 if (opcode == 1) {
1205 /* MDI write */
1206 switch (reg) {
1207 case 0: /* Control Register */
1208 if (data & 0x8000) {
1209 /* Reset status and control registers to default. */
1210 s->mdimem[0] = eepro100_mdi_default[0];
1211 s->mdimem[1] = eepro100_mdi_default[1];
1212 data = s->mdimem[reg];
1213 } else {
1214 /* Restart Auto Configuration = Normal Operation */
1215 data &= ~0x0200;
1216 }
1217 break;
1218 case 1: /* Status Register */
1219 missing("not writable");
1220 data = s->mdimem[reg];
1221 break;
1222 case 2: /* PHY Identification Register (Word 1) */
1223 case 3: /* PHY Identification Register (Word 2) */
1224 missing("not implemented");
1225 break;
1226 case 4: /* Auto-Negotiation Advertisement Register */
1227 case 5: /* Auto-Negotiation Link Partner Ability Register */
1228 break;
1229 case 6: /* Auto-Negotiation Expansion Register */
1230 default:
1231 missing("not implemented");
1232 }
1233 s->mdimem[reg] = data;
1234 } else if (opcode == 2) {
1235 /* MDI read */
1236 switch (reg) {
1237 case 0: /* Control Register */
1238 if (data & 0x8000) {
1239 /* Reset status and control registers to default. */
1240 s->mdimem[0] = eepro100_mdi_default[0];
1241 s->mdimem[1] = eepro100_mdi_default[1];
1242 }
1243 break;
1244 case 1: /* Status Register */
1245 s->mdimem[reg] |= 0x0020;
1246 break;
1247 case 2: /* PHY Identification Register (Word 1) */
1248 case 3: /* PHY Identification Register (Word 2) */
1249 case 4: /* Auto-Negotiation Advertisement Register */
1250 break;
1251 case 5: /* Auto-Negotiation Link Partner Ability Register */
1252 s->mdimem[reg] = 0x41fe;
1253 break;
1254 case 6: /* Auto-Negotiation Expansion Register */
1255 s->mdimem[reg] = 0x0001;
1256 break;
1257 }
1258 data = s->mdimem[reg];
1259 }
1260 /* Emulation takes no time to finish MDI transaction.
1261 * Set MDI bit in SCB status register. */
1262 s->mem[SCBAck] |= 0x08;
1263 val |= BIT(28);
1264 if (raiseint) {
1265 eepro100_mdi_interrupt(s);
1266 }
1267 }
1268 val = (val & 0xffff0000) + data;
Stefan Weile5e23ab2011-04-30 22:40:08 +02001269 e100_write_reg4(s, SCBCtrlMDI, val);
ths663e8e52007-04-02 12:35:34 +00001270}
1271
1272/*****************************************************************************
1273 *
1274 * Port emulation.
1275 *
1276 ****************************************************************************/
1277
1278#define PORT_SOFTWARE_RESET 0
1279#define PORT_SELFTEST 1
1280#define PORT_SELECTIVE_RESET 2
1281#define PORT_DUMP 3
1282#define PORT_SELECTION_MASK 3
1283
1284typedef struct {
1285 uint32_t st_sign; /* Self Test Signature */
1286 uint32_t st_result; /* Self Test Results */
Anthony Liguoric227f092009-10-01 16:12:16 -05001287} eepro100_selftest_t;
ths663e8e52007-04-02 12:35:34 +00001288
1289static uint32_t eepro100_read_port(EEPRO100State * s)
1290{
1291 return 0;
1292}
1293
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001294static void eepro100_write_port(EEPRO100State *s)
ths663e8e52007-04-02 12:35:34 +00001295{
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001296 uint32_t val = e100_read_reg4(s, SCBPort);
ths663e8e52007-04-02 12:35:34 +00001297 uint32_t address = (val & ~PORT_SELECTION_MASK);
1298 uint8_t selection = (val & PORT_SELECTION_MASK);
1299 switch (selection) {
1300 case PORT_SOFTWARE_RESET:
1301 nic_reset(s);
1302 break;
1303 case PORT_SELFTEST:
Stefan Weilaac443e2009-09-19 12:11:36 +02001304 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
Anthony Liguoric227f092009-10-01 16:12:16 -05001305 eepro100_selftest_t data;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001306 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
ths663e8e52007-04-02 12:35:34 +00001307 data.st_sign = 0xffffffff;
1308 data.st_result = 0;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001309 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
ths663e8e52007-04-02 12:35:34 +00001310 break;
1311 case PORT_SELECTIVE_RESET:
Stefan Weilaac443e2009-09-19 12:11:36 +02001312 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
ths663e8e52007-04-02 12:35:34 +00001313 nic_selective_reset(s);
1314 break;
1315 default:
1316 logout("val=0x%08x\n", val);
1317 missing("unknown port selection");
1318 }
1319}
1320
1321/*****************************************************************************
1322 *
1323 * General hardware emulation.
1324 *
1325 ****************************************************************************/
1326
1327static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1328{
Blue Swirlef476062010-10-13 18:38:07 +00001329 uint8_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001330 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001331 val = s->mem[addr];
ths663e8e52007-04-02 12:35:34 +00001332 }
1333
1334 switch (addr) {
1335 case SCBStatus:
ths663e8e52007-04-02 12:35:34 +00001336 case SCBAck:
Stefan Weilaac443e2009-09-19 12:11:36 +02001337 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001338 break;
1339 case SCBCmd:
Stefan Weilaac443e2009-09-19 12:11:36 +02001340 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
Stefan Weile7493b22010-03-02 22:37:59 +01001341#if 0
1342 val = eepro100_read_command(s);
1343#endif
ths663e8e52007-04-02 12:35:34 +00001344 break;
1345 case SCBIntmask:
Stefan Weilaac443e2009-09-19 12:11:36 +02001346 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001347 break;
1348 case SCBPort + 3:
Stefan Weilaac443e2009-09-19 12:11:36 +02001349 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001350 break;
1351 case SCBeeprom:
1352 val = eepro100_read_eeprom(s);
1353 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001354 case SCBCtrlMDI:
1355 case SCBCtrlMDI + 1:
1356 case SCBCtrlMDI + 2:
1357 case SCBCtrlMDI + 3:
1358 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1359 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1360 break;
Stefan Weil0908bba2010-03-02 22:37:42 +01001361 case SCBpmdr: /* Power Management Driver Register */
ths663e8e52007-04-02 12:35:34 +00001362 val = 0;
Stefan Weilaac443e2009-09-19 12:11:36 +02001363 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001364 break;
Stefan Weila39bd012011-04-30 22:40:12 +02001365 case SCBgctrl: /* General Control Register */
1366 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1367 break;
Stefan Weil0908bba2010-03-02 22:37:42 +01001368 case SCBgstat: /* General Status Register */
ths663e8e52007-04-02 12:35:34 +00001369 /* 100 Mbps full duplex, valid link */
1370 val = 0x07;
Stefan Weilaac443e2009-09-19 12:11:36 +02001371 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
ths663e8e52007-04-02 12:35:34 +00001372 break;
1373 default:
1374 logout("addr=%s val=0x%02x\n", regname(addr), val);
1375 missing("unknown byte read");
1376 }
1377 return val;
1378}
1379
1380static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1381{
Blue Swirlef476062010-10-13 18:38:07 +00001382 uint16_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001383 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001384 val = e100_read_reg2(s, addr);
ths663e8e52007-04-02 12:35:34 +00001385 }
1386
ths663e8e52007-04-02 12:35:34 +00001387 switch (addr) {
1388 case SCBStatus:
=?UTF-8?q?Reimar=20D=C3=B6ffinger?=dbbaaff2009-10-02 18:39:41 +02001389 case SCBCmd:
Stefan Weilaac443e2009-09-19 12:11:36 +02001390 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001391 break;
1392 case SCBeeprom:
1393 val = eepro100_read_eeprom(s);
Stefan Weilaac443e2009-09-19 12:11:36 +02001394 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001395 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001396 case SCBCtrlMDI:
1397 case SCBCtrlMDI + 2:
1398 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1399 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1400 break;
ths663e8e52007-04-02 12:35:34 +00001401 default:
1402 logout("addr=%s val=0x%04x\n", regname(addr), val);
1403 missing("unknown word read");
1404 }
1405 return val;
1406}
1407
1408static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1409{
Blue Swirlef476062010-10-13 18:38:07 +00001410 uint32_t val = 0;
ths663e8e52007-04-02 12:35:34 +00001411 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001412 val = e100_read_reg4(s, addr);
ths663e8e52007-04-02 12:35:34 +00001413 }
1414
1415 switch (addr) {
1416 case SCBStatus:
Stefan Weilaac443e2009-09-19 12:11:36 +02001417 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001418 break;
1419 case SCBPointer:
Stefan Weilaac443e2009-09-19 12:11:36 +02001420 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001421 break;
1422 case SCBPort:
1423 val = eepro100_read_port(s);
Stefan Weilaac443e2009-09-19 12:11:36 +02001424 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001425 break;
Stefan Weil072476e2011-04-30 22:40:13 +02001426 case SCBflash:
1427 val = eepro100_read_eeprom(s);
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
ths663e8e52007-04-02 12:35:34 +00001430 case SCBCtrlMDI:
1431 val = eepro100_read_mdi(s);
1432 break;
1433 default:
1434 logout("addr=%s val=0x%08x\n", regname(addr), val);
1435 missing("unknown longword read");
1436 }
1437 return val;
1438}
1439
1440static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1441{
Stefan Weile74818f2010-04-06 13:44:01 +02001442 /* SCBStatus is readonly. */
1443 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001444 s->mem[addr] = val;
ths663e8e52007-04-02 12:35:34 +00001445 }
1446
ths663e8e52007-04-02 12:35:34 +00001447 switch (addr) {
1448 case SCBStatus:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001449 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001450 break;
1451 case SCBAck:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001452 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001453 eepro100_acknowledge(s);
1454 break;
1455 case SCBCmd:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001456 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001457 eepro100_write_command(s, val);
1458 break;
1459 case SCBIntmask:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001460 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001461 if (val & BIT(1)) {
1462 eepro100_swi_interrupt(s);
1463 }
1464 eepro100_interrupt(s, 0);
1465 break;
Stefan Weil27a05002011-04-30 22:40:10 +02001466 case SCBPointer:
1467 case SCBPointer + 1:
1468 case SCBPointer + 2:
1469 case SCBPointer + 3:
1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1471 break;
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001472 case SCBPort:
1473 case SCBPort + 1:
1474 case SCBPort + 2:
1475 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1476 break;
ths663e8e52007-04-02 12:35:34 +00001477 case SCBPort + 3:
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001478 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1479 eepro100_write_port(s);
1480 break;
Stefan Weilaac443e2009-09-19 12:11:36 +02001481 case SCBFlow: /* does not exist on 82557 */
ths3257d2b2007-09-14 22:22:13 +00001482 case SCBFlow + 1:
1483 case SCBFlow + 2:
Stefan Weil0908bba2010-03-02 22:37:42 +01001484 case SCBpmdr: /* does not exist on 82557 */
Stefan Weilaac443e2009-09-19 12:11:36 +02001485 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001486 break;
1487 case SCBeeprom:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001488 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001489 eepro100_write_eeprom(s->eeprom, val);
1490 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001491 case SCBCtrlMDI:
1492 case SCBCtrlMDI + 1:
1493 case SCBCtrlMDI + 2:
1494 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1495 break;
1496 case SCBCtrlMDI + 3:
1497 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1498 eepro100_write_mdi(s);
1499 break;
ths663e8e52007-04-02 12:35:34 +00001500 default:
1501 logout("addr=%s val=0x%02x\n", regname(addr), val);
1502 missing("unknown byte write");
1503 }
1504}
1505
1506static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1507{
Stefan Weile74818f2010-04-06 13:44:01 +02001508 /* SCBStatus is readonly. */
1509 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001510 e100_write_reg2(s, addr, val);
ths663e8e52007-04-02 12:35:34 +00001511 }
1512
ths663e8e52007-04-02 12:35:34 +00001513 switch (addr) {
1514 case SCBStatus:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001515 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
Stefan Weile74818f2010-04-06 13:44:01 +02001516 s->mem[SCBAck] = (val >> 8);
ths663e8e52007-04-02 12:35:34 +00001517 eepro100_acknowledge(s);
1518 break;
1519 case SCBCmd:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001520 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001521 eepro100_write_command(s, val);
1522 eepro100_write1(s, SCBIntmask, val >> 8);
1523 break;
Stefan Weil27a05002011-04-30 22:40:10 +02001524 case SCBPointer:
1525 case SCBPointer + 2:
1526 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1527 break;
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001528 case SCBPort:
1529 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1530 break;
1531 case SCBPort + 2:
1532 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1533 eepro100_write_port(s);
1534 break;
ths663e8e52007-04-02 12:35:34 +00001535 case SCBeeprom:
Stefan Weil1b4f97d2011-04-30 22:40:04 +02001536 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001537 eepro100_write_eeprom(s->eeprom, val);
1538 break;
Stefan Weil0113f482011-04-30 22:40:11 +02001539 case SCBCtrlMDI:
1540 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1541 break;
1542 case SCBCtrlMDI + 2:
1543 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1544 eepro100_write_mdi(s);
1545 break;
ths663e8e52007-04-02 12:35:34 +00001546 default:
1547 logout("addr=%s val=0x%04x\n", regname(addr), val);
1548 missing("unknown word write");
1549 }
1550}
1551
1552static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1553{
1554 if (addr <= sizeof(s->mem) - sizeof(val)) {
Stefan Weile5e23ab2011-04-30 22:40:08 +02001555 e100_write_reg4(s, addr, val);
ths663e8e52007-04-02 12:35:34 +00001556 }
1557
1558 switch (addr) {
1559 case SCBPointer:
Stefan Weil27a05002011-04-30 22:40:10 +02001560 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
ths663e8e52007-04-02 12:35:34 +00001561 break;
1562 case SCBPort:
Stefan Weilaac443e2009-09-19 12:11:36 +02001563 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
Stefan Weil3fd3d0b2011-04-30 22:40:09 +02001564 eepro100_write_port(s);
ths663e8e52007-04-02 12:35:34 +00001565 break;
Stefan Weil072476e2011-04-30 22:40:13 +02001566 case SCBflash:
1567 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1568 val = val >> 16;
1569 eepro100_write_eeprom(s->eeprom, val);
1570 break;
ths663e8e52007-04-02 12:35:34 +00001571 case SCBCtrlMDI:
Stefan Weil0113f482011-04-30 22:40:11 +02001572 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1573 eepro100_write_mdi(s);
ths663e8e52007-04-02 12:35:34 +00001574 break;
1575 default:
1576 logout("addr=%s val=0x%08x\n", regname(addr), val);
1577 missing("unknown longword write");
1578 }
1579}
1580
Avi Kivitya8170e52012-10-23 12:30:10 +02001581static uint64_t eepro100_read(void *opaque, hwaddr addr,
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001582 unsigned size)
ths663e8e52007-04-02 12:35:34 +00001583{
1584 EEPRO100State *s = opaque;
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001585
1586 switch (size) {
1587 case 1: return eepro100_read1(s, addr);
1588 case 2: return eepro100_read2(s, addr);
1589 case 4: return eepro100_read4(s, addr);
1590 default: abort();
1591 }
ths663e8e52007-04-02 12:35:34 +00001592}
1593
Avi Kivitya8170e52012-10-23 12:30:10 +02001594static void eepro100_write(void *opaque, hwaddr addr,
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001595 uint64_t data, unsigned size)
ths663e8e52007-04-02 12:35:34 +00001596{
1597 EEPRO100State *s = opaque;
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001598
1599 switch (size) {
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001600 case 1:
1601 eepro100_write1(s, addr, data);
1602 break;
1603 case 2:
1604 eepro100_write2(s, addr, data);
1605 break;
1606 case 4:
1607 eepro100_write4(s, addr, data);
1608 break;
1609 default:
1610 abort();
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001611 }
ths663e8e52007-04-02 12:35:34 +00001612}
1613
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001614static const MemoryRegionOps eepro100_ops = {
1615 .read = eepro100_read,
1616 .write = eepro100_write,
1617 .endianness = DEVICE_LITTLE_ENDIAN,
ths663e8e52007-04-02 12:35:34 +00001618};
1619
Stefan Hajnoczi4e68f7a2012-07-24 16:35:13 +01001620static int nic_can_receive(NetClientState *nc)
ths663e8e52007-04-02 12:35:34 +00001621{
Jason Wangcc1f0f42013-01-30 19:12:23 +08001622 EEPRO100State *s = qemu_get_nic_opaque(nc);
Stefan Weilaac443e2009-09-19 12:11:36 +02001623 TRACE(RXTX, logout("%p\n", s));
ths663e8e52007-04-02 12:35:34 +00001624 return get_ru_state(s) == ru_ready;
Stefan Weile7493b22010-03-02 22:37:59 +01001625#if 0
1626 return !eepro100_buffer_full(s);
1627#endif
ths663e8e52007-04-02 12:35:34 +00001628}
1629
Stefan Hajnoczi4e68f7a2012-07-24 16:35:13 +01001630static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
ths663e8e52007-04-02 12:35:34 +00001631{
1632 /* TODO:
1633 * - Magic packets should set bit 30 in power management driver register.
1634 * - Interesting packets should set bit 29 in power management driver register.
1635 */
Jason Wangcc1f0f42013-01-30 19:12:23 +08001636 EEPRO100State *s = qemu_get_nic_opaque(nc);
ths663e8e52007-04-02 12:35:34 +00001637 uint16_t rfd_status = 0xa000;
Stefan Weil792f1d62011-04-30 22:40:07 +02001638#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1639 uint8_t min_buf[60];
1640#endif
ths663e8e52007-04-02 12:35:34 +00001641 static const uint8_t broadcast_macaddr[6] =
1642 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1643
Stefan Weil792f1d62011-04-30 22:40:07 +02001644#if defined(CONFIG_PAD_RECEIVED_FRAMES)
1645 /* Pad to minimum Ethernet frame length */
1646 if (size < sizeof(min_buf)) {
1647 memcpy(min_buf, buf, size);
1648 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1649 buf = min_buf;
1650 size = sizeof(min_buf);
1651 }
1652#endif
1653
ths663e8e52007-04-02 12:35:34 +00001654 if (s->configuration[8] & 0x80) {
1655 /* CSMA is disabled. */
1656 logout("%p received while CSMA is disabled\n", s);
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001657 return -1;
Stefan Weil792f1d62011-04-30 22:40:07 +02001658#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
Stefan Weilced52962010-03-02 22:37:49 +01001659 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
ths663e8e52007-04-02 12:35:34 +00001660 /* Short frame and configuration byte 7/0 (discard short receive) set:
1661 * Short frame is discarded */
Stefan Weil067d01d2009-09-19 12:37:51 +02001662 logout("%p received short frame (%zu byte)\n", s, size);
ths663e8e52007-04-02 12:35:34 +00001663 s->statistics.rx_short_frame_errors++;
Stefan Weile7493b22010-03-02 22:37:59 +01001664 return -1;
1665#endif
Stefan Weilced52962010-03-02 22:37:49 +01001666 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
ths663e8e52007-04-02 12:35:34 +00001667 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1668 * Long frames are discarded. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001669 logout("%p received long frame (%zu byte), ignored\n", s, size);
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001670 return -1;
Stefan Weile7493b22010-03-02 22:37:59 +01001671 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
ths663e8e52007-04-02 12:35:34 +00001672 /* Frame matches individual address. */
1673 /* TODO: check configuration byte 15/4 (ignore U/L). */
Stefan Weil067d01d2009-09-19 12:37:51 +02001674 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001675 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1676 /* Broadcast frame. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001677 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001678 rfd_status |= 0x0002;
Stefan Weil7b8737d2009-12-20 16:52:24 +01001679 } else if (buf[0] & 0x01) {
ths663e8e52007-04-02 12:35:34 +00001680 /* Multicast frame. */
Stefan Weil7b8737d2009-12-20 16:52:24 +01001681 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001682 if (s->configuration[21] & BIT(3)) {
Stefan Weil7b8737d2009-12-20 16:52:24 +01001683 /* Multicast all bit is set, receive all multicast frames. */
1684 } else {
Stefan Weil69f3ce72012-04-10 20:48:54 +02001685 unsigned mcast_idx = e100_compute_mcast_idx(buf);
Stefan Weil7b8737d2009-12-20 16:52:24 +01001686 assert(mcast_idx < 64);
1687 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1688 /* Multicast frame is allowed in hash table. */
Stefan Weilced52962010-03-02 22:37:49 +01001689 } else if (s->configuration[15] & BIT(0)) {
Stefan Weil7b8737d2009-12-20 16:52:24 +01001690 /* Promiscuous: receive all. */
1691 rfd_status |= 0x0004;
1692 } else {
1693 TRACE(RXTX, logout("%p multicast ignored\n", s));
1694 return -1;
1695 }
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001696 }
Stefan Weil7b8737d2009-12-20 16:52:24 +01001697 /* TODO: Next not for promiscuous mode? */
ths663e8e52007-04-02 12:35:34 +00001698 rfd_status |= 0x0002;
Stefan Weilced52962010-03-02 22:37:49 +01001699 } else if (s->configuration[15] & BIT(0)) {
ths663e8e52007-04-02 12:35:34 +00001700 /* Promiscuous: receive all. */
Stefan Weil067d01d2009-09-19 12:37:51 +02001701 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
ths663e8e52007-04-02 12:35:34 +00001702 rfd_status |= 0x0004;
Stefan Weil010ec622010-09-29 21:59:55 +02001703 } else if (s->configuration[20] & BIT(6)) {
1704 /* Multiple IA bit set. */
1705 unsigned mcast_idx = compute_mcast_idx(buf);
1706 assert(mcast_idx < 64);
1707 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1708 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1709 } else {
1710 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1711 return -1;
1712 }
ths663e8e52007-04-02 12:35:34 +00001713 } else {
Stefan Weil067d01d2009-09-19 12:37:51 +02001714 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
Stefan Weilaac443e2009-09-19 12:11:36 +02001715 nic_dump(buf, size)));
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001716 return size;
ths663e8e52007-04-02 12:35:34 +00001717 }
1718
1719 if (get_ru_state(s) != ru_ready) {
Stefan Weilaac443e2009-09-19 12:11:36 +02001720 /* No resources available. */
1721 logout("no resources, state=%u\n", get_ru_state(s));
Stefan Weile8240122010-03-02 22:37:53 +01001722 /* TODO: RNR interrupt only at first failed frame? */
1723 eepro100_rnr_interrupt(s);
ths663e8e52007-04-02 12:35:34 +00001724 s->statistics.rx_resource_errors++;
Stefan Weile7493b22010-03-02 22:37:59 +01001725#if 0
1726 assert(!"no resources");
1727#endif
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001728 return -1;
ths663e8e52007-04-02 12:35:34 +00001729 }
Stefan Weile7493b22010-03-02 22:37:59 +01001730 /* !!! */
Anthony Liguoric227f092009-10-01 16:12:16 -05001731 eepro100_rx_t rx;
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001732 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
David Gibsone965d4b2011-11-04 12:03:32 +11001733 &rx, sizeof(eepro100_rx_t));
ths663e8e52007-04-02 12:35:34 +00001734 uint16_t rfd_command = le16_to_cpu(rx.command);
1735 uint16_t rfd_size = le16_to_cpu(rx.size);
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001736
1737 if (size > rfd_size) {
1738 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1739 "(%zu bytes); data truncated\n", rfd_size, size);
1740 size = rfd_size;
1741 }
Stefan Weil792f1d62011-04-30 22:40:07 +02001742#if !defined(CONFIG_PAD_RECEIVED_FRAMES)
ths663e8e52007-04-02 12:35:34 +00001743 if (size < 64) {
1744 rfd_status |= 0x0080;
1745 }
Stefan Weil792f1d62011-04-30 22:40:07 +02001746#endif
Stefan Weilaac443e2009-09-19 12:11:36 +02001747 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1748 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001749 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1750 offsetof(eepro100_rx_t, status), rfd_status);
1751 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1752 offsetof(eepro100_rx_t, count), size);
ths663e8e52007-04-02 12:35:34 +00001753 /* Early receive interrupt not supported. */
Stefan Weile7493b22010-03-02 22:37:59 +01001754#if 0
1755 eepro100_er_interrupt(s);
1756#endif
ths663e8e52007-04-02 12:35:34 +00001757 /* Receive CRC Transfer not supported. */
Stefan Weilced52962010-03-02 22:37:49 +01001758 if (s->configuration[18] & BIT(2)) {
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001759 missing("Receive CRC Transfer");
1760 return -1;
1761 }
ths663e8e52007-04-02 12:35:34 +00001762 /* TODO: check stripping enable bit. */
Stefan Weile7493b22010-03-02 22:37:59 +01001763#if 0
1764 assert(!(s->configuration[17] & BIT(0)));
1765#endif
Eduard - Gabriel Munteanu16ef60c2011-10-31 17:06:49 +11001766 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1767 sizeof(eepro100_rx_t), buf, size);
ths663e8e52007-04-02 12:35:34 +00001768 s->statistics.rx_good_frames++;
1769 eepro100_fr_interrupt(s);
1770 s->ru_offset = le32_to_cpu(rx.link);
Stefan Weilced52962010-03-02 22:37:49 +01001771 if (rfd_command & COMMAND_EL) {
ths663e8e52007-04-02 12:35:34 +00001772 /* EL bit is set, so this was the last frame. */
Kevin Wolf7f1e9d42009-09-23 17:42:42 +02001773 logout("receive: Running out of frames\n");
Bo Yang10699852012-08-29 19:26:11 +08001774 set_ru_state(s, ru_no_resources);
1775 eepro100_rnr_interrupt(s);
ths663e8e52007-04-02 12:35:34 +00001776 }
Stefan Weilced52962010-03-02 22:37:49 +01001777 if (rfd_command & COMMAND_S) {
ths663e8e52007-04-02 12:35:34 +00001778 /* S bit is set. */
1779 set_ru_state(s, ru_suspended);
1780 }
Mark McLoughlin4f1c9422009-05-18 13:40:55 +01001781 return size;
ths663e8e52007-04-02 12:35:34 +00001782}
1783
Juan Quintela151b2982009-10-19 15:37:57 +02001784static const VMStateDescription vmstate_eepro100 = {
1785 .version_id = 3,
1786 .minimum_version_id = 2,
1787 .minimum_version_id_old = 2,
1788 .fields = (VMStateField []) {
1789 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1790 VMSTATE_UNUSED(32),
1791 VMSTATE_BUFFER(mult, EEPRO100State),
1792 VMSTATE_BUFFER(mem, EEPRO100State),
1793 /* Save all members of struct between scb_stat and mem. */
1794 VMSTATE_UINT8(scb_stat, EEPRO100State),
1795 VMSTATE_UINT8(int_stat, EEPRO100State),
1796 VMSTATE_UNUSED(3*4),
1797 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1798 VMSTATE_UNUSED(19*4),
1799 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1800 /* The eeprom should be saved and restored by its own routines. */
1801 VMSTATE_UINT32(device, EEPRO100State),
1802 /* TODO check device. */
Juan Quintela151b2982009-10-19 15:37:57 +02001803 VMSTATE_UINT32(cu_base, EEPRO100State),
1804 VMSTATE_UINT32(cu_offset, EEPRO100State),
1805 VMSTATE_UINT32(ru_base, EEPRO100State),
1806 VMSTATE_UINT32(ru_offset, EEPRO100State),
1807 VMSTATE_UINT32(statsaddr, EEPRO100State),
Stefan Weilba42b642009-10-30 13:36:21 +01001808 /* Save eepro100_stats_t statistics. */
Juan Quintela151b2982009-10-19 15:37:57 +02001809 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1810 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1811 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1817 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1818 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1819 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1825 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1826 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1827 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1828 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1829 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
Juan Quintela151b2982009-10-19 15:37:57 +02001830 /* Configuration bytes. */
1831 VMSTATE_BUFFER(configuration, EEPRO100State),
1832 VMSTATE_END_OF_LIST()
Stefan Weilaac443e2009-09-19 12:11:36 +02001833 }
Juan Quintela151b2982009-10-19 15:37:57 +02001834};
ths663e8e52007-04-02 12:35:34 +00001835
Stefan Hajnoczi4e68f7a2012-07-24 16:35:13 +01001836static void nic_cleanup(NetClientState *nc)
aliguorib946a152009-04-17 17:11:08 +00001837{
Jason Wangcc1f0f42013-01-30 19:12:23 +08001838 EEPRO100State *s = qemu_get_nic_opaque(nc);
aliguorib946a152009-04-17 17:11:08 +00001839
Mark McLoughline00e3652009-11-25 18:49:16 +00001840 s->nic = NULL;
aliguorib946a152009-04-17 17:11:08 +00001841}
1842
Alex Williamsonf90c2bc2012-07-03 22:39:27 -06001843static void pci_nic_uninit(PCIDevice *pci_dev)
aliguorib946a152009-04-17 17:11:08 +00001844{
Stefan Weilc4c270e2009-09-19 13:02:09 +02001845 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
aliguorib946a152009-04-17 17:11:08 +00001846
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001847 memory_region_destroy(&s->mmio_bar);
1848 memory_region_destroy(&s->io_bar);
1849 memory_region_destroy(&s->flash_bar);
Alex Williamson0be71e32010-06-25 11:09:07 -06001850 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
Alex Williamson5fce2b32010-06-25 11:09:21 -06001851 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
Jason Wang948ecf22013-01-30 19:12:24 +08001852 qemu_del_nic(s->nic);
aliguorib946a152009-04-17 17:11:08 +00001853}
1854
Mark McLoughline00e3652009-11-25 18:49:16 +00001855static NetClientInfo net_eepro100_info = {
Laszlo Ersek2be64a62012-07-17 16:17:12 +02001856 .type = NET_CLIENT_OPTIONS_KIND_NIC,
Mark McLoughline00e3652009-11-25 18:49:16 +00001857 .size = sizeof(NICState),
1858 .can_receive = nic_can_receive,
1859 .receive = nic_receive,
1860 .cleanup = nic_cleanup,
1861};
1862
Stefan Weil558c8632010-04-06 13:44:03 +02001863static int e100_nic_init(PCIDevice *pci_dev)
ths663e8e52007-04-02 12:35:34 +00001864{
Juan Quintela273a2142009-08-24 18:42:37 +02001865 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
Anthony Liguori40021f02011-12-04 12:22:06 -06001866 E100PCIDeviceInfo *info = eepro100_get_class(s);
ths663e8e52007-04-02 12:35:34 +00001867
Stefan Weilaac443e2009-09-19 12:11:36 +02001868 TRACE(OTHER, logout("\n"));
ths663e8e52007-04-02 12:35:34 +00001869
Anthony Liguori40021f02011-12-04 12:22:06 -06001870 s->device = info->device;
ths663e8e52007-04-02 12:35:34 +00001871
Anthony Liguori40021f02011-12-04 12:22:06 -06001872 e100_pci_reset(s);
ths663e8e52007-04-02 12:35:34 +00001873
1874 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1875 * i82559 and later support 64 or 256 word EEPROM. */
Alex Williamson5fce2b32010-06-25 11:09:21 -06001876 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
ths663e8e52007-04-02 12:35:34 +00001877
1878 /* Handler for memory-mapped I/O */
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001879 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1880 PCI_MEM_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001881 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001882 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1883 PCI_IO_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001884 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
Avi Kivity5e6ffdd2011-08-08 16:09:09 +03001885 /* FIXME: flash aliases to mmio?! */
1886 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1887 PCI_FLASH_SIZE);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001888 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
ths663e8e52007-04-02 12:35:34 +00001889
Gerd Hoffmann508ef932009-10-21 15:25:36 +02001890 qemu_macaddr_default_if_unset(&s->conf.macaddr);
Stefan Weilce0e58b2010-03-02 22:37:41 +01001891 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
ths663e8e52007-04-02 12:35:34 +00001892
1893 nic_reset(s);
1894
Mark McLoughline00e3652009-11-25 18:49:16 +00001895 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
Anthony Liguorif79f2bf2011-12-04 11:17:51 -06001896 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
ths663e8e52007-04-02 12:35:34 +00001897
Jason Wangb356f762013-01-30 19:12:22 +08001898 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1899 TRACE(OTHER, logout("%s\n", qemu_get_queue(s->nic)->info_str));
ths663e8e52007-04-02 12:35:34 +00001900
Jan Kiszkaa08d4362009-06-27 09:25:07 +02001901 qemu_register_reset(nic_reset, s);
ths663e8e52007-04-02 12:35:34 +00001902
Anthony Liguori7267c092011-08-20 22:09:37 -05001903 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
Juan Quintela151b2982009-10-19 15:37:57 +02001904 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
Jason Wangb356f762013-01-30 19:12:22 +08001905 s->vmstate->name = qemu_get_queue(s->nic)->model;
Alex Williamson0be71e32010-06-25 11:09:07 -06001906 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
Stefan Weil4e9df062009-10-31 13:38:33 +01001907
Gleb Natapov1ca4d092010-12-08 13:35:05 +02001908 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1909
Gerd Hoffmann81a322d2009-08-14 10:36:05 +02001910 return 0;
ths663e8e52007-04-02 12:35:34 +00001911}
1912
Stefan Weil558c8632010-04-06 13:44:03 +02001913static E100PCIDeviceInfo e100_devices[] = {
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001914 {
Anthony Liguori39bffca2011-12-07 21:34:16 -06001915 .name = "i82550",
1916 .desc = "Intel i82550 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001917 .device = i82550,
1918 /* TODO: check device id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001919 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02001920 /* Revision ID: 0x0c, 0x0d, 0x0e. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001921 .revision = 0x0e,
Stefan Weil558c8632010-04-06 13:44:03 +02001922 /* TODO: check size of statistical counters. */
1923 .stats_size = 80,
1924 /* TODO: check extended tcb support. */
1925 .has_extended_tcb_support = true,
1926 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001927 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001928 .name = "i82551",
1929 .desc = "Intel i82551 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001930 .device = i82551,
Anthony Liguori40021f02011-12-04 12:22:06 -06001931 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02001932 /* Revision ID: 0x0f, 0x10. */
Anthony Liguori40021f02011-12-04 12:22:06 -06001933 .revision = 0x0f,
Stefan Weil558c8632010-04-06 13:44:03 +02001934 /* TODO: check size of statistical counters. */
1935 .stats_size = 80,
1936 .has_extended_tcb_support = true,
1937 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001938 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001939 .name = "i82557a",
1940 .desc = "Intel i82557A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001941 .device = i82557A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001942 .device_id = PCI_DEVICE_ID_INTEL_82557,
1943 .revision = 0x01,
Stefan Weil558c8632010-04-06 13:44:03 +02001944 .power_management = false,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001945 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001946 .name = "i82557b",
1947 .desc = "Intel i82557B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001948 .device = i82557B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001949 .device_id = PCI_DEVICE_ID_INTEL_82557,
1950 .revision = 0x02,
Stefan Weil558c8632010-04-06 13:44:03 +02001951 .power_management = false,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02001952 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001953 .name = "i82557c",
1954 .desc = "Intel i82557C Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001955 .device = i82557C,
Anthony Liguori40021f02011-12-04 12:22:06 -06001956 .device_id = PCI_DEVICE_ID_INTEL_82557,
1957 .revision = 0x03,
Stefan Weil558c8632010-04-06 13:44:03 +02001958 .power_management = false,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001959 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001960 .name = "i82558a",
1961 .desc = "Intel i82558A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001962 .device = i82558A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001963 .device_id = PCI_DEVICE_ID_INTEL_82557,
1964 .revision = 0x04,
Stefan Weil558c8632010-04-06 13:44:03 +02001965 .stats_size = 76,
1966 .has_extended_tcb_support = true,
1967 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001968 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001969 .name = "i82558b",
1970 .desc = "Intel i82558B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001971 .device = i82558B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001972 .device_id = PCI_DEVICE_ID_INTEL_82557,
1973 .revision = 0x05,
Stefan Weil558c8632010-04-06 13:44:03 +02001974 .stats_size = 76,
1975 .has_extended_tcb_support = true,
1976 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001977 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001978 .name = "i82559a",
1979 .desc = "Intel i82559A Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001980 .device = i82559A,
Anthony Liguori40021f02011-12-04 12:22:06 -06001981 .device_id = PCI_DEVICE_ID_INTEL_82557,
1982 .revision = 0x06,
Stefan Weil558c8632010-04-06 13:44:03 +02001983 .stats_size = 80,
1984 .has_extended_tcb_support = true,
1985 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001986 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001987 .name = "i82559b",
1988 .desc = "Intel i82559B Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001989 .device = i82559B,
Anthony Liguori40021f02011-12-04 12:22:06 -06001990 .device_id = PCI_DEVICE_ID_INTEL_82557,
1991 .revision = 0x07,
Stefan Weil558c8632010-04-06 13:44:03 +02001992 .stats_size = 80,
1993 .has_extended_tcb_support = true,
1994 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02001995 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001996 .name = "i82559c",
1997 .desc = "Intel i82559C Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02001998 .device = i82559C,
Anthony Liguori40021f02011-12-04 12:22:06 -06001999 .device_id = PCI_DEVICE_ID_INTEL_82557,
Stefan Weil558c8632010-04-06 13:44:03 +02002000#if 0
Anthony Liguori40021f02011-12-04 12:22:06 -06002001 .revision = 0x08,
Stefan Weil558c8632010-04-06 13:44:03 +02002002#endif
2003 /* TODO: Windows wants revision id 0x0c. */
Anthony Liguori40021f02011-12-04 12:22:06 -06002004 .revision = 0x0c,
Isaku Yamahataad035022011-05-25 10:58:00 +09002005#if EEPROM_SIZE > 0
Anthony Liguori40021f02011-12-04 12:22:06 -06002006 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
2007 .subsystem_id = 0x0040,
Isaku Yamahataad035022011-05-25 10:58:00 +09002008#endif
Stefan Weil558c8632010-04-06 13:44:03 +02002009 .stats_size = 80,
2010 .has_extended_tcb_support = true,
2011 .power_management = true,
Stefan Weilc4c270e2009-09-19 13:02:09 +02002012 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002013 .name = "i82559er",
2014 .desc = "Intel i82559ER Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02002015 .device = i82559ER,
Anthony Liguori40021f02011-12-04 12:22:06 -06002016 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2017 .revision = 0x09,
Stefan Weil558c8632010-04-06 13:44:03 +02002018 .stats_size = 80,
2019 .has_extended_tcb_support = true,
2020 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02002021 },{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002022 .name = "i82562",
2023 .desc = "Intel i82562 Ethernet",
Stefan Weil558c8632010-04-06 13:44:03 +02002024 .device = i82562,
2025 /* TODO: check device id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06002026 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
Stefan Weil558c8632010-04-06 13:44:03 +02002027 /* TODO: wrong revision id. */
Anthony Liguori40021f02011-12-04 12:22:06 -06002028 .revision = 0x0e,
Stefan Weil558c8632010-04-06 13:44:03 +02002029 .stats_size = 80,
2030 .has_extended_tcb_support = true,
2031 .power_management = true,
Stefan Weildb667a12010-04-06 13:44:04 +02002032 },{
2033 /* Toshiba Tecra 8200. */
Anthony Liguori39bffca2011-12-07 21:34:16 -06002034 .name = "i82801",
2035 .desc = "Intel i82801 Ethernet",
Stefan Weildb667a12010-04-06 13:44:04 +02002036 .device = i82801,
Anthony Liguori40021f02011-12-04 12:22:06 -06002037 .device_id = 0x2449,
2038 .revision = 0x03,
Stefan Weildb667a12010-04-06 13:44:04 +02002039 .stats_size = 80,
2040 .has_extended_tcb_support = true,
2041 .power_management = true,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +02002042 }
2043};
2044
Anthony Liguori40021f02011-12-04 12:22:06 -06002045static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2046{
2047 E100PCIDeviceInfo *info = NULL;
2048 int i;
2049
2050 /* This is admittedly awkward but also temporary. QOM allows for
2051 * parameterized typing and for subclassing both of which would suitable
2052 * handle what's going on here. But class_data is already being used as
2053 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2054 * right now. Once we merge the final QOM series, we can come back here and
2055 * do this in a much more elegant fashion.
2056 */
2057 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002058 if (strcmp(e100_devices[i].name, typename) == 0) {
Anthony Liguori40021f02011-12-04 12:22:06 -06002059 info = &e100_devices[i];
2060 break;
2061 }
2062 }
2063 assert(info != NULL);
2064
2065 return info;
2066}
2067
2068static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2069{
2070 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2071}
2072
Anthony Liguori39bffca2011-12-07 21:34:16 -06002073static Property e100_properties[] = {
2074 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2075 DEFINE_PROP_END_OF_LIST(),
2076};
2077
Anthony Liguori40021f02011-12-04 12:22:06 -06002078static void eepro100_class_init(ObjectClass *klass, void *data)
2079{
Anthony Liguori39bffca2011-12-07 21:34:16 -06002080 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06002081 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2082 E100PCIDeviceInfo *info;
2083
2084 info = eepro100_get_class_by_name(object_class_get_name(klass));
2085
Anthony Liguori39bffca2011-12-07 21:34:16 -06002086 dc->props = e100_properties;
2087 dc->desc = info->desc;
Anthony Liguori40021f02011-12-04 12:22:06 -06002088 k->vendor_id = PCI_VENDOR_ID_INTEL;
2089 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2090 k->romfile = "pxe-eepro100.rom";
2091 k->init = e100_nic_init;
2092 k->exit = pci_nic_uninit;
2093 k->device_id = info->device_id;
2094 k->revision = info->revision;
2095 k->subsystem_vendor_id = info->subsystem_vendor_id;
2096 k->subsystem_id = info->subsystem_id;
2097}
2098
Andreas Färber83f7d432012-02-09 15:20:55 +01002099static void eepro100_register_types(void)
Paul Brook9d07d752009-05-14 22:35:07 +01002100{
Stefan Weil558c8632010-04-06 13:44:03 +02002101 size_t i;
2102 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
Anthony Liguori39bffca2011-12-07 21:34:16 -06002103 TypeInfo type_info = {};
2104 E100PCIDeviceInfo *info = &e100_devices[i];
Anthony Liguori40021f02011-12-04 12:22:06 -06002105
Anthony Liguori39bffca2011-12-07 21:34:16 -06002106 type_info.name = info->name;
2107 type_info.parent = TYPE_PCI_DEVICE;
2108 type_info.class_init = eepro100_class_init;
2109 type_info.instance_size = sizeof(EEPRO100State);
Anthony Liguori40021f02011-12-04 12:22:06 -06002110
Anthony Liguori39bffca2011-12-07 21:34:16 -06002111 type_register(&type_info);
Stefan Weil558c8632010-04-06 13:44:03 +02002112 }
Paul Brook9d07d752009-05-14 22:35:07 +01002113}
2114
Andreas Färber83f7d432012-02-09 15:20:55 +01002115type_init(eepro100_register_types)